xref: /netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/qcom,gcc-msm8996.h (revision 4effb9b18f024fdac2e35b6e9f6ec111f2d026be)
1 /*	$NetBSD: qcom,gcc-msm8996.h,v 1.1.1.4 2020/01/03 14:33:04 skrll Exp $	*/
2 
3 /* SPDX-License-Identifier: GPL-2.0-only */
4 /*
5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
9 #define _DT_BINDINGS_CLK_MSM_GCC_8996_H
10 
11 #define GPLL0_EARLY						0
12 #define GPLL0							1
13 #define GPLL1_EARLY						2
14 #define GPLL1							3
15 #define GPLL2_EARLY						4
16 #define GPLL2							5
17 #define GPLL3_EARLY						6
18 #define GPLL3							7
19 #define GPLL4_EARLY						8
20 #define GPLL4							9
21 #define SYSTEM_NOC_CLK_SRC					10
22 #define CONFIG_NOC_CLK_SRC					11
23 #define PERIPH_NOC_CLK_SRC					12
24 #define MMSS_BIMC_GFX_CLK_SRC					13
25 #define USB30_MASTER_CLK_SRC					14
26 #define USB30_MOCK_UTMI_CLK_SRC					15
27 #define USB3_PHY_AUX_CLK_SRC					16
28 #define USB20_MASTER_CLK_SRC					17
29 #define USB20_MOCK_UTMI_CLK_SRC					18
30 #define SDCC1_APPS_CLK_SRC					19
31 #define SDCC1_ICE_CORE_CLK_SRC					20
32 #define SDCC2_APPS_CLK_SRC					21
33 #define SDCC3_APPS_CLK_SRC					22
34 #define SDCC4_APPS_CLK_SRC					23
35 #define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
36 #define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
37 #define BLSP1_UART1_APPS_CLK_SRC				26
38 #define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
39 #define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
40 #define BLSP1_UART2_APPS_CLK_SRC				29
41 #define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
42 #define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
43 #define BLSP1_UART3_APPS_CLK_SRC				32
44 #define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
45 #define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
46 #define BLSP1_UART4_APPS_CLK_SRC				35
47 #define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
48 #define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
49 #define BLSP1_UART5_APPS_CLK_SRC				38
50 #define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
51 #define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
52 #define BLSP1_UART6_APPS_CLK_SRC				41
53 #define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
54 #define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
55 #define BLSP2_UART1_APPS_CLK_SRC				44
56 #define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
57 #define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
58 #define BLSP2_UART2_APPS_CLK_SRC				47
59 #define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
60 #define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
61 #define BLSP2_UART3_APPS_CLK_SRC				50
62 #define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
63 #define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
64 #define BLSP2_UART4_APPS_CLK_SRC				53
65 #define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
66 #define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
67 #define BLSP2_UART5_APPS_CLK_SRC				56
68 #define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
69 #define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
70 #define BLSP2_UART6_APPS_CLK_SRC				59
71 #define PDM2_CLK_SRC						60
72 #define TSIF_REF_CLK_SRC					61
73 #define CE1_CLK_SRC						62
74 #define GCC_SLEEP_CLK_SRC					63
75 #define BIMC_CLK_SRC						64
76 #define HMSS_AHB_CLK_SRC					65
77 #define BIMC_HMSS_AXI_CLK_SRC					66
78 #define HMSS_RBCPR_CLK_SRC					67
79 #define HMSS_GPLL0_CLK_SRC					68
80 #define GP1_CLK_SRC						69
81 #define GP2_CLK_SRC						70
82 #define GP3_CLK_SRC						71
83 #define PCIE_AUX_CLK_SRC					72
84 #define UFS_AXI_CLK_SRC						73
85 #define UFS_ICE_CORE_CLK_SRC					74
86 #define QSPI_SER_CLK_SRC					75
87 #define GCC_SYS_NOC_AXI_CLK					76
88 #define GCC_SYS_NOC_HMSS_AHB_CLK				77
89 #define GCC_SNOC_CNOC_AHB_CLK					78
90 #define GCC_SNOC_PNOC_AHB_CLK					79
91 #define GCC_SYS_NOC_AT_CLK					80
92 #define GCC_SYS_NOC_USB3_AXI_CLK				81
93 #define GCC_SYS_NOC_UFS_AXI_CLK					82
94 #define GCC_CFG_NOC_AHB_CLK					83
95 #define GCC_PERIPH_NOC_AHB_CLK					84
96 #define GCC_PERIPH_NOC_USB20_AHB_CLK				85
97 #define GCC_TIC_CLK						86
98 #define GCC_IMEM_AXI_CLK					87
99 #define GCC_MMSS_SYS_NOC_AXI_CLK				88
100 #define GCC_MMSS_NOC_CFG_AHB_CLK				89
101 #define GCC_MMSS_BIMC_GFX_CLK					90
102 #define GCC_USB30_MASTER_CLK					91
103 #define GCC_USB30_SLEEP_CLK					92
104 #define GCC_USB30_MOCK_UTMI_CLK					93
105 #define GCC_USB3_PHY_AUX_CLK					94
106 #define GCC_USB3_PHY_PIPE_CLK					95
107 #define GCC_USB20_MASTER_CLK					96
108 #define GCC_USB20_SLEEP_CLK					97
109 #define GCC_USB20_MOCK_UTMI_CLK					98
110 #define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
111 #define GCC_SDCC1_APPS_CLK					100
112 #define GCC_SDCC1_AHB_CLK					101
113 #define GCC_SDCC1_ICE_CORE_CLK					102
114 #define GCC_SDCC2_APPS_CLK					103
115 #define GCC_SDCC2_AHB_CLK					104
116 #define GCC_SDCC3_APPS_CLK					105
117 #define GCC_SDCC3_AHB_CLK					106
118 #define GCC_SDCC4_APPS_CLK					107
119 #define GCC_SDCC4_AHB_CLK					108
120 #define GCC_BLSP1_AHB_CLK					109
121 #define GCC_BLSP1_SLEEP_CLK					110
122 #define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
123 #define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
124 #define GCC_BLSP1_UART1_APPS_CLK				113
125 #define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
126 #define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
127 #define GCC_BLSP1_UART2_APPS_CLK				116
128 #define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
129 #define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
130 #define GCC_BLSP1_UART3_APPS_CLK				119
131 #define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
132 #define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
133 #define GCC_BLSP1_UART4_APPS_CLK				122
134 #define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
135 #define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
136 #define GCC_BLSP1_UART5_APPS_CLK				125
137 #define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
138 #define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
139 #define GCC_BLSP1_UART6_APPS_CLK				128
140 #define GCC_BLSP2_AHB_CLK					129
141 #define GCC_BLSP2_SLEEP_CLK					130
142 #define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
143 #define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
144 #define GCC_BLSP2_UART1_APPS_CLK				133
145 #define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
146 #define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
147 #define GCC_BLSP2_UART2_APPS_CLK				136
148 #define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
149 #define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
150 #define GCC_BLSP2_UART3_APPS_CLK				139
151 #define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
152 #define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
153 #define GCC_BLSP2_UART4_APPS_CLK				142
154 #define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
155 #define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
156 #define GCC_BLSP2_UART5_APPS_CLK				145
157 #define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
158 #define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
159 #define GCC_BLSP2_UART6_APPS_CLK				148
160 #define GCC_PDM_AHB_CLK						149
161 #define GCC_PDM_XO4_CLK						150
162 #define GCC_PDM2_CLK						151
163 #define GCC_PRNG_AHB_CLK					152
164 #define GCC_TSIF_AHB_CLK					153
165 #define GCC_TSIF_REF_CLK					154
166 #define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
167 #define GCC_TCSR_AHB_CLK					156
168 #define GCC_BOOT_ROM_AHB_CLK					157
169 #define GCC_MSG_RAM_AHB_CLK					158
170 #define GCC_TLMM_AHB_CLK					159
171 #define GCC_TLMM_CLK						160
172 #define GCC_MPM_AHB_CLK						161
173 #define GCC_SPMI_SER_CLK					162
174 #define GCC_SPMI_CNOC_AHB_CLK					163
175 #define GCC_CE1_CLK						164
176 #define GCC_CE1_AXI_CLK						165
177 #define GCC_CE1_AHB_CLK						166
178 #define GCC_BIMC_HMSS_AXI_CLK					167
179 #define GCC_BIMC_GFX_CLK					168
180 #define GCC_HMSS_AHB_CLK					169
181 #define GCC_HMSS_SLV_AXI_CLK					170
182 #define GCC_HMSS_MSTR_AXI_CLK					171
183 #define GCC_HMSS_RBCPR_CLK					172
184 #define GCC_GP1_CLK						173
185 #define GCC_GP2_CLK						174
186 #define GCC_GP3_CLK						175
187 #define GCC_PCIE_0_SLV_AXI_CLK					176
188 #define GCC_PCIE_0_MSTR_AXI_CLK					177
189 #define GCC_PCIE_0_CFG_AHB_CLK					178
190 #define GCC_PCIE_0_AUX_CLK					179
191 #define GCC_PCIE_0_PIPE_CLK					180
192 #define GCC_PCIE_1_SLV_AXI_CLK					181
193 #define GCC_PCIE_1_MSTR_AXI_CLK					182
194 #define GCC_PCIE_1_CFG_AHB_CLK					183
195 #define GCC_PCIE_1_AUX_CLK					184
196 #define GCC_PCIE_1_PIPE_CLK					185
197 #define GCC_PCIE_2_SLV_AXI_CLK					186
198 #define GCC_PCIE_2_MSTR_AXI_CLK					187
199 #define GCC_PCIE_2_CFG_AHB_CLK					188
200 #define GCC_PCIE_2_AUX_CLK					189
201 #define GCC_PCIE_2_PIPE_CLK					190
202 #define GCC_PCIE_PHY_CFG_AHB_CLK				191
203 #define GCC_PCIE_PHY_AUX_CLK					192
204 #define GCC_UFS_AXI_CLK						193
205 #define GCC_UFS_AHB_CLK						194
206 #define GCC_UFS_TX_CFG_CLK					195
207 #define GCC_UFS_RX_CFG_CLK					196
208 #define GCC_UFS_TX_SYMBOL_0_CLK					197
209 #define GCC_UFS_RX_SYMBOL_0_CLK					198
210 #define GCC_UFS_RX_SYMBOL_1_CLK					199
211 #define GCC_UFS_UNIPRO_CORE_CLK					200
212 #define GCC_UFS_ICE_CORE_CLK					201
213 #define GCC_UFS_SYS_CLK_CORE_CLK				202
214 #define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
215 #define GCC_AGGRE0_SNOC_AXI_CLK					204
216 #define GCC_AGGRE0_CNOC_AHB_CLK					205
217 #define GCC_SMMU_AGGRE0_AXI_CLK					206
218 #define GCC_SMMU_AGGRE0_AHB_CLK					207
219 #define GCC_AGGRE1_PNOC_AHB_CLK					208
220 #define GCC_AGGRE2_UFS_AXI_CLK					209
221 #define GCC_AGGRE2_USB3_AXI_CLK					210
222 #define GCC_QSPI_AHB_CLK					211
223 #define GCC_QSPI_SER_CLK					212
224 #define GCC_USB3_CLKREF_CLK					213
225 #define GCC_HDMI_CLKREF_CLK					214
226 #define GCC_UFS_CLKREF_CLK					215
227 #define GCC_PCIE_CLKREF_CLK					216
228 #define GCC_RX2_USB2_CLKREF_CLK					217
229 #define GCC_RX1_USB2_CLKREF_CLK					218
230 #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			219
231 #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			220
232 #define GCC_EDP_CLKREF_CLK					221
233 #define GCC_MSS_CFG_AHB_CLK					222
234 #define GCC_MSS_Q6_BIMC_AXI_CLK					223
235 #define GCC_MSS_SNOC_AXI_CLK					224
236 #define GCC_MSS_MNOC_BIMC_AXI_CLK				225
237 #define GCC_DCC_AHB_CLK						226
238 #define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				227
239 #define GCC_MMSS_GPLL0_DIV_CLK					228
240 #define GCC_MSS_GPLL0_DIV_CLK					229
241 
242 #define GCC_SYSTEM_NOC_BCR					0
243 #define GCC_CONFIG_NOC_BCR					1
244 #define GCC_PERIPH_NOC_BCR					2
245 #define GCC_IMEM_BCR						3
246 #define GCC_MMSS_BCR						4
247 #define GCC_PIMEM_BCR						5
248 #define GCC_QDSS_BCR						6
249 #define GCC_USB_30_BCR						7
250 #define GCC_USB_20_BCR						8
251 #define GCC_QUSB2PHY_PRIM_BCR					9
252 #define GCC_QUSB2PHY_SEC_BCR					10
253 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				11
254 #define GCC_SDCC1_BCR						12
255 #define GCC_SDCC2_BCR						13
256 #define GCC_SDCC3_BCR						14
257 #define GCC_SDCC4_BCR						15
258 #define GCC_BLSP1_BCR						16
259 #define GCC_BLSP1_QUP1_BCR					17
260 #define GCC_BLSP1_UART1_BCR					18
261 #define GCC_BLSP1_QUP2_BCR					19
262 #define GCC_BLSP1_UART2_BCR					20
263 #define GCC_BLSP1_QUP3_BCR					21
264 #define GCC_BLSP1_UART3_BCR					22
265 #define GCC_BLSP1_QUP4_BCR					23
266 #define GCC_BLSP1_UART4_BCR					24
267 #define GCC_BLSP1_QUP5_BCR					25
268 #define GCC_BLSP1_UART5_BCR					26
269 #define GCC_BLSP1_QUP6_BCR					27
270 #define GCC_BLSP1_UART6_BCR					28
271 #define GCC_BLSP2_BCR						29
272 #define GCC_BLSP2_QUP1_BCR					30
273 #define GCC_BLSP2_UART1_BCR					31
274 #define GCC_BLSP2_QUP2_BCR					32
275 #define GCC_BLSP2_UART2_BCR					33
276 #define GCC_BLSP2_QUP3_BCR					34
277 #define GCC_BLSP2_UART3_BCR					35
278 #define GCC_BLSP2_QUP4_BCR					36
279 #define GCC_BLSP2_UART4_BCR					37
280 #define GCC_BLSP2_QUP5_BCR					38
281 #define GCC_BLSP2_UART5_BCR					39
282 #define GCC_BLSP2_QUP6_BCR					40
283 #define GCC_BLSP2_UART6_BCR					41
284 #define GCC_PDM_BCR						42
285 #define GCC_PRNG_BCR						43
286 #define GCC_TSIF_BCR						44
287 #define GCC_TCSR_BCR						45
288 #define GCC_BOOT_ROM_BCR					46
289 #define GCC_MSG_RAM_BCR						47
290 #define GCC_TLMM_BCR						48
291 #define GCC_MPM_BCR						49
292 #define GCC_SEC_CTRL_BCR					50
293 #define GCC_SPMI_BCR						51
294 #define GCC_SPDM_BCR						52
295 #define GCC_CE1_BCR						53
296 #define GCC_BIMC_BCR						54
297 #define GCC_SNOC_BUS_TIMEOUT0_BCR				55
298 #define GCC_SNOC_BUS_TIMEOUT2_BCR				56
299 #define GCC_SNOC_BUS_TIMEOUT1_BCR				57
300 #define GCC_SNOC_BUS_TIMEOUT3_BCR				58
301 #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				59
302 #define GCC_PNOC_BUS_TIMEOUT0_BCR				60
303 #define GCC_PNOC_BUS_TIMEOUT1_BCR				61
304 #define GCC_PNOC_BUS_TIMEOUT2_BCR				62
305 #define GCC_PNOC_BUS_TIMEOUT3_BCR				63
306 #define GCC_PNOC_BUS_TIMEOUT4_BCR				64
307 #define GCC_CNOC_BUS_TIMEOUT0_BCR				65
308 #define GCC_CNOC_BUS_TIMEOUT1_BCR				66
309 #define GCC_CNOC_BUS_TIMEOUT2_BCR				67
310 #define GCC_CNOC_BUS_TIMEOUT3_BCR				68
311 #define GCC_CNOC_BUS_TIMEOUT4_BCR				69
312 #define GCC_CNOC_BUS_TIMEOUT5_BCR				70
313 #define GCC_CNOC_BUS_TIMEOUT6_BCR				71
314 #define GCC_CNOC_BUS_TIMEOUT7_BCR				72
315 #define GCC_CNOC_BUS_TIMEOUT8_BCR				73
316 #define GCC_CNOC_BUS_TIMEOUT9_BCR				74
317 #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				75
318 #define GCC_APB2JTAG_BCR					76
319 #define GCC_RBCPR_CX_BCR					77
320 #define GCC_RBCPR_MX_BCR					78
321 #define GCC_PCIE_0_BCR						79
322 #define GCC_PCIE_0_PHY_BCR					80
323 #define GCC_PCIE_1_BCR						81
324 #define GCC_PCIE_1_PHY_BCR					82
325 #define GCC_PCIE_2_BCR						83
326 #define GCC_PCIE_2_PHY_BCR					84
327 #define GCC_PCIE_PHY_BCR					85
328 #define GCC_DCD_BCR						86
329 #define GCC_OBT_ODT_BCR						87
330 #define GCC_UFS_BCR						88
331 #define GCC_SSC_BCR						89
332 #define GCC_VS_BCR						90
333 #define GCC_AGGRE0_NOC_BCR					91
334 #define GCC_AGGRE1_NOC_BCR					92
335 #define GCC_AGGRE2_NOC_BCR					93
336 #define GCC_DCC_BCR						94
337 #define GCC_IPA_BCR						95
338 #define GCC_QSPI_BCR						96
339 #define GCC_SKL_BCR						97
340 #define GCC_MSMPU_BCR						98
341 #define GCC_MSS_Q6_BCR						99
342 #define GCC_QREFS_VBG_CAL_BCR					100
343 #define GCC_PCIE_PHY_COM_BCR					101
344 #define GCC_PCIE_PHY_COM_NOCSR_BCR				102
345 #define GCC_USB3_PHY_BCR					103
346 #define GCC_USB3PHY_PHY_BCR					104
347 #define GCC_MSS_RESTART						105
348 
349 
350 /* Indexes for GDSCs */
351 #define AGGRE0_NOC_GDSC			0
352 #define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
353 #define HLOS1_VOTE_LPASS_ADSP_GDSC	2
354 #define HLOS1_VOTE_LPASS_CORE_GDSC	3
355 #define USB30_GDSC			4
356 #define PCIE0_GDSC			5
357 #define PCIE1_GDSC			6
358 #define PCIE2_GDSC			7
359 #define UFS_GDSC			8
360 
361 #endif
362