| /llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 111 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate() argument
38 computeTargetABI(const Triple & TT,const FeatureBitset & FeatureBits,StringRef ABIName) computeTargetABI() argument
122 parseFeatureBits(bool IsRV64,const FeatureBitset & FeatureBits) parseFeatureBits() argument
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| /llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchBaseInfo.cpp | 72 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, in computeTargetABI() argument
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| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 92 FeatureBitset FeatureBits; // Feature bits for current CPU + FS global() variable
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| /llvm-project/clang/lib/Basic/Targets/ |
| H A D | AArch64.cpp | 1084 __anond56891b00102(StringRef FeatString, std::vector<std::string> &Features, llvm::AArch64::ExtensionSet &FeatureBits) parseTargetAttr() argument
1103 llvm::AArch64::ExtensionSet FeatureBits; parseTargetAttr() local
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| /llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 215 const FeatureBitset &FeatureBits = in DecodeGPRPairRegisterClass() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 164 FeatureBitset FeatureBits = getFeatureBits(); initializeSubtargetDependencies() local
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| /llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 922 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); AddThumbPredicate() local
2550 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); DecodeHINTInstruction() local
2795 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); DecodeSETPANInstruction() local
4834 const FeatureBitset &FeatureBits = DecodeThumbTableBranch() local
4979 const FeatureBitset &FeatureBits = DecodeMSRMask() local
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| /llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 912 const FeatureBitset &FeatureBits = STI.getFeatureBits(); printMSRMaskOperand() local
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| /llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 267 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); popFeatureBits() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5423 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); getMClassRegisterMask() local
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| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 473 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch() local
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