1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT 10 11 #include <cstddef> 12 13 #include "lldb/lldb-defines.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-private.h" 16 17 #include "Utility/ARM_DWARF_Registers.h" 18 #include "Utility/ARM_ehframe_Registers.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 #ifndef GPR_OFFSET 24 #error GPR_OFFSET must be defined before including this header file 25 #endif 26 27 #ifndef FPU_OFFSET 28 #error FPU_OFFSET must be defined before including this header file 29 #endif 30 31 #ifndef FPSCR_OFFSET 32 #error FPSCR_OFFSET must be defined before including this header file 33 #endif 34 35 #ifndef EXC_OFFSET 36 #error EXC_OFFSET_NAME must be defined before including this header file 37 #endif 38 39 #ifndef DEFINE_DBG 40 #error DEFINE_DBG must be defined before including this header file 41 #endif 42 43 enum { 44 gpr_r0 = 0, 45 gpr_r1, 46 gpr_r2, 47 gpr_r3, 48 gpr_r4, 49 gpr_r5, 50 gpr_r6, 51 gpr_r7, 52 gpr_r8, 53 gpr_r9, 54 gpr_r10, 55 gpr_r11, 56 gpr_r12, 57 gpr_r13, 58 gpr_sp = gpr_r13, 59 gpr_r14, 60 gpr_lr = gpr_r14, 61 gpr_r15, 62 gpr_pc = gpr_r15, 63 gpr_cpsr, 64 65 fpu_s0, 66 fpu_s1, 67 fpu_s2, 68 fpu_s3, 69 fpu_s4, 70 fpu_s5, 71 fpu_s6, 72 fpu_s7, 73 fpu_s8, 74 fpu_s9, 75 fpu_s10, 76 fpu_s11, 77 fpu_s12, 78 fpu_s13, 79 fpu_s14, 80 fpu_s15, 81 fpu_s16, 82 fpu_s17, 83 fpu_s18, 84 fpu_s19, 85 fpu_s20, 86 fpu_s21, 87 fpu_s22, 88 fpu_s23, 89 fpu_s24, 90 fpu_s25, 91 fpu_s26, 92 fpu_s27, 93 fpu_s28, 94 fpu_s29, 95 fpu_s30, 96 fpu_s31, 97 fpu_fpscr, 98 99 fpu_d0, 100 fpu_d1, 101 fpu_d2, 102 fpu_d3, 103 fpu_d4, 104 fpu_d5, 105 fpu_d6, 106 fpu_d7, 107 fpu_d8, 108 fpu_d9, 109 fpu_d10, 110 fpu_d11, 111 fpu_d12, 112 fpu_d13, 113 fpu_d14, 114 fpu_d15, 115 fpu_d16, 116 fpu_d17, 117 fpu_d18, 118 fpu_d19, 119 fpu_d20, 120 fpu_d21, 121 fpu_d22, 122 fpu_d23, 123 fpu_d24, 124 fpu_d25, 125 fpu_d26, 126 fpu_d27, 127 fpu_d28, 128 fpu_d29, 129 fpu_d30, 130 fpu_d31, 131 132 fpu_q0, 133 fpu_q1, 134 fpu_q2, 135 fpu_q3, 136 fpu_q4, 137 fpu_q5, 138 fpu_q6, 139 fpu_q7, 140 fpu_q8, 141 fpu_q9, 142 fpu_q10, 143 fpu_q11, 144 fpu_q12, 145 fpu_q13, 146 fpu_q14, 147 fpu_q15, 148 149 exc_exception, 150 exc_fsr, 151 exc_far, 152 153 dbg_bvr0, 154 dbg_bvr1, 155 dbg_bvr2, 156 dbg_bvr3, 157 dbg_bvr4, 158 dbg_bvr5, 159 dbg_bvr6, 160 dbg_bvr7, 161 dbg_bvr8, 162 dbg_bvr9, 163 dbg_bvr10, 164 dbg_bvr11, 165 dbg_bvr12, 166 dbg_bvr13, 167 dbg_bvr14, 168 dbg_bvr15, 169 170 dbg_bcr0, 171 dbg_bcr1, 172 dbg_bcr2, 173 dbg_bcr3, 174 dbg_bcr4, 175 dbg_bcr5, 176 dbg_bcr6, 177 dbg_bcr7, 178 dbg_bcr8, 179 dbg_bcr9, 180 dbg_bcr10, 181 dbg_bcr11, 182 dbg_bcr12, 183 dbg_bcr13, 184 dbg_bcr14, 185 dbg_bcr15, 186 187 dbg_wvr0, 188 dbg_wvr1, 189 dbg_wvr2, 190 dbg_wvr3, 191 dbg_wvr4, 192 dbg_wvr5, 193 dbg_wvr6, 194 dbg_wvr7, 195 dbg_wvr8, 196 dbg_wvr9, 197 dbg_wvr10, 198 dbg_wvr11, 199 dbg_wvr12, 200 dbg_wvr13, 201 dbg_wvr14, 202 dbg_wvr15, 203 204 dbg_wcr0, 205 dbg_wcr1, 206 dbg_wcr2, 207 dbg_wcr3, 208 dbg_wcr4, 209 dbg_wcr5, 210 dbg_wcr6, 211 dbg_wcr7, 212 dbg_wcr8, 213 dbg_wcr9, 214 dbg_wcr10, 215 dbg_wcr11, 216 dbg_wcr12, 217 dbg_wcr13, 218 dbg_wcr14, 219 dbg_wcr15, 220 221 k_num_registers 222 }; 223 224 static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; 225 static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; 226 static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; 227 static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; 228 static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; 229 static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; 230 static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; 231 static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; 232 static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; 233 static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; 234 static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; 235 static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; 236 static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; 237 static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; 238 static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; 239 static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; 240 static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; 241 static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; 242 static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; 243 static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; 244 static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; 245 static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; 246 static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; 247 static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; 248 static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; 249 static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; 250 static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; 251 static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; 252 static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; 253 static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; 254 static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; 255 static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; 256 257 static uint32_t g_d0_invalidates[] = {fpu_q0, fpu_s0, fpu_s1, 258 LLDB_INVALID_REGNUM}; 259 static uint32_t g_d1_invalidates[] = {fpu_q0, fpu_s2, fpu_s3, 260 LLDB_INVALID_REGNUM}; 261 static uint32_t g_d2_invalidates[] = {fpu_q1, fpu_s4, fpu_s5, 262 LLDB_INVALID_REGNUM}; 263 static uint32_t g_d3_invalidates[] = {fpu_q1, fpu_s6, fpu_s7, 264 LLDB_INVALID_REGNUM}; 265 static uint32_t g_d4_invalidates[] = {fpu_q2, fpu_s8, fpu_s9, 266 LLDB_INVALID_REGNUM}; 267 static uint32_t g_d5_invalidates[] = {fpu_q2, fpu_s10, fpu_s11, 268 LLDB_INVALID_REGNUM}; 269 static uint32_t g_d6_invalidates[] = {fpu_q3, fpu_s12, fpu_s13, 270 LLDB_INVALID_REGNUM}; 271 static uint32_t g_d7_invalidates[] = {fpu_q3, fpu_s14, fpu_s15, 272 LLDB_INVALID_REGNUM}; 273 static uint32_t g_d8_invalidates[] = {fpu_q4, fpu_s16, fpu_s17, 274 LLDB_INVALID_REGNUM}; 275 static uint32_t g_d9_invalidates[] = {fpu_q4, fpu_s18, fpu_s19, 276 LLDB_INVALID_REGNUM}; 277 static uint32_t g_d10_invalidates[] = {fpu_q5, fpu_s20, fpu_s21, 278 LLDB_INVALID_REGNUM}; 279 static uint32_t g_d11_invalidates[] = {fpu_q5, fpu_s22, fpu_s23, 280 LLDB_INVALID_REGNUM}; 281 static uint32_t g_d12_invalidates[] = {fpu_q6, fpu_s24, fpu_s25, 282 LLDB_INVALID_REGNUM}; 283 static uint32_t g_d13_invalidates[] = {fpu_q6, fpu_s26, fpu_s27, 284 LLDB_INVALID_REGNUM}; 285 static uint32_t g_d14_invalidates[] = {fpu_q7, fpu_s28, fpu_s29, 286 LLDB_INVALID_REGNUM}; 287 static uint32_t g_d15_invalidates[] = {fpu_q7, fpu_s30, fpu_s31, 288 LLDB_INVALID_REGNUM}; 289 static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; 290 static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; 291 static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; 292 static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; 293 static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; 294 static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; 295 static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; 296 static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; 297 static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; 298 static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; 299 static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; 300 static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; 301 static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; 302 static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; 303 static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; 304 static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; 305 306 static uint32_t g_q0_invalidates[] = { 307 fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM}; 308 static uint32_t g_q1_invalidates[] = { 309 fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM}; 310 static uint32_t g_q2_invalidates[] = { 311 fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM}; 312 static uint32_t g_q3_invalidates[] = { 313 fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM}; 314 static uint32_t g_q4_invalidates[] = { 315 fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM}; 316 static uint32_t g_q5_invalidates[] = { 317 fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM}; 318 static uint32_t g_q6_invalidates[] = { 319 fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM}; 320 static uint32_t g_q7_invalidates[] = { 321 fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM}; 322 static uint32_t g_q8_invalidates[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM}; 323 static uint32_t g_q9_invalidates[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM}; 324 static uint32_t g_q10_invalidates[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM}; 325 static uint32_t g_q11_invalidates[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM}; 326 static uint32_t g_q12_invalidates[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM}; 327 static uint32_t g_q13_invalidates[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; 328 static uint32_t g_q14_invalidates[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; 329 static uint32_t g_q15_invalidates[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; 330 331 static uint32_t g_q0_contained[] = {fpu_q0, LLDB_INVALID_REGNUM}; 332 static uint32_t g_q1_contained[] = {fpu_q1, LLDB_INVALID_REGNUM}; 333 static uint32_t g_q2_contained[] = {fpu_q2, LLDB_INVALID_REGNUM}; 334 static uint32_t g_q3_contained[] = {fpu_q3, LLDB_INVALID_REGNUM}; 335 static uint32_t g_q4_contained[] = {fpu_q4, LLDB_INVALID_REGNUM}; 336 static uint32_t g_q5_contained[] = {fpu_q5, LLDB_INVALID_REGNUM}; 337 static uint32_t g_q6_contained[] = {fpu_q6, LLDB_INVALID_REGNUM}; 338 static uint32_t g_q7_contained[] = {fpu_q7, LLDB_INVALID_REGNUM}; 339 static uint32_t g_q8_contained[] = {fpu_q8, LLDB_INVALID_REGNUM}; 340 static uint32_t g_q9_contained[] = {fpu_q9, LLDB_INVALID_REGNUM}; 341 static uint32_t g_q10_contained[] = {fpu_q10, LLDB_INVALID_REGNUM}; 342 static uint32_t g_q11_contained[] = {fpu_q11, LLDB_INVALID_REGNUM}; 343 static uint32_t g_q12_contained[] = {fpu_q12, LLDB_INVALID_REGNUM}; 344 static uint32_t g_q13_contained[] = {fpu_q13, LLDB_INVALID_REGNUM}; 345 static uint32_t g_q14_contained[] = {fpu_q14, LLDB_INVALID_REGNUM}; 346 static uint32_t g_q15_contained[] = {fpu_q15, LLDB_INVALID_REGNUM}; 347 348 #define FPU_REG(name, size, offset, qreg) \ 349 { \ 350 #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \ 351 {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ 352 LLDB_INVALID_REGNUM, fpu_##name }, \ 353 g_##qreg##_contained, g_##name##_invalidates, nullptr, \ 354 } 355 356 #define FPU_QREG(name, offset) \ 357 { \ 358 #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \ 359 eFormatVectorOfUInt8, \ 360 {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ 361 LLDB_INVALID_REGNUM, fpu_##name }, \ 362 nullptr, g_##name##_invalidates, nullptr, \ 363 } 364 365 static RegisterInfo g_register_infos_arm[] = { 366 { 367 "r0", 368 nullptr, 369 4, 370 GPR_OFFSET(0), 371 eEncodingUint, 372 eFormatHex, 373 {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, 374 gpr_r0}, 375 nullptr, 376 nullptr, 377 nullptr, 378 }, 379 { 380 "r1", 381 nullptr, 382 4, 383 GPR_OFFSET(1), 384 eEncodingUint, 385 eFormatHex, 386 {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, 387 gpr_r1}, 388 nullptr, 389 nullptr, 390 nullptr, 391 }, 392 { 393 "r2", 394 nullptr, 395 4, 396 GPR_OFFSET(2), 397 eEncodingUint, 398 eFormatHex, 399 {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, 400 gpr_r2}, 401 nullptr, 402 nullptr, 403 nullptr, 404 }, 405 { 406 "r3", 407 nullptr, 408 4, 409 GPR_OFFSET(3), 410 eEncodingUint, 411 eFormatHex, 412 {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, 413 gpr_r3}, 414 nullptr, 415 nullptr, 416 nullptr, 417 }, 418 { 419 "r4", 420 nullptr, 421 4, 422 GPR_OFFSET(4), 423 eEncodingUint, 424 eFormatHex, 425 {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 426 gpr_r4}, 427 nullptr, 428 nullptr, 429 nullptr, 430 }, 431 { 432 "r5", 433 nullptr, 434 4, 435 GPR_OFFSET(5), 436 eEncodingUint, 437 eFormatHex, 438 {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 439 gpr_r5}, 440 nullptr, 441 nullptr, 442 nullptr, 443 }, 444 { 445 "r6", 446 nullptr, 447 4, 448 GPR_OFFSET(6), 449 eEncodingUint, 450 eFormatHex, 451 {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 452 gpr_r6}, 453 nullptr, 454 nullptr, 455 nullptr, 456 }, 457 { 458 "r7", 459 nullptr, 460 4, 461 GPR_OFFSET(7), 462 eEncodingUint, 463 eFormatHex, 464 {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 465 gpr_r7}, 466 nullptr, 467 nullptr, 468 nullptr, 469 }, 470 { 471 "r8", 472 nullptr, 473 4, 474 GPR_OFFSET(8), 475 eEncodingUint, 476 eFormatHex, 477 {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 478 gpr_r8}, 479 nullptr, 480 nullptr, 481 nullptr, 482 }, 483 { 484 "r9", 485 nullptr, 486 4, 487 GPR_OFFSET(9), 488 eEncodingUint, 489 eFormatHex, 490 {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 491 gpr_r9}, 492 nullptr, 493 nullptr, 494 nullptr, 495 }, 496 { 497 "r10", 498 nullptr, 499 4, 500 GPR_OFFSET(10), 501 eEncodingUint, 502 eFormatHex, 503 {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 504 gpr_r10}, 505 nullptr, 506 nullptr, 507 nullptr, 508 }, 509 { 510 "r11", 511 nullptr, 512 4, 513 GPR_OFFSET(11), 514 eEncodingUint, 515 eFormatHex, 516 {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 517 gpr_r11}, 518 nullptr, 519 nullptr, 520 nullptr, 521 }, 522 { 523 "r12", 524 nullptr, 525 4, 526 GPR_OFFSET(12), 527 eEncodingUint, 528 eFormatHex, 529 {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 530 gpr_r12}, 531 nullptr, 532 nullptr, 533 nullptr, 534 }, 535 { 536 "sp", 537 "r13", 538 4, 539 GPR_OFFSET(13), 540 eEncodingUint, 541 eFormatHex, 542 {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 543 gpr_sp}, 544 nullptr, 545 nullptr, 546 nullptr, 547 }, 548 { 549 "lr", 550 "r14", 551 4, 552 GPR_OFFSET(14), 553 eEncodingUint, 554 eFormatHex, 555 {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 556 gpr_lr}, 557 nullptr, 558 nullptr, 559 nullptr, 560 }, 561 { 562 "pc", 563 "r15", 564 4, 565 GPR_OFFSET(15), 566 eEncodingUint, 567 eFormatHex, 568 {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 569 gpr_pc}, 570 nullptr, 571 nullptr, 572 nullptr, 573 }, 574 { 575 "cpsr", 576 "psr", 577 4, 578 GPR_OFFSET(16), 579 eEncodingUint, 580 eFormatHex, 581 {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, 582 LLDB_INVALID_REGNUM, gpr_cpsr}, 583 nullptr, 584 nullptr, 585 nullptr, 586 }, 587 588 FPU_REG(s0, 4, 0, q0), 589 FPU_REG(s1, 4, 1, q0), 590 FPU_REG(s2, 4, 2, q0), 591 FPU_REG(s3, 4, 3, q0), 592 FPU_REG(s4, 4, 4, q1), 593 FPU_REG(s5, 4, 5, q1), 594 FPU_REG(s6, 4, 6, q1), 595 FPU_REG(s7, 4, 7, q1), 596 FPU_REG(s8, 4, 8, q2), 597 FPU_REG(s9, 4, 9, q2), 598 FPU_REG(s10, 4, 10, q2), 599 FPU_REG(s11, 4, 11, q2), 600 FPU_REG(s12, 4, 12, q3), 601 FPU_REG(s13, 4, 13, q3), 602 FPU_REG(s14, 4, 14, q3), 603 FPU_REG(s15, 4, 15, q3), 604 FPU_REG(s16, 4, 16, q4), 605 FPU_REG(s17, 4, 17, q4), 606 FPU_REG(s18, 4, 18, q4), 607 FPU_REG(s19, 4, 19, q4), 608 FPU_REG(s20, 4, 20, q5), 609 FPU_REG(s21, 4, 21, q5), 610 FPU_REG(s22, 4, 22, q5), 611 FPU_REG(s23, 4, 23, q5), 612 FPU_REG(s24, 4, 24, q6), 613 FPU_REG(s25, 4, 25, q6), 614 FPU_REG(s26, 4, 26, q6), 615 FPU_REG(s27, 4, 27, q6), 616 FPU_REG(s28, 4, 28, q7), 617 FPU_REG(s29, 4, 29, q7), 618 FPU_REG(s30, 4, 30, q7), 619 FPU_REG(s31, 4, 31, q7), 620 621 { 622 "fpscr", 623 nullptr, 624 4, 625 FPSCR_OFFSET, 626 eEncodingUint, 627 eFormatHex, 628 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 629 LLDB_INVALID_REGNUM, fpu_fpscr}, 630 nullptr, 631 nullptr, 632 nullptr, 633 }, 634 635 FPU_REG(d0, 8, 0, q0), 636 FPU_REG(d1, 8, 2, q0), 637 FPU_REG(d2, 8, 4, q1), 638 FPU_REG(d3, 8, 6, q1), 639 FPU_REG(d4, 8, 8, q2), 640 FPU_REG(d5, 8, 10, q2), 641 FPU_REG(d6, 8, 12, q3), 642 FPU_REG(d7, 8, 14, q3), 643 FPU_REG(d8, 8, 16, q4), 644 FPU_REG(d9, 8, 18, q4), 645 FPU_REG(d10, 8, 20, q5), 646 FPU_REG(d11, 8, 22, q5), 647 FPU_REG(d12, 8, 24, q6), 648 FPU_REG(d13, 8, 26, q6), 649 FPU_REG(d14, 8, 28, q7), 650 FPU_REG(d15, 8, 30, q7), 651 FPU_REG(d16, 8, 32, q8), 652 FPU_REG(d17, 8, 34, q8), 653 FPU_REG(d18, 8, 36, q9), 654 FPU_REG(d19, 8, 38, q9), 655 FPU_REG(d20, 8, 40, q10), 656 FPU_REG(d21, 8, 42, q10), 657 FPU_REG(d22, 8, 44, q11), 658 FPU_REG(d23, 8, 46, q11), 659 FPU_REG(d24, 8, 48, q12), 660 FPU_REG(d25, 8, 50, q12), 661 FPU_REG(d26, 8, 52, q13), 662 FPU_REG(d27, 8, 54, q13), 663 FPU_REG(d28, 8, 56, q14), 664 FPU_REG(d29, 8, 58, q14), 665 FPU_REG(d30, 8, 60, q15), 666 FPU_REG(d31, 8, 62, q15), 667 668 FPU_QREG(q0, 0), 669 FPU_QREG(q1, 4), 670 FPU_QREG(q2, 8), 671 FPU_QREG(q3, 12), 672 FPU_QREG(q4, 16), 673 FPU_QREG(q5, 20), 674 FPU_QREG(q6, 24), 675 FPU_QREG(q7, 28), 676 FPU_QREG(q8, 32), 677 FPU_QREG(q9, 36), 678 FPU_QREG(q10, 40), 679 FPU_QREG(q11, 44), 680 FPU_QREG(q12, 48), 681 FPU_QREG(q13, 52), 682 FPU_QREG(q14, 56), 683 FPU_QREG(q15, 60), 684 685 { 686 "exception", 687 nullptr, 688 4, 689 EXC_OFFSET(0), 690 eEncodingUint, 691 eFormatHex, 692 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 693 LLDB_INVALID_REGNUM, exc_exception}, 694 nullptr, 695 nullptr, 696 nullptr, 697 }, 698 { 699 "fsr", 700 nullptr, 701 4, 702 EXC_OFFSET(1), 703 eEncodingUint, 704 eFormatHex, 705 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 706 LLDB_INVALID_REGNUM, exc_fsr}, 707 nullptr, 708 nullptr, 709 nullptr, 710 }, 711 { 712 "far", 713 nullptr, 714 4, 715 EXC_OFFSET(2), 716 eEncodingUint, 717 eFormatHex, 718 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 719 LLDB_INVALID_REGNUM, exc_far}, 720 nullptr, 721 nullptr, 722 nullptr, 723 }, 724 725 {DEFINE_DBG(bvr, 0)}, 726 {DEFINE_DBG(bvr, 1)}, 727 {DEFINE_DBG(bvr, 2)}, 728 {DEFINE_DBG(bvr, 3)}, 729 {DEFINE_DBG(bvr, 4)}, 730 {DEFINE_DBG(bvr, 5)}, 731 {DEFINE_DBG(bvr, 6)}, 732 {DEFINE_DBG(bvr, 7)}, 733 {DEFINE_DBG(bvr, 8)}, 734 {DEFINE_DBG(bvr, 9)}, 735 {DEFINE_DBG(bvr, 10)}, 736 {DEFINE_DBG(bvr, 11)}, 737 {DEFINE_DBG(bvr, 12)}, 738 {DEFINE_DBG(bvr, 13)}, 739 {DEFINE_DBG(bvr, 14)}, 740 {DEFINE_DBG(bvr, 15)}, 741 742 {DEFINE_DBG(bcr, 0)}, 743 {DEFINE_DBG(bcr, 1)}, 744 {DEFINE_DBG(bcr, 2)}, 745 {DEFINE_DBG(bcr, 3)}, 746 {DEFINE_DBG(bcr, 4)}, 747 {DEFINE_DBG(bcr, 5)}, 748 {DEFINE_DBG(bcr, 6)}, 749 {DEFINE_DBG(bcr, 7)}, 750 {DEFINE_DBG(bcr, 8)}, 751 {DEFINE_DBG(bcr, 9)}, 752 {DEFINE_DBG(bcr, 10)}, 753 {DEFINE_DBG(bcr, 11)}, 754 {DEFINE_DBG(bcr, 12)}, 755 {DEFINE_DBG(bcr, 13)}, 756 {DEFINE_DBG(bcr, 14)}, 757 {DEFINE_DBG(bcr, 15)}, 758 759 {DEFINE_DBG(wvr, 0)}, 760 {DEFINE_DBG(wvr, 1)}, 761 {DEFINE_DBG(wvr, 2)}, 762 {DEFINE_DBG(wvr, 3)}, 763 {DEFINE_DBG(wvr, 4)}, 764 {DEFINE_DBG(wvr, 5)}, 765 {DEFINE_DBG(wvr, 6)}, 766 {DEFINE_DBG(wvr, 7)}, 767 {DEFINE_DBG(wvr, 8)}, 768 {DEFINE_DBG(wvr, 9)}, 769 {DEFINE_DBG(wvr, 10)}, 770 {DEFINE_DBG(wvr, 11)}, 771 {DEFINE_DBG(wvr, 12)}, 772 {DEFINE_DBG(wvr, 13)}, 773 {DEFINE_DBG(wvr, 14)}, 774 {DEFINE_DBG(wvr, 15)}, 775 776 {DEFINE_DBG(wcr, 0)}, 777 {DEFINE_DBG(wcr, 1)}, 778 {DEFINE_DBG(wcr, 2)}, 779 {DEFINE_DBG(wcr, 3)}, 780 {DEFINE_DBG(wcr, 4)}, 781 {DEFINE_DBG(wcr, 5)}, 782 {DEFINE_DBG(wcr, 6)}, 783 {DEFINE_DBG(wcr, 7)}, 784 {DEFINE_DBG(wcr, 8)}, 785 {DEFINE_DBG(wcr, 9)}, 786 {DEFINE_DBG(wcr, 10)}, 787 {DEFINE_DBG(wcr, 11)}, 788 {DEFINE_DBG(wcr, 12)}, 789 {DEFINE_DBG(wcr, 13)}, 790 {DEFINE_DBG(wcr, 14)}, 791 {DEFINE_DBG(wcr, 15)}}; 792 793 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT 794