1 /* $NetBSD: smu11_driver_if_navi10.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SMU11_DRIVER_IF_NAVI10_H__ 26 #define __SMU11_DRIVER_IF_NAVI10_H__ 27 28 // *** IMPORTANT *** 29 // SMU TEAM: Always increment the interface version if 30 // any structure is changed in this file 31 // Be aware of that the version should be updated in 32 // smu_v11_0.h, maybe rename is also needed. 33 // #define SMU11_DRIVER_IF_VERSION 0x33 34 35 #define PPTABLE_NV10_SMU_VERSION 8 36 37 #define NUM_GFXCLK_DPM_LEVELS 16 38 #define NUM_SMNCLK_DPM_LEVELS 2 39 #define NUM_SOCCLK_DPM_LEVELS 8 40 #define NUM_MP0CLK_DPM_LEVELS 2 41 #define NUM_DCLK_DPM_LEVELS 8 42 #define NUM_VCLK_DPM_LEVELS 8 43 #define NUM_DCEFCLK_DPM_LEVELS 8 44 #define NUM_PHYCLK_DPM_LEVELS 8 45 #define NUM_DISPCLK_DPM_LEVELS 8 46 #define NUM_PIXCLK_DPM_LEVELS 8 47 #define NUM_UCLK_DPM_LEVELS 4 48 #define NUM_MP1CLK_DPM_LEVELS 2 49 #define NUM_LINK_LEVELS 2 50 51 52 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 53 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 54 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 55 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 56 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 57 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 58 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 59 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 60 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 61 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 62 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 63 #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 64 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 65 66 //Gemini Modes 67 #define PPSMC_GeminiModeNone 0 //Single GPU board 68 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 69 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 70 71 // Feature Control Defines 72 // DPM 73 #define FEATURE_DPM_PREFETCHER_BIT 0 74 #define FEATURE_DPM_GFXCLK_BIT 1 75 #define FEATURE_DPM_GFX_PACE_BIT 2 76 #define FEATURE_DPM_UCLK_BIT 3 77 #define FEATURE_DPM_SOCCLK_BIT 4 78 #define FEATURE_DPM_MP0CLK_BIT 5 79 #define FEATURE_DPM_LINK_BIT 6 80 #define FEATURE_DPM_DCEFCLK_BIT 7 81 #define FEATURE_MEM_VDDCI_SCALING_BIT 8 82 #define FEATURE_MEM_MVDD_SCALING_BIT 9 83 84 //Idle 85 #define FEATURE_DS_GFXCLK_BIT 10 86 #define FEATURE_DS_SOCCLK_BIT 11 87 #define FEATURE_DS_LCLK_BIT 12 88 #define FEATURE_DS_DCEFCLK_BIT 13 89 #define FEATURE_DS_UCLK_BIT 14 90 #define FEATURE_GFX_ULV_BIT 15 91 #define FEATURE_FW_DSTATE_BIT 16 92 #define FEATURE_GFXOFF_BIT 17 93 #define FEATURE_BACO_BIT 18 94 #define FEATURE_VCN_PG_BIT 19 95 #define FEATURE_JPEG_PG_BIT 20 96 #define FEATURE_USB_PG_BIT 21 97 #define FEATURE_RSMU_SMN_CG_BIT 22 98 //Throttler/Response 99 #define FEATURE_PPT_BIT 23 100 #define FEATURE_TDC_BIT 24 101 #define FEATURE_GFX_EDC_BIT 25 102 #define FEATURE_APCC_PLUS_BIT 26 103 #define FEATURE_GTHR_BIT 27 104 #define FEATURE_ACDC_BIT 28 105 #define FEATURE_VR0HOT_BIT 29 106 #define FEATURE_VR1HOT_BIT 30 107 #define FEATURE_FW_CTF_BIT 31 108 #define FEATURE_FAN_CONTROL_BIT 32 109 #define FEATURE_THERMAL_BIT 33 110 #define FEATURE_GFX_DCS_BIT 34 111 //VF 112 #define FEATURE_RM_BIT 35 113 #define FEATURE_LED_DISPLAY_BIT 36 114 //Other 115 #define FEATURE_GFX_SS_BIT 37 116 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 117 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 118 119 #define FEATURE_MMHUB_PG_BIT 40 120 #define FEATURE_ATHUB_PG_BIT 41 121 #define FEATURE_APCC_DFLL_BIT 42 122 #define FEATURE_SPARE_43_BIT 43 123 #define FEATURE_SPARE_44_BIT 44 124 #define FEATURE_SPARE_45_BIT 45 125 #define FEATURE_SPARE_46_BIT 46 126 #define FEATURE_SPARE_47_BIT 47 127 #define FEATURE_SPARE_48_BIT 48 128 #define FEATURE_SPARE_49_BIT 49 129 #define FEATURE_SPARE_50_BIT 50 130 #define FEATURE_SPARE_51_BIT 51 131 #define FEATURE_SPARE_52_BIT 52 132 #define FEATURE_SPARE_53_BIT 53 133 #define FEATURE_SPARE_54_BIT 54 134 #define FEATURE_SPARE_55_BIT 55 135 #define FEATURE_SPARE_56_BIT 56 136 #define FEATURE_SPARE_57_BIT 57 137 #define FEATURE_SPARE_58_BIT 58 138 #define FEATURE_SPARE_59_BIT 59 139 #define FEATURE_SPARE_60_BIT 60 140 #define FEATURE_SPARE_61_BIT 61 141 #define FEATURE_SPARE_62_BIT 62 142 #define FEATURE_SPARE_63_BIT 63 143 #define NUM_FEATURES 64 144 145 // Debug Overrides Bitmask 146 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 147 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 148 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_SOCCLK 0x00000004 149 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000008 150 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000010 151 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 152 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 153 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_SOCCLK 0x00000080 154 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 155 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 156 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 157 158 // VR Mapping Bit Defines 159 #define VR_MAPPING_VR_SELECT_MASK 0x01 160 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 161 162 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 163 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 164 165 // PSI Bit Defines 166 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 167 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 168 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 169 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 170 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 171 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 172 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 173 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 174 175 // Throttler Control/Status Bits 176 #define THROTTLER_PADDING_BIT 0 177 #define THROTTLER_TEMP_EDGE_BIT 1 178 #define THROTTLER_TEMP_HOTSPOT_BIT 2 179 #define THROTTLER_TEMP_MEM_BIT 3 180 #define THROTTLER_TEMP_VR_GFX_BIT 4 181 #define THROTTLER_TEMP_VR_MEM0_BIT 5 182 #define THROTTLER_TEMP_VR_MEM1_BIT 6 183 #define THROTTLER_TEMP_VR_SOC_BIT 7 184 #define THROTTLER_TEMP_LIQUID0_BIT 8 185 #define THROTTLER_TEMP_LIQUID1_BIT 9 186 #define THROTTLER_TEMP_PLX_BIT 10 187 #define THROTTLER_TEMP_SKIN_BIT 11 188 #define THROTTLER_TDC_GFX_BIT 12 189 #define THROTTLER_TDC_SOC_BIT 13 190 #define THROTTLER_PPT0_BIT 14 191 #define THROTTLER_PPT1_BIT 15 192 #define THROTTLER_PPT2_BIT 16 193 #define THROTTLER_PPT3_BIT 17 194 #define THROTTLER_FIT_BIT 18 195 #define THROTTLER_PPM_BIT 19 196 #define THROTTLER_APCC_BIT 20 197 198 // FW DState Features Control Bits 199 #define FW_DSTATE_SOC_ULV_BIT 0 200 #define FW_DSTATE_G6_HSR_BIT 1 201 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 202 #define FW_DSTATE_MP0_DS_BIT 3 203 #define FW_DSTATE_SMN_DS_BIT 4 204 #define FW_DSTATE_MP1_DS_BIT 5 205 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 206 #define FW_DSTATE_LIV_MIN_BIT 7 207 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 208 209 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 210 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 211 #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 212 #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 213 #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 214 #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 215 #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 216 #define FW_DSTATE_LIV_MIN_MASK (1 << FW_DSTATE_LIV_MIN_BIT ) 217 #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 218 219 //I2C Interface 220 221 #define NUM_I2C_CONTROLLERS 8 222 223 #define I2C_CONTROLLER_ENABLED 1 224 #define I2C_CONTROLLER_DISABLED 0 225 226 #define MAX_SW_I2C_COMMANDS 8 227 228 typedef enum { 229 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 230 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 231 I2C_CONTROLLER_PORT_COUNT, 232 } I2cControllerPort_e; 233 234 typedef enum { 235 I2C_CONTROLLER_NAME_VR_GFX = 0, 236 I2C_CONTROLLER_NAME_VR_SOC, 237 I2C_CONTROLLER_NAME_VR_VDDCI, 238 I2C_CONTROLLER_NAME_VR_MVDD, 239 I2C_CONTROLLER_NAME_LIQUID0, 240 I2C_CONTROLLER_NAME_LIQUID1, 241 I2C_CONTROLLER_NAME_PLX, 242 I2C_CONTROLLER_NAME_SPARE, 243 I2C_CONTROLLER_NAME_COUNT, 244 } I2cControllerName_e; 245 246 typedef enum { 247 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 248 I2C_CONTROLLER_THROTTLER_VR_GFX, 249 I2C_CONTROLLER_THROTTLER_VR_SOC, 250 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 251 I2C_CONTROLLER_THROTTLER_VR_MVDD, 252 I2C_CONTROLLER_THROTTLER_LIQUID0, 253 I2C_CONTROLLER_THROTTLER_LIQUID1, 254 I2C_CONTROLLER_THROTTLER_PLX, 255 I2C_CONTROLLER_THROTTLER_COUNT, 256 } I2cControllerThrottler_e; 257 258 typedef enum { 259 I2C_CONTROLLER_PROTOCOL_VR_0, 260 I2C_CONTROLLER_PROTOCOL_VR_1, 261 I2C_CONTROLLER_PROTOCOL_TMP_0, 262 I2C_CONTROLLER_PROTOCOL_TMP_1, 263 I2C_CONTROLLER_PROTOCOL_SPARE_0, 264 I2C_CONTROLLER_PROTOCOL_SPARE_1, 265 I2C_CONTROLLER_PROTOCOL_COUNT, 266 } I2cControllerProtocol_e; 267 268 typedef struct { 269 uint8_t Enabled; 270 uint8_t Speed; 271 uint8_t Padding[2]; 272 uint32_t SlaveAddress; 273 uint8_t ControllerPort; 274 uint8_t ControllerName; 275 uint8_t ThermalThrotter; 276 uint8_t I2cProtocol; 277 } I2cControllerConfig_t; 278 279 typedef enum { 280 I2C_PORT_SVD_SCL = 0, 281 I2C_PORT_GPIO, 282 } I2cPort_e; 283 284 typedef enum { 285 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 286 I2C_SPEED_FAST_100K, //100 Kbits/s 287 I2C_SPEED_FAST_400K, //400 Kbits/s 288 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 289 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 290 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 291 I2C_SPEED_COUNT, 292 } I2cSpeed_e; 293 294 typedef enum { 295 I2C_CMD_READ = 0, 296 I2C_CMD_WRITE, 297 I2C_CMD_COUNT, 298 } I2cCmdType_e; 299 300 #define CMDCONFIG_STOP_BIT 0 301 #define CMDCONFIG_RESTART_BIT 1 302 303 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 304 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 305 306 typedef struct { 307 uint8_t RegisterAddr; ////only valid for write, ignored for read 308 uint8_t Cmd; //Read(0) or Write(1) 309 uint8_t Data; //Return data for read. Data to send for write 310 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 311 } SwI2cCmd_t; //SW I2C Command Table 312 313 typedef struct { 314 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 315 uint8_t I2CSpeed; //Slow(0) or Fast(1) 316 uint16_t SlaveAddress; 317 uint8_t NumCmds; //Number of commands 318 uint8_t Padding[3]; 319 320 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 321 322 uint32_t MmHubPadding[8]; // SMU internal use 323 324 } SwI2cRequest_t; // SW I2C Request Table 325 326 //D3HOT sequences 327 typedef enum { 328 BACO_SEQUENCE, 329 MSR_SEQUENCE, 330 BAMACO_SEQUENCE, 331 ULPS_SEQUENCE, 332 D3HOT_SEQUENCE_COUNT, 333 }D3HOTSequence_e; 334 335 //THis is aligned with RSMU PGFSM Register Mapping 336 typedef enum { 337 PG_DYNAMIC_MODE = 0, 338 PG_STATIC_MODE, 339 } PowerGatingMode_e; 340 341 //This is aligned with RSMU PGFSM Register Mapping 342 typedef enum { 343 PG_POWER_DOWN = 0, 344 PG_POWER_UP, 345 } PowerGatingSettings_e; 346 347 typedef struct { 348 uint32_t a; // store in IEEE float format in this variable 349 uint32_t b; // store in IEEE float format in this variable 350 uint32_t c; // store in IEEE float format in this variable 351 } QuadraticInt_t; 352 353 typedef struct { 354 uint32_t m; // store in IEEE float format in this variable 355 uint32_t b; // store in IEEE float format in this variable 356 } LinearInt_t; 357 358 typedef struct { 359 uint32_t a; // store in IEEE float format in this variable 360 uint32_t b; // store in IEEE float format in this variable 361 uint32_t c; // store in IEEE float format in this variable 362 } DroopInt_t; 363 364 typedef enum { 365 GFXCLK_SOURCE_PLL = 0, 366 GFXCLK_SOURCE_DFLL, 367 GFXCLK_SOURCE_COUNT, 368 } GfxclkSrc_e; 369 370 //Only Clks that have DPM descriptors are listed here 371 typedef enum { 372 PPCLK_GFXCLK = 0, 373 PPCLK_SOCCLK, 374 PPCLK_UCLK, 375 PPCLK_DCLK, 376 PPCLK_VCLK, 377 PPCLK_DCEFCLK, 378 PPCLK_DISPCLK, 379 PPCLK_PIXCLK, 380 PPCLK_PHYCLK, 381 PPCLK_COUNT, 382 } PPCLK_e; 383 384 typedef enum { 385 POWER_SOURCE_AC, 386 POWER_SOURCE_DC, 387 POWER_SOURCE_COUNT, 388 } POWER_SOURCE_e; 389 390 typedef enum { 391 PPT_THROTTLER_PPT0, 392 PPT_THROTTLER_PPT1, 393 PPT_THROTTLER_PPT2, 394 PPT_THROTTLER_PPT3, 395 PPT_THROTTLER_COUNT 396 } PPT_THROTTLER_e; 397 398 typedef enum { 399 VOLTAGE_MODE_AVFS = 0, 400 VOLTAGE_MODE_AVFS_SS, 401 VOLTAGE_MODE_SS, 402 VOLTAGE_MODE_COUNT, 403 } VOLTAGE_MODE_e; 404 405 406 typedef enum { 407 AVFS_VOLTAGE_GFX = 0, 408 AVFS_VOLTAGE_SOC, 409 AVFS_VOLTAGE_COUNT, 410 } AVFS_VOLTAGE_TYPE_e; 411 412 typedef enum { 413 UCLK_DIV_BY_1 = 0, 414 UCLK_DIV_BY_2, 415 UCLK_DIV_BY_4, 416 UCLK_DIV_BY_8, 417 } UCLK_DIV_e; 418 419 typedef enum { 420 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 421 GPIO_INT_POLARITY_ACTIVE_HIGH, 422 } GpioIntPolarity_e; 423 424 typedef enum { 425 MEMORY_TYPE_GDDR6 = 0, 426 MEMORY_TYPE_HBM, 427 } MemoryType_e; 428 429 typedef enum { 430 PWR_CONFIG_TDP = 0, 431 PWR_CONFIG_TGP, 432 PWR_CONFIG_TCP_ESTIMATED, 433 PWR_CONFIG_TCP_MEASURED, 434 } PwrConfig_e; 435 436 typedef struct { 437 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 438 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 439 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 440 uint8_t Padding; 441 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 442 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 443 } DpmDescriptor_t; 444 445 typedef enum { 446 TEMP_EDGE, 447 TEMP_HOTSPOT, 448 TEMP_MEM, 449 TEMP_VR_GFX, 450 TEMP_VR_MEM0, 451 TEMP_VR_MEM1, 452 TEMP_VR_SOC, 453 TEMP_LIQUID0, 454 TEMP_LIQUID1, 455 TEMP_PLX, 456 TEMP_COUNT 457 } TEMP_e; 458 459 //Out of band monitor status defines 460 //see SPEC //gpu/doc/soc_arch/spec/feature/SMBUS/SMBUS.xlsx 461 #define POWER_MANAGER_CONTROLLER_NOT_RUNNING 0 462 #define POWER_MANAGER_CONTROLLER_RUNNING 1 463 464 #define POWER_MANAGER_CONTROLLER_BIT 0 465 #define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT 8 466 #define GPU_DIE_TEMPERATURE_THROTTLING_BIT 9 467 #define HBM_DIE_TEMPERATURE_THROTTLING_BIT 10 468 #define TGP_THROTTLING_BIT 11 469 #define PCC_THROTTLING_BIT 12 470 #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT 13 471 #define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT 14 472 473 #define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT ) 474 #define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_MASK (1 << MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT ) 475 #define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT ) 476 #define HBM_DIE_TEMPERATURE_THROTTLING_MASK (1 << HBM_DIE_TEMPERATURE_THROTTLING_BIT ) 477 #define TGP_THROTTLING_MASK (1 << TGP_THROTTLING_BIT ) 478 #define PCC_THROTTLING_MASK (1 << PCC_THROTTLING_BIT ) 479 #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK (1 << HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT ) 480 #define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT) 481 482 //This structure to be DMA to SMBUS Config register space 483 typedef struct { 484 uint8_t MinorInfoVersion; 485 uint8_t MajorInfoVersion; 486 uint8_t TableSize; 487 uint8_t Reserved; 488 489 uint8_t Reserved1; 490 uint8_t RevID; 491 uint16_t DeviceID; 492 493 uint16_t DieTemperatureLimit; 494 uint16_t FanTargetTemperature; 495 496 uint16_t MemoryTemperatureLimit; 497 uint16_t MemoryTemperatureLimit1; 498 499 uint16_t TGP; 500 uint16_t CardPower; 501 502 uint32_t DieTemperatureRegisterOffset; 503 504 uint32_t Reserved2; 505 506 uint32_t Reserved3; 507 508 uint32_t Status; 509 510 uint16_t DieTemperature; 511 uint16_t CurrentMemoryTemperature; 512 513 uint16_t MemoryTemperature; 514 uint8_t MemoryHotspotPosition; 515 uint8_t Reserved4; 516 517 uint32_t BoardLevelEnergyAccumulator; 518 } OutOfBandMonitor_t; 519 520 typedef struct { 521 uint32_t Version; 522 523 // SECTION: Feature Enablement 524 uint32_t FeaturesToRun[2]; 525 526 // SECTION: Infrastructure Limits 527 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 528 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 529 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; 530 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; 531 532 uint16_t TdcLimitSoc; // Amps 533 uint16_t TdcLimitSocTau; // Time constant of LPF in ms 534 uint16_t TdcLimitGfx; // Amps 535 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 536 537 uint16_t TedgeLimit; // Celcius 538 uint16_t ThotspotLimit; // Celcius 539 uint16_t TmemLimit; // Celcius 540 uint16_t Tvr_gfxLimit; // Celcius 541 uint16_t Tvr_mem0Limit; // Celcius 542 uint16_t Tvr_mem1Limit; // Celcius 543 uint16_t Tvr_socLimit; // Celcius 544 uint16_t Tliquid0Limit; // Celcius 545 uint16_t Tliquid1Limit; // Celcius 546 uint16_t TplxLimit; // Celcius 547 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 548 549 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 550 uint16_t PpmTemperatureThreshold; 551 552 // SECTION: Throttler settings 553 uint32_t ThrottlerControlMask; // See Throtter masks defines 554 555 // SECTION: FW DSTATE Settings 556 uint32_t FwDStateMask; // See FW DState masks defines 557 558 // SECTION: ULV Settings 559 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 560 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 561 562 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events 563 uint8_t paddingRlcUlvParams[3]; 564 565 uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 566 uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 567 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 568 uint8_t Padding234; 569 570 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 571 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 572 573 574 // SECTION: Voltage Control Parameters 575 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 576 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 577 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 578 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 579 580 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 581 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 582 583 //SECTION: DPM Config 1 584 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 585 586 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 587 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 588 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 589 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 590 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 591 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 592 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 593 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 594 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 595 uint32_t Paddingclks[16]; 596 597 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 598 uint16_t Padding8_Clks; 599 600 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 601 602 // SECTION: DPM Config 2 603 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 604 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 605 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 606 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 607 // GFXCLK DPM 608 uint16_t GfxclkFgfxoffEntry; // in Mhz 609 uint16_t GfxclkFinit; // in Mhz 610 uint16_t GfxclkFidle; // in MHz 611 uint16_t GfxclkSlewRate; // for PLL babystepping??? 612 uint16_t GfxclkFopt; // in Mhz 613 uint8_t Padding567[2]; 614 uint16_t GfxclkDsMaxFreq; // in MHz 615 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 616 uint8_t Padding456; 617 618 // UCLK section 619 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 620 uint8_t paddingUclk[3]; 621 622 uint8_t MemoryType; // 0-GDDR6, 1-HBM 623 uint8_t MemoryChannels; 624 uint8_t PaddingMem[2]; 625 626 // Link DPM Settings 627 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 628 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 629 uint16_t LclkFreq[NUM_LINK_LEVELS]; 630 631 // GFXCLK Thermal DPM (formerly 'Boost' Settings) 632 uint16_t EnableTdpm; 633 uint16_t TdpmHighHystTemperature; 634 uint16_t TdpmLowHystTemperature; 635 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 636 637 // SECTION: Fan Control 638 uint16_t FanStopTemp; //Celcius 639 uint16_t FanStartTemp; //Celcius 640 641 uint16_t FanGainEdge; 642 uint16_t FanGainHotspot; 643 uint16_t FanGainLiquid0; 644 uint16_t FanGainLiquid1; 645 uint16_t FanGainVrGfx; 646 uint16_t FanGainVrSoc; 647 uint16_t FanGainVrMem0; 648 uint16_t FanGainVrMem1; 649 uint16_t FanGainPlx; 650 uint16_t FanGainMem; 651 uint16_t FanPwmMin; 652 uint16_t FanAcousticLimitRpm; 653 uint16_t FanThrottlingRpm; 654 uint16_t FanMaximumRpm; 655 uint16_t FanTargetTemperature; 656 uint16_t FanTargetGfxclk; 657 uint8_t FanTempInputSelect; 658 uint8_t FanPadding; 659 uint8_t FanZeroRpmEnable; 660 uint8_t FanTachEdgePerRev; 661 //uint8_t padding8_Fan[2]; 662 663 // The following are AFC override parameters. Leave at 0 to use FW defaults. 664 int16_t FuzzyFan_ErrorSetDelta; 665 int16_t FuzzyFan_ErrorRateSetDelta; 666 int16_t FuzzyFan_PwmSetDelta; 667 uint16_t FuzzyFan_Reserved; 668 669 670 // SECTION: AVFS 671 // Overrides 672 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 673 uint8_t Padding8_Avfs[2]; 674 675 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 676 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 677 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 678 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 679 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 680 681 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 682 683 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 684 685 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 686 uint8_t Padding8_GfxBtc[2]; 687 688 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 689 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 690 691 // SECTION: Advanced Options 692 uint32_t DebugOverrides; 693 QuadraticInt_t ReservedEquation0; 694 QuadraticInt_t ReservedEquation1; 695 QuadraticInt_t ReservedEquation2; 696 QuadraticInt_t ReservedEquation3; 697 698 // Total Power configuration, use defines from PwrConfig_e 699 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 700 uint8_t TotalPowerSpare1; 701 uint16_t TotalPowerSpare2; 702 703 // APCC Settings 704 uint16_t PccThresholdLow; 705 uint16_t PccThresholdHigh; 706 uint32_t PaddingAPCC[6]; //FIXME pending SPEC 707 708 // Temperature Dependent Vmin 709 uint16_t VDDGFX_TVmin; //Celcius 710 uint16_t VDDSOC_TVmin; //Celcius 711 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 712 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 713 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 714 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 715 716 uint16_t VDDGFX_TVminHystersis; // Celcius 717 uint16_t VDDSOC_TVminHystersis; // Celcius 718 719 // BTC Setting 720 uint32_t BtcConfig; 721 722 uint16_t SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2 723 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 724 725 // SECTION: Board Reserved 726 uint32_t Reserved[8]; 727 728 // SECTION: BOARD PARAMETERS 729 // I2C Control 730 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 731 732 // SVI2 Board Parameters 733 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 734 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 735 736 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 737 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 738 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 739 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 740 741 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 742 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 743 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 744 uint8_t Padding8_V; 745 746 // Telemetry Settings 747 uint16_t GfxMaxCurrent; // in Amps 748 int8_t GfxOffset; // in Amps 749 uint8_t Padding_TelemetryGfx; 750 751 uint16_t SocMaxCurrent; // in Amps 752 int8_t SocOffset; // in Amps 753 uint8_t Padding_TelemetrySoc; 754 755 uint16_t Mem0MaxCurrent; // in Amps 756 int8_t Mem0Offset; // in Amps 757 uint8_t Padding_TelemetryMem0; 758 759 uint16_t Mem1MaxCurrent; // in Amps 760 int8_t Mem1Offset; // in Amps 761 uint8_t Padding_TelemetryMem1; 762 763 // GPIO Settings 764 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 765 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 766 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 767 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 768 769 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 770 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 771 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 772 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 773 774 // LED Display Settings 775 uint8_t LedPin0; // GPIO number for LedPin[0] 776 uint8_t LedPin1; // GPIO number for LedPin[1] 777 uint8_t LedPin2; // GPIO number for LedPin[2] 778 uint8_t padding8_4; 779 780 // GFXCLK PLL Spread Spectrum 781 uint8_t PllGfxclkSpreadEnabled; // on or off 782 uint8_t PllGfxclkSpreadPercent; // Q4.4 783 uint16_t PllGfxclkSpreadFreq; // kHz 784 785 // GFXCLK DFLL Spread Spectrum 786 uint8_t DfllGfxclkSpreadEnabled; // on or off 787 uint8_t DfllGfxclkSpreadPercent; // Q4.4 788 uint16_t DfllGfxclkSpreadFreq; // kHz 789 790 // UCLK Spread Spectrum 791 uint8_t UclkSpreadEnabled; // on or off 792 uint8_t UclkSpreadPercent; // Q4.4 793 uint16_t UclkSpreadFreq; // kHz 794 795 // SOCCLK Spread Spectrum 796 uint8_t SoclkSpreadEnabled; // on or off 797 uint8_t SocclkSpreadPercent; // Q4.4 798 uint16_t SocclkSpreadFreq; // kHz 799 800 // Total board power 801 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 802 uint16_t BoardPadding; 803 804 // Mvdd Svi2 Div Ratio Setting 805 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 806 807 uint8_t RenesesLoadLineEnabled; 808 uint8_t GfxLoadlineResistance; 809 uint8_t SocLoadlineResistance; 810 uint8_t Padding8_Loadline; 811 812 uint32_t BoardReserved[8]; 813 814 // Padding for MMHUB - do not modify this 815 uint32_t MmHubPadding[8]; // SMU internal use 816 817 } PPTable_t; 818 819 typedef struct { 820 // Time constant parameters for clock averages in ms 821 uint16_t GfxclkAverageLpfTau; 822 uint16_t SocclkAverageLpfTau; 823 uint16_t UclkAverageLpfTau; 824 uint16_t GfxActivityLpfTau; 825 uint16_t UclkActivityLpfTau; 826 uint16_t SocketPowerLpfTau; 827 828 // Padding - ignore 829 uint32_t MmHubPadding[8]; // SMU internal use 830 } DriverSmuConfig_t; 831 832 typedef struct { 833 834 uint16_t GfxclkFmin; // MHz 835 uint16_t GfxclkFmax; // MHz 836 uint16_t GfxclkFreq1; // MHz 837 uint16_t GfxclkVolt1; // mV (Q2) 838 uint16_t GfxclkFreq2; // MHz 839 uint16_t GfxclkVolt2; // mV (Q2) 840 uint16_t GfxclkFreq3; // MHz 841 uint16_t GfxclkVolt3; // mV (Q2) 842 uint16_t UclkFmax; // MHz 843 int16_t OverDrivePct; // % 844 uint16_t FanMaximumRpm; 845 uint16_t FanMinimumPwm; 846 uint16_t FanTargetTemperature; // Degree Celcius 847 uint16_t MaxOpTemp; // Degree Celcius 848 uint16_t FanZeroRpmEnable; 849 uint16_t Padding; 850 851 uint32_t MmHubPadding[8]; // SMU internal use 852 853 } OverDriveTable_t; 854 855 typedef struct { 856 uint16_t CurrClock[PPCLK_COUNT]; 857 uint16_t AverageGfxclkFrequency; 858 uint16_t AverageSocclkFrequency; 859 uint16_t AverageUclkFrequency ; 860 uint16_t AverageGfxActivity ; 861 uint16_t AverageUclkActivity ; 862 uint8_t CurrSocVoltageOffset ; 863 uint8_t CurrGfxVoltageOffset ; 864 uint8_t CurrMemVidOffset ; 865 uint8_t Padding8 ; 866 uint16_t AverageSocketPower ; 867 uint16_t TemperatureEdge ; 868 uint16_t TemperatureHotspot ; 869 uint16_t TemperatureMem ; 870 uint16_t TemperatureVrGfx ; 871 uint16_t TemperatureVrMem0 ; 872 uint16_t TemperatureVrMem1 ; 873 uint16_t TemperatureVrSoc ; 874 uint16_t TemperatureLiquid0 ; 875 uint16_t TemperatureLiquid1 ; 876 uint16_t TemperaturePlx ; 877 uint16_t Padding16 ; 878 uint32_t ThrottlerStatus ; 879 880 uint8_t LinkDpmLevel; 881 uint8_t Padding8_2; 882 uint16_t CurrFanSpeed; 883 884 // Padding - ignore 885 uint32_t MmHubPadding[8]; // SMU internal use 886 } SmuMetrics_t; 887 888 typedef struct { 889 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 890 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 891 uint16_t MinUclk; 892 uint16_t MaxUclk; 893 894 uint8_t WmSetting; 895 uint8_t Padding[3]; 896 897 uint32_t MmHubPadding[8]; // SMU internal use 898 } WatermarkRowGeneric_t; 899 900 #define NUM_WM_RANGES 4 901 902 typedef enum { 903 WM_SOCCLK = 0, 904 WM_DCEFCLK, 905 WM_COUNT, 906 } WM_CLOCK_e; 907 908 typedef struct { 909 // Watermarks 910 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 911 912 uint32_t MmHubPadding[8]; // SMU internal use 913 } Watermarks_t; 914 915 typedef struct { 916 uint16_t avgPsmCount[28]; 917 uint16_t minPsmCount[28]; 918 float avgPsmVoltage[28]; 919 float minPsmVoltage[28]; 920 921 uint32_t MmHubPadding[32]; // SMU internal use 922 } AvfsDebugTable_t_NV14; 923 924 typedef struct { 925 uint16_t avgPsmCount[36]; 926 uint16_t minPsmCount[36]; 927 float avgPsmVoltage[36]; 928 float minPsmVoltage[36]; 929 930 uint32_t MmHubPadding[8]; // SMU internal use 931 } AvfsDebugTable_t_NV10; 932 933 typedef struct { 934 uint8_t AvfsVersion; 935 uint8_t Padding; 936 937 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 938 939 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 940 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 941 942 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 943 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 944 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 945 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 946 947 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 948 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 949 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 950 951 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 952 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 953 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 954 955 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 956 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 957 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 958 959 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 960 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 961 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 962 963 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 964 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 965 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 966 967 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 968 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 969 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 970 971 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 972 973 974 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 975 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 976 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 977 978 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 979 980 uint32_t EnabledAvfsModules[2]; //NV10 - 36 AVFS modules 981 982 uint32_t MmHubPadding[8]; // SMU internal use 983 } AvfsFuseOverride_t; 984 985 typedef struct { 986 987 uint8_t Gfx_ActiveHystLimit; 988 uint8_t Gfx_IdleHystLimit; 989 uint8_t Gfx_FPS; 990 uint8_t Gfx_MinActiveFreqType; 991 uint8_t Gfx_BoosterFreqType; 992 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 993 uint16_t Gfx_MinActiveFreq; // MHz 994 uint16_t Gfx_BoosterFreq; // MHz 995 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 996 uint32_t Gfx_PD_Data_limit_a; // Q16 997 uint32_t Gfx_PD_Data_limit_b; // Q16 998 uint32_t Gfx_PD_Data_limit_c; // Q16 999 uint32_t Gfx_PD_Data_error_coeff; // Q16 1000 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1001 1002 uint8_t Soc_ActiveHystLimit; 1003 uint8_t Soc_IdleHystLimit; 1004 uint8_t Soc_FPS; 1005 uint8_t Soc_MinActiveFreqType; 1006 uint8_t Soc_BoosterFreqType; 1007 uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1008 uint16_t Soc_MinActiveFreq; // MHz 1009 uint16_t Soc_BoosterFreq; // MHz 1010 uint16_t Soc_PD_Data_time_constant; // Time constant of PD controller in ms 1011 uint32_t Soc_PD_Data_limit_a; // Q16 1012 uint32_t Soc_PD_Data_limit_b; // Q16 1013 uint32_t Soc_PD_Data_limit_c; // Q16 1014 uint32_t Soc_PD_Data_error_coeff; // Q16 1015 uint32_t Soc_PD_Data_error_rate_coeff; // Q16 1016 1017 uint8_t Mem_ActiveHystLimit; 1018 uint8_t Mem_IdleHystLimit; 1019 uint8_t Mem_FPS; 1020 uint8_t Mem_MinActiveFreqType; 1021 uint8_t Mem_BoosterFreqType; 1022 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1023 uint16_t Mem_MinActiveFreq; // MHz 1024 uint16_t Mem_BoosterFreq; // MHz 1025 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1026 uint32_t Mem_PD_Data_limit_a; // Q16 1027 uint32_t Mem_PD_Data_limit_b; // Q16 1028 uint32_t Mem_PD_Data_limit_c; // Q16 1029 uint32_t Mem_PD_Data_error_coeff; // Q16 1030 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1031 1032 uint32_t Mem_UpThreshold_Limit; // Q16 1033 uint8_t Mem_UpHystLimit; 1034 uint8_t Mem_DownHystLimit; 1035 uint16_t Mem_Fps; 1036 1037 uint32_t MmHubPadding[8]; // SMU internal use 1038 1039 } DpmActivityMonitorCoeffInt_t; 1040 1041 1042 // Workload bits 1043 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1044 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1045 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1046 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1047 #define WORKLOAD_PPLIB_VR_BIT 4 1048 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1049 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1050 #define WORKLOAD_PPLIB_COUNT 7 1051 1052 1053 // These defines are used with the following messages: 1054 // SMC_MSG_TransferTableDram2Smu 1055 // SMC_MSG_TransferTableSmu2Dram 1056 1057 // Table transfer status 1058 #define TABLE_TRANSFER_OK 0x0 1059 #define TABLE_TRANSFER_FAILED 0xFF 1060 1061 // Table types 1062 #define TABLE_PPTABLE 0 1063 #define TABLE_WATERMARKS 1 1064 #define TABLE_AVFS 2 1065 #define TABLE_AVFS_PSM_DEBUG 3 1066 #define TABLE_AVFS_FUSE_OVERRIDE 4 1067 #define TABLE_PMSTATUSLOG 5 1068 #define TABLE_SMU_METRICS 6 1069 #define TABLE_DRIVER_SMU_CONFIG 7 1070 #define TABLE_ACTIVITY_MONITOR_COEFF 8 1071 #define TABLE_OVERDRIVE 9 1072 #define TABLE_I2C_COMMANDS 10 1073 #define TABLE_PACE 11 1074 #define TABLE_COUNT 12 1075 1076 //RLC Pace Table total number of levels 1077 #define RLC_PACE_TABLE_NUM_LEVELS 16 1078 1079 typedef struct { 1080 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1081 1082 uint32_t MmHubPadding[8]; // SMU internal use 1083 } RlcPaceFlopsPerByteOverride_t; 1084 1085 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1086 #define UCLK_SWITCH_SLOW 0 1087 #define UCLK_SWITCH_FAST 1 1088 #endif 1089