1 /* Definitions of target machine for GNU compiler. LoongArch version. 2 Copyright (C) 2021-2022 Free Software Foundation, Inc. 3 Contributed by Loongson Ltd. 4 Based on MIPS and RISC-V target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* LoongArch external variables defined in loongarch.cc. */ 23 24 #include "config/loongarch/loongarch-opts.h" 25 26 /* Macros to silence warnings about numbers being signed in traditional 27 C and unsigned in ISO C when compiled on 32-bit hosts. */ 28 29 #define BITMASK_HIGH (((unsigned long) 1) << 31) /* 0x80000000 */ 30 31 /* Run-time compilation parameters selecting different hardware subsets. */ 32 33 /* Target CPU builtins. */ 34 #define TARGET_CPU_CPP_BUILTINS() loongarch_cpu_cpp_builtins (pfile) 35 36 /* Default target_flags if no switches are specified. */ 37 38 #ifdef IN_LIBGCC2 39 #undef TARGET_64BIT 40 /* Make this compile time constant for libgcc2. */ 41 #ifdef __loongarch64 42 #define TARGET_64BIT 1 43 #else 44 #define TARGET_64BIT 0 45 #endif 46 #endif /* IN_LIBGCC2 */ 47 48 #define TARGET_LIBGCC_SDATA_SECTION ".sdata" 49 50 /* Driver native functions for SPEC processing in the GCC driver. */ 51 #include "loongarch-driver.h" 52 53 /* This definition replaces the formerly used 'm' constraint with a 54 different constraint letter in order to avoid changing semantics of 55 the 'm' constraint when accepting new address formats in 56 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 57 must not be used in insn definitions or inline assemblies. */ 58 #define TARGET_MEM_CONSTRAINT 'w' 59 60 /* Tell collect what flags to pass to nm. */ 61 #ifndef NM_FLAGS 62 #define NM_FLAGS "-Bn" 63 #endif 64 65 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 66 overridden by subtargets. */ 67 68 #ifndef SUBTARGET_ASM_SPEC 69 #define SUBTARGET_ASM_SPEC "" 70 #endif 71 72 #if HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION 73 #define ASM_MRELAX_DEFAULT "%{!mrelax:%{!mno-relax:-mrelax}}" 74 #else 75 #define ASM_MRELAX_DEFAULT "%{!mrelax:%{!mno-relax:-mno-relax}}" 76 #endif 77 78 #if HAVE_AS_MRELAX_OPTION 79 #define ASM_MRELAX_SPEC \ 80 "%{!mno-pass-mrelax-to-as:%{mrelax} %{mno-relax} " ASM_MRELAX_DEFAULT "}" 81 #else 82 #define ASM_MRELAX_SPEC \ 83 "%{mpass-mrelax-to-as:%{mrelax} %{mno-relax} " ASM_MRELAX_DEFAULT "}" 84 #endif 85 86 #undef ASM_SPEC 87 #define ASM_SPEC \ 88 "%{mabi=*} " ASM_MRELAX_SPEC " %(subtarget_asm_spec)" 89 90 /* Extra switches sometimes passed to the linker. */ 91 92 #ifndef LINK_SPEC 93 #define LINK_SPEC "" 94 #endif /* LINK_SPEC defined */ 95 96 /* Specs for the compiler proper. */ 97 98 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 99 100 #undef CC1_SPEC 101 #define CC1_SPEC "\ 102 %{G*} \ 103 %(subtarget_cc1_spec)" 104 105 /* Preprocessor specs. */ 106 107 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 108 overridden by subtargets. */ 109 #ifndef SUBTARGET_CPP_SPEC 110 #define SUBTARGET_CPP_SPEC "" 111 #endif 112 113 #define CPP_SPEC "%(subtarget_cpp_spec)" 114 115 /* This macro defines names of additional specifications to put in the specs 116 that can be used in various specifications like CC1_SPEC. Its definition 117 is an initializer with a subgrouping for each command option. 118 119 Each subgrouping contains a string constant, that defines the 120 specification name, and a string constant that used by the GCC driver 121 program. 122 123 Do not define this macro if it does not need to do anything. */ 124 125 #define EXTRA_SPECS \ 126 {"subtarget_cc1_spec", SUBTARGET_CC1_SPEC}, \ 127 {"subtarget_cpp_spec", SUBTARGET_CPP_SPEC}, \ 128 {"subtarget_asm_spec", SUBTARGET_ASM_SPEC}, 129 130 /* Registers may have a prefix which can be ignored when matching 131 user asm and register definitions. */ 132 #ifndef REGISTER_PREFIX 133 #define REGISTER_PREFIX "$" 134 #endif 135 136 /* Local compiler-generated symbols must have a prefix that the assembler 137 understands. */ 138 139 #define LOCAL_LABEL_PREFIX "." 140 141 /* By default on the loongarch, external symbols do not have an underscore 142 prepended. */ 143 144 #define USER_LABEL_PREFIX "" 145 146 #ifndef PREFERRED_DEBUGGING_TYPE 147 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 148 #endif 149 150 /* The size of DWARF addresses should be the same as the size of symbols 151 in the target file format. */ 152 #define DWARF2_ADDR_SIZE (TARGET_64BIT ? 8 : 4) 153 154 /* By default, turn on GDB extensions. */ 155 #define DEFAULT_GDB_EXTENSIONS 1 156 157 /* By default, produce dwarf version 2 format debugging output in response 158 to the ‘-g’ option. */ 159 #define DWARF2_DEBUGGING_INFO 1 160 161 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 162 #define DWARF_FRAME_REGNUM(REGNO) loongarch_dwarf_regno[REGNO] 163 164 /* The DWARF 2 CFA column which tracks the return address. */ 165 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 166 167 /* Before the prologue, RA lives in r1. */ 168 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 169 170 /* Describe how we implement __builtin_eh_return. */ 171 #define EH_RETURN_DATA_REGNO(N) \ 172 ((N) < (4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 173 174 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) 175 176 #define EH_USES(N) loongarch_eh_uses (N) 177 178 /* Offsets recorded in opcodes are a multiple of this alignment factor. 179 The default for this in 64-bit mode is 8, which causes problems with 180 SFmode register saves. */ 181 #define DWARF_CIE_DATA_ALIGNMENT -4 182 183 /* Target machine storage layout. */ 184 185 #define BITS_BIG_ENDIAN 0 186 #define BYTES_BIG_ENDIAN 0 187 #define WORDS_BIG_ENDIAN 0 188 189 #define MAX_BITS_PER_WORD 64 190 191 /* Width of a word, in units (bytes). */ 192 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 193 #ifndef IN_LIBGCC2 194 #define MIN_UNITS_PER_WORD 4 195 #endif 196 197 /* For LARCH, width of a floating point register. */ 198 #define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4) 199 200 /* The largest size of value that can be held in floating-point 201 registers and moved with a single instruction. */ 202 #define UNITS_PER_HWFPVALUE \ 203 (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG) 204 205 /* The largest size of value that can be held in floating-point 206 registers. */ 207 #define UNITS_PER_FPVALUE \ 208 (TARGET_SOFT_FLOAT ? 0 \ 209 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 210 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 211 212 /* The number of bytes in a double. */ 213 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 214 215 /* Set the sizes of the core types. */ 216 #define SHORT_TYPE_SIZE 16 217 #define INT_TYPE_SIZE 32 218 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 219 #define LONG_LONG_TYPE_SIZE 64 220 221 #define FLOAT_TYPE_SIZE 32 222 #define DOUBLE_TYPE_SIZE 64 223 #define LONG_DOUBLE_TYPE_SIZE (TARGET_64BIT ? 128 : 64) 224 225 /* Define the sizes of fixed-point types. */ 226 #define SHORT_FRACT_TYPE_SIZE 8 227 #define FRACT_TYPE_SIZE 16 228 #define LONG_FRACT_TYPE_SIZE 32 229 #define LONG_LONG_FRACT_TYPE_SIZE 64 230 231 #define SHORT_ACCUM_TYPE_SIZE 16 232 #define ACCUM_TYPE_SIZE 32 233 #define LONG_ACCUM_TYPE_SIZE 64 234 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) 235 236 /* long double is not a fixed mode, but the idea is that, if we 237 support long double, we also want a 128-bit integer type. */ 238 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 239 240 /* Width in bits of a pointer. */ 241 #ifndef POINTER_SIZE 242 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) 243 #endif 244 245 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 246 #define PARM_BOUNDARY BITS_PER_WORD 247 248 /* Allocation boundary (in *bits*) for the code of a function. */ 249 #define FUNCTION_BOUNDARY 32 250 251 /* Alignment of field after `int : 0' in a structure. */ 252 #define EMPTY_FIELD_BOUNDARY 32 253 254 /* Number of bits which any structure or union's size must be a multiple of. 255 Each structure or union's size is rounded up to a multiple of this. */ 256 #define STRUCTURE_SIZE_BOUNDARY 8 257 258 /* There is no point aligning anything to a rounder boundary than 259 LONG_DOUBLE_TYPE_SIZE. */ 260 #define BIGGEST_ALIGNMENT (LONG_DOUBLE_TYPE_SIZE) 261 262 /* All accesses must be aligned. */ 263 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN) 264 265 /* Define this if you wish to imitate the way many other C compilers 266 handle alignment of bitfields and the structures that contain 267 them. 268 269 The behavior is that the type written for a bit-field (`int', 270 `short', or other integer type) imposes an alignment for the 271 entire structure, as if the structure really did contain an 272 ordinary field of that type. In addition, the bit-field is placed 273 within the structure so that it would fit within such a field, 274 not crossing a boundary for it. 275 276 Thus, on most machines, a bit-field whose type is written as `int' 277 would not cross a four-byte boundary, and would force four-byte 278 alignment for the whole structure. (The alignment used may not 279 be four bytes; it is controlled by the other alignment 280 parameters.) 281 282 If the macro is defined, its definition should be a C expression; 283 a nonzero value for the expression enables this behavior. */ 284 285 #define PCC_BITFIELD_TYPE_MATTERS 1 286 287 /* If defined, a C expression to compute the alignment for a static 288 variable. TYPE is the data type, and ALIGN is the alignment that 289 the object would ordinarily have. The value of this macro is used 290 instead of that alignment to align the object. 291 292 If this macro is not defined, then ALIGN is used. 293 294 One use of this macro is to increase alignment of medium-size 295 data to make it all fit in fewer cache lines. Another is to 296 cause character arrays to be word-aligned so that `strcpy' calls 297 that copy constants to character arrays can be done inline. */ 298 299 #undef DATA_ALIGNMENT 300 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 301 ((((ALIGN) < BITS_PER_WORD) \ 302 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 303 || TREE_CODE (TYPE) == UNION_TYPE \ 304 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 305 306 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 307 character arrays to be word-aligned so that `strcpy' calls that copy 308 constants to character arrays can be done inline, and 'strcmp' can be 309 optimised to use word loads. */ 310 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 311 312 /* Define if operations between registers always perform the operation 313 on the full register even if a narrower mode is specified. */ 314 #define WORD_REGISTER_OPERATIONS 1 315 316 /* When in 64-bit mode, move insns will sign extend SImode and FCCmode 317 moves. All other references are zero extended. */ 318 #define LOAD_EXTEND_OP(MODE) \ 319 (TARGET_64BIT && ((MODE) == SImode || (MODE) == FCCmode) ? SIGN_EXTEND \ 320 : ZERO_EXTEND) 321 322 /* Define this macro if it is advisable to hold scalars in registers 323 in a wider mode than that declared by the program. In such cases, 324 the value is constrained to be within the bounds of the declared 325 type, but kept valid in the wider mode. The signedness of the 326 extension may differ from that of the type. */ 327 328 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 329 if (GET_MODE_CLASS (MODE) == MODE_INT \ 330 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 331 { \ 332 if ((MODE) == SImode) \ 333 (UNSIGNEDP) = 0; \ 334 (MODE) = Pmode; \ 335 } 336 337 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 338 Extensions of pointers to word_mode must be signed. */ 339 #define POINTERS_EXTEND_UNSIGNED false 340 341 /* Define if loading short immediate values into registers sign extends. */ 342 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 343 344 /* The clz.{w/d} instructions have the natural values at 0. */ 345 346 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 347 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 348 349 /* Standard register usage. */ 350 351 /* Number of hardware registers. We have: 352 353 - 32 integer registers 354 - 32 floating point registers 355 - 8 condition code registers 356 - 2 fake registers: 357 - ARG_POINTER_REGNUM 358 - FRAME_POINTER_REGNUM 359 */ 360 361 #define FIRST_PSEUDO_REGISTER 74 362 363 /* zero, tp, sp and x are fixed. */ 364 #define FIXED_REGISTERS \ 365 { /* General registers. */ \ 366 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 368 /* Floating-point registers. */ \ 369 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 370 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 371 /* Others. */ \ 372 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} 373 374 /* The call RTLs themselves clobber ra. */ 375 #define CALL_USED_REGISTERS \ 376 { /* General registers. */ \ 377 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 378 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 379 /* Floating-point registers. */ \ 380 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 381 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 382 /* Others. */ \ 383 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 384 385 /* Internal macros to classify a register number as to whether it's a 386 general purpose register, a floating point register, or a status 387 register. */ 388 389 #define GP_REG_FIRST 0 390 #define GP_REG_LAST 31 391 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 392 393 #define FP_REG_FIRST 32 394 #define FP_REG_LAST 63 395 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 396 397 /* The DWARF 2 CFA column which tracks the return address from a 398 signal handler context. This means that to maintain backwards 399 compatibility, no hard register can be assigned this column if it 400 would need to be handled by the DWARF unwinder. */ 401 #define DWARF_ALT_FRAME_RETURN_COLUMN 72 402 403 #define FCC_REG_FIRST 64 404 #define FCC_REG_LAST 71 405 #define FCC_REG_NUM (FCC_REG_LAST - FCC_REG_FIRST + 1) 406 407 #define GP_REG_P(REGNO) \ 408 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 409 #define FP_REG_P(REGNO) \ 410 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 411 #define FCC_REG_P(REGNO) \ 412 ((unsigned int) ((int) (REGNO) - FCC_REG_FIRST) < FCC_REG_NUM) 413 414 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 415 416 /* Select a register mode required for caller save of hard regno REGNO. */ 417 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 418 loongarch_hard_regno_caller_save_mode (REGNO, NREGS, MODE) 419 420 /* Register to use for pushing function arguments. */ 421 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 3) 422 423 /* These two registers don't really exist: they get eliminated to either 424 the stack or hard frame pointer. */ 425 #define ARG_POINTER_REGNUM 72 426 #define FRAME_POINTER_REGNUM 73 427 428 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 22) 429 430 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 431 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 432 433 /* Register in which static-chain is passed to a function. */ 434 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 20) /* $t8 */ 435 436 #define GP_TEMP_FIRST (GP_REG_FIRST + 12) 437 #define LARCH_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1) 438 #define LARCH_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST) 439 #define LARCH_PROLOGUE_TEMP3_REGNUM (GP_TEMP_FIRST + 2) 440 #define LARCH_EPILOGUE_TEMP_REGNUM (GP_TEMP_FIRST) 441 442 #define CALLEE_SAVED_REG_NUMBER(REGNO) \ 443 ((REGNO) >= 22 && (REGNO) <= 31 ? (REGNO) - 22 : -1) 444 445 #define LARCH_PROLOGUE_TEMP(MODE) \ 446 gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP_REGNUM) 447 #define LARCH_PROLOGUE_TEMP2(MODE) \ 448 gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP2_REGNUM) 449 #define LARCH_PROLOGUE_TEMP3(MODE) \ 450 gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP3_REGNUM) 451 #define LARCH_EPILOGUE_TEMP(MODE) \ 452 gen_rtx_REG (MODE, LARCH_EPILOGUE_TEMP_REGNUM) 453 454 /* Define this macro if it is as good or better to call a constant 455 function address than to call an address kept in a register. */ 456 #define NO_FUNCTION_CSE 1 457 458 #define THREAD_POINTER_REGNUM (GP_REG_FIRST + 2) 459 460 /* Define the classes of registers for register constraints in the 461 machine description. Also define ranges of constants. 462 463 One of the classes must always be named ALL_REGS and include all hard regs. 464 If there is more than one class, another class must be named NO_REGS 465 and contain no registers. 466 467 The name GENERAL_REGS must be the name of a class (or an alias for 468 another name such as ALL_REGS). This is the class of registers 469 that is allowed by "r" in a register constraint. 470 Also, registers outside this class are allocated only when 471 instructions express preferences for them. 472 473 The classes must be numbered in nondecreasing order; that is, 474 a larger-numbered class must never be contained completely 475 in a smaller-numbered class. 476 477 For any two classes, it is very desirable that there be another 478 class that represents their union. */ 479 480 enum reg_class 481 { 482 NO_REGS, /* no registers in set */ 483 SIBCALL_REGS, /* registers used by indirect sibcalls */ 484 JIRL_REGS, /* registers used by indirect calls */ 485 CSR_REGS, /* integer registers except for $r0 and $r1 for lcsr. */ 486 GR_REGS, /* integer registers */ 487 FP_REGS, /* floating point registers */ 488 FCC_REGS, /* status registers (fp status) */ 489 FRAME_REGS, /* arg pointer and frame pointer */ 490 ALL_REGS, /* all registers */ 491 LIM_REG_CLASSES /* max value + 1 */ 492 }; 493 494 #define N_REG_CLASSES (int) LIM_REG_CLASSES 495 496 #define GENERAL_REGS GR_REGS 497 498 /* An initializer containing the names of the register classes as C 499 string constants. These names are used in writing some of the 500 debugging dumps. */ 501 502 #define REG_CLASS_NAMES \ 503 { \ 504 "NO_REGS", \ 505 "SIBCALL_REGS", \ 506 "JIRL_REGS", \ 507 "CSR_REGS", \ 508 "GR_REGS", \ 509 "FP_REGS", \ 510 "FCC_REGS", \ 511 "FRAME_REGS", \ 512 "ALL_REGS" \ 513 } 514 515 /* An initializer containing the contents of the register classes, 516 as integers which are bit masks. The Nth integer specifies the 517 contents of class N. The way the integer MASK is interpreted is 518 that register R is in the class if `MASK & (1 << R)' is 1. 519 520 When the machine has more than 32 registers, an integer does not 521 suffice. Then the integers are replaced by sub-initializers, 522 braced groupings containing several integers. Each 523 sub-initializer must be suitable as an initializer for the type 524 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 525 526 #define REG_CLASS_CONTENTS \ 527 { \ 528 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 529 { 0x001fd000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ 530 { 0xff9ffff0, 0x00000000, 0x00000000 }, /* JIRL_REGS */ \ 531 { 0xfffffffc, 0x00000000, 0x00000000 }, /* CSR_REGS */ \ 532 { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 533 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 534 { 0x00000000, 0x00000000, 0x000000ff }, /* FCC_REGS */ \ 535 { 0x00000000, 0x00000000, 0x00000300 }, /* FRAME_REGS */ \ 536 { 0xffffffff, 0xffffffff, 0x000003ff } /* ALL_REGS */ \ 537 } 538 539 /* A C expression whose value is a register class containing hard 540 register REGNO. In general there is more that one such class; 541 choose a class which is "minimal", meaning that no smaller class 542 also contains the register. */ 543 544 #define REGNO_REG_CLASS(REGNO) loongarch_regno_to_class[(REGNO)] 545 546 /* A macro whose definition is the name of the class to which a 547 valid base register must belong. A base register is one used in 548 an address which is the register value plus a displacement. */ 549 550 #define BASE_REG_CLASS (GR_REGS) 551 552 /* A macro whose definition is the name of the class to which a 553 valid index register must belong. An index register is one used 554 in an address where its value is either multiplied by a scale 555 factor or added to another register (as well as added to a 556 displacement). */ 557 558 #define INDEX_REG_CLASS GR_REGS 559 560 /* We generally want to put call-clobbered registers ahead of 561 call-saved ones. (IRA expects this.) */ 562 563 #define REG_ALLOC_ORDER \ 564 { /* Call-clobbered GPRs. */ \ 565 12, 13, 14, 15, 16, 17, 18, 19, 20, 4, 5, 6, 7, 8, 9, 10, 11, 1, \ 566 /* Call-saved GPRs. */ \ 567 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 568 /* GPRs that can never be exposed to the register allocator. */ \ 569 0, 2, 3, 21, 22, \ 570 /* Call-clobbered FPRs. */ \ 571 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 572 48, 49, 50, 51,52, 53, 54, 55, \ 573 56, 57, 58, 59, 60, 61, 62, 63, \ 574 /* None of the remaining classes have defined call-saved \ 575 registers. */ \ 576 64, 65, 66, 67, 68, 69, 70, 71, 72, 73} 577 578 #define IMM_BITS 12 579 #define IMM_REACH (HOST_WIDE_INT_1 << IMM_BITS) 580 #define HWIT_1U HOST_WIDE_INT_1U 581 582 /* True if VALUE is an unsigned 6-bit number. */ 583 584 #define UIMM6_OPERAND(VALUE) (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 585 586 /* True if VALUE is a signed 10-bit number. */ 587 588 #define IMM10_OPERAND(VALUE) ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 589 590 /* True if VALUE is a signed 12-bit number. */ 591 592 #define IMM12_OPERAND(VALUE) \ 593 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH / 2 < IMM_REACH) 594 595 /* True if VALUE is a signed 16-bit number. */ 596 597 #define IMM16_OPERAND(VALUE) \ 598 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 599 600 /* True if VALUE is an unsigned 12-bit number. */ 601 602 #define IMM12_OPERAND_UNSIGNED(VALUE) \ 603 (((VALUE) & ~(unsigned HOST_WIDE_INT) (IMM_REACH - 1)) == 0) 604 605 /* True if VALUE can be loaded into a register using LU12I. */ 606 607 #define LU12I_OPERAND(VALUE) \ 608 (((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) == ((HWIT_1U << 31) - IMM_REACH) \ 609 || ((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) + IMM_REACH == 0) 610 611 /* True if VALUE can be loaded into a register using LU32I. */ 612 613 #define LU32I_OPERAND(VALUE) \ 614 (((VALUE) | (((HWIT_1U << 19) - 1) << 32)) == (((HWIT_1U << 19) - 1) << 32) \ 615 || ((VALUE) | (((HWIT_1U << 19) - 1) << 32)) + (HWIT_1U << 32) == 0) 616 617 /* True if VALUE can be loaded into a register using LU52I. */ 618 619 #define HWIT_UC_0xFFF HOST_WIDE_INT_UC(0xfff) 620 #define LU52I_OPERAND(VALUE) \ 621 (((VALUE) | (HWIT_UC_0xFFF << 52)) == (HWIT_UC_0xFFF << 52)) 622 623 /* Return a value X with the low 12 bits clear, and such that 624 VALUE - X is a signed 12-bit value. */ 625 626 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH / 2)) & ~(IMM_REACH - 1)) 627 628 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) 629 630 #define IMM12_INT(X) IMM12_OPERAND (INTVAL (X)) 631 #define IMM12_INT_UNSIGNED(X) IMM12_OPERAND_UNSIGNED (INTVAL (X)) 632 #define LU12I_INT(X) LU12I_OPERAND (INTVAL (X)) 633 #define LU32I_INT(X) LU32I_OPERAND (INTVAL (X)) 634 #define LU52I_INT(X) LU52I_OPERAND (INTVAL (X)) 635 #define LARCH_U12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) 636 #define LARCH_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) 637 #define LARCH_16BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -32768, 32767)) 638 #define LARCH_SHIFT_2_OFFSET_P(OFFSET) (((OFFSET) & 0x3) == 0) 639 640 /* Return the maximum number of consecutive registers 641 needed to represent mode MODE in a register of class CLASS. */ 642 643 #define CLASS_MAX_NREGS(CLASS, MODE) loongarch_class_max_nregs (CLASS, MODE) 644 645 /* Stack layout; function entry, exit and calling. */ 646 647 #define STACK_GROWS_DOWNWARD 1 648 649 #define FRAME_GROWS_DOWNWARD 1 650 651 #define RETURN_ADDR_RTX loongarch_return_addr 652 653 /* Similarly, don't use the least-significant bit to tell pointers to 654 code from vtable index. */ 655 656 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 657 658 #define ELIMINABLE_REGS \ 659 { \ 660 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 661 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 662 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 663 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 664 } 665 666 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 667 (OFFSET) = loongarch_initial_elimination_offset ((FROM), (TO)) 668 669 /* Allocate stack space for arguments at the beginning of each function. */ 670 #define ACCUMULATE_OUTGOING_ARGS 1 671 672 /* The argument pointer always points to the first argument. */ 673 #define FIRST_PARM_OFFSET(FNDECL) 0 674 675 #define REG_PARM_STACK_SPACE(FNDECL) 0 676 677 /* Define this if it is the responsibility of the caller to 678 allocate the area reserved for arguments passed in registers. 679 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 680 of this macro is to determine whether the space is included in 681 `crtl->outgoing_args_size'. */ 682 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 683 684 #define STACK_BOUNDARY (TARGET_ABI_LP64 ? 128 : 64) 685 686 /* Symbolic macros for the registers used to return integer and floating 687 point values. */ 688 689 #define GP_RETURN (GP_REG_FIRST + 4) 690 #define FP_RETURN ((TARGET_SOFT_FLOAT_ABI) ? GP_RETURN : (FP_REG_FIRST + 0)) 691 692 #define MAX_ARGS_IN_REGISTERS 8 693 694 /* Symbolic macros for the first/last argument registers. */ 695 696 #define GP_ARG_FIRST (GP_REG_FIRST + 4) 697 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 698 #define FP_ARG_FIRST (FP_REG_FIRST + 0) 699 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 700 701 /* 1 if N is a possible register number for function argument passing. 702 We have no FP argument registers when soft-float. */ 703 704 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ 705 #define FUNCTION_ARG_REGNO_P(N) \ 706 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ 707 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) 708 709 typedef struct { 710 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ 711 unsigned int num_gprs; 712 713 /* Number of floating-point registers used so far, likewise. */ 714 unsigned int num_fprs; 715 716 } CUMULATIVE_ARGS; 717 718 /* Initialize a variable CUM of type CUMULATIVE_ARGS 719 for a call to a function whose data type is FNTYPE. 720 For a library call, FNTYPE is 0. */ 721 722 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 723 memset (&(CUM), 0, sizeof (CUM)) 724 725 #define EPILOGUE_USES(REGNO) loongarch_epilogue_uses (REGNO) 726 727 /* Treat LOC as a byte offset from the stack pointer and round it up 728 to the next fully-aligned offset. */ 729 #define LARCH_STACK_ALIGN(LOC) \ 730 (TARGET_ABI_LP64 ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) 731 732 #define MCOUNT_NAME "_mcount" 733 734 /* Emit rtl for profiling. Output assembler code to FILE 735 to call "_mcount" for profiling a function entry. */ 736 #define PROFILE_HOOK(LABEL) \ 737 { \ 738 rtx fun, ra; \ 739 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ 740 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 741 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ 742 } 743 744 /* All the work done in PROFILE_HOOK, but still required. */ 745 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 746 747 #define NO_PROFILE_COUNTERS 1 748 749 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 750 the stack pointer does not matter. The value is tested only in 751 functions that have frame pointers. 752 No definition is equivalent to always zero. */ 753 754 #define EXIT_IGNORE_STACK 1 755 756 /* Trampolines are a block of code followed by two pointers. */ 757 758 #define TRAMPOLINE_CODE_SIZE 16 759 #define TRAMPOLINE_SIZE \ 760 ((Pmode == SImode) ? TRAMPOLINE_CODE_SIZE \ 761 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) 762 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE 763 764 /* loongarch_trampoline_init calls this library function to flush 765 program and data caches. */ 766 767 #ifndef CACHE_FLUSH_FUNC 768 #define CACHE_FLUSH_FUNC "_flush_cache" 769 #endif 770 771 /* Addressing modes, and classification of registers for them. */ 772 773 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 774 loongarch_regno_mode_ok_for_base_p (REGNO, VOIDmode, 1) 775 776 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 777 loongarch_regno_mode_ok_for_base_p (REGNO, MODE, 1) 778 779 /* Maximum number of registers that can appear in a valid memory address. */ 780 781 #define MAX_REGS_PER_ADDRESS 2 782 783 /* Check for constness inline but use loongarch_legitimate_address_p 784 to check whether a constant really is an address. */ 785 786 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && memory_address_p (SImode, X)) 787 788 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 789 'the start of the function that this code is output in'. */ 790 791 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 792 do \ 793 { \ 794 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 795 asm_fprintf ((FILE), "%U%s", \ 796 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 797 else \ 798 asm_fprintf ((FILE), "%U%s", (NAME)); \ 799 } \ 800 while (0) 801 802 #define CASE_VECTOR_MODE Pmode 803 804 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) Pmode 805 806 /* Define this as 1 if `char' should by default be signed; else as 0. */ 807 #ifndef DEFAULT_SIGNED_CHAR 808 #define DEFAULT_SIGNED_CHAR 1 809 #endif 810 811 /* The SPARC port says: 812 The maximum number of bytes that a single instruction 813 can move quickly between memory and registers or between 814 two memory locations. */ 815 #define MOVE_MAX UNITS_PER_WORD 816 #define MAX_MOVE_MAX 8 817 818 /* The SPARC port says: 819 Nonzero if access to memory by bytes is slow and undesirable. 820 For RISC chips, it means that access to memory by bytes is no 821 better than access by words when possible, so grab a whole word 822 and maybe make use of that. */ 823 #define SLOW_BYTE_ACCESS 1 824 825 /* Standard LoongArch integer shifts truncate the shift amount to the 826 width of the shifted operand. */ 827 #define SHIFT_COUNT_TRUNCATED 1 828 829 /* Specify the machine mode that pointers have. 830 After generation of rtl, the compiler makes no further distinction 831 between pointers and any other objects of this machine mode. */ 832 833 #ifndef Pmode 834 #define Pmode (TARGET_64BIT ? DImode : SImode) 835 #endif 836 837 /* Give call MEMs SImode since it is the "most permissive" mode 838 for both 32-bit and 64-bit targets. */ 839 840 #define FUNCTION_MODE SImode 841 842 /* We allocate $fcc registers by hand and can't cope with moves of 843 CCmode registers to and from pseudos (or memory). */ 844 #define AVOID_CCMODE_COPIES 845 846 /* A C expression for the cost of a branch instruction. A value of 847 1 is the default; other values are interpreted relative to that. */ 848 849 #define BRANCH_COST(speed_p, predictable_p) loongarch_branch_cost 850 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 851 852 /* Return the asm template for a conditional branch instruction. 853 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 854 its operands. */ 855 #define LARCH_BRANCH(OPCODE, OPERANDS) OPCODE "\t" OPERANDS 856 857 /* Control the assembler format that we output. */ 858 859 /* Output to assembler file text saying following lines 860 may contain character constants, extra white space, comments, etc. */ 861 862 #ifndef ASM_APP_ON 863 #define ASM_APP_ON " #APP\n" 864 #endif 865 866 /* Output to assembler file text saying following lines 867 no longer contain unusual constructs. */ 868 869 #ifndef ASM_APP_OFF 870 #define ASM_APP_OFF " #NO_APP\n" 871 #endif 872 873 #define REGISTER_NAMES \ 874 { "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \ 875 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", \ 876 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \ 877 "$r24", "$r25", "$r26", "$r27", "$r28", "$r29", "$r30", "$r31", \ 878 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 879 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 880 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 881 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 882 "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4","$fcc5","$fcc6","$fcc7", \ 883 "$arg", "$frame"} 884 885 /* This macro defines additional names for hard registers. */ 886 887 #define ADDITIONAL_REGISTER_NAMES \ 888 { \ 889 { "zero", 0 + GP_REG_FIRST }, \ 890 { "ra", 1 + GP_REG_FIRST }, \ 891 { "tp", 2 + GP_REG_FIRST }, \ 892 { "sp", 3 + GP_REG_FIRST }, \ 893 { "a0", 4 + GP_REG_FIRST }, \ 894 { "a1", 5 + GP_REG_FIRST }, \ 895 { "a2", 6 + GP_REG_FIRST }, \ 896 { "a3", 7 + GP_REG_FIRST }, \ 897 { "a4", 8 + GP_REG_FIRST }, \ 898 { "a5", 9 + GP_REG_FIRST }, \ 899 { "a6", 10 + GP_REG_FIRST }, \ 900 { "a7", 11 + GP_REG_FIRST }, \ 901 { "t0", 12 + GP_REG_FIRST }, \ 902 { "t1", 13 + GP_REG_FIRST }, \ 903 { "t2", 14 + GP_REG_FIRST }, \ 904 { "t3", 15 + GP_REG_FIRST }, \ 905 { "t4", 16 + GP_REG_FIRST }, \ 906 { "t5", 17 + GP_REG_FIRST }, \ 907 { "t6", 18 + GP_REG_FIRST }, \ 908 { "t7", 19 + GP_REG_FIRST }, \ 909 { "t8", 20 + GP_REG_FIRST }, \ 910 { "x", 21 + GP_REG_FIRST }, \ 911 { "fp", 22 + GP_REG_FIRST }, \ 912 { "s0", 23 + GP_REG_FIRST }, \ 913 { "s1", 24 + GP_REG_FIRST }, \ 914 { "s2", 25 + GP_REG_FIRST }, \ 915 { "s3", 26 + GP_REG_FIRST }, \ 916 { "s4", 27 + GP_REG_FIRST }, \ 917 { "s5", 28 + GP_REG_FIRST }, \ 918 { "s6", 29 + GP_REG_FIRST }, \ 919 { "s7", 30 + GP_REG_FIRST }, \ 920 { "s8", 31 + GP_REG_FIRST }, \ 921 { "v0", 4 + GP_REG_FIRST }, \ 922 { "v1", 5 + GP_REG_FIRST } \ 923 } 924 925 /* Globalizing directive for a label. */ 926 #define GLOBAL_ASM_OP "\t.globl\t" 927 928 /* This says how to output an external. It would be possible not to 929 output anything and let undefined symbol become external. However 930 the assembler uses length information on externals to allocate in 931 data/sdata bss/sbss, thereby saving exec time. */ 932 933 #undef ASM_OUTPUT_EXTERNAL 934 #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) \ 935 loongarch_output_external (STREAM, DECL, NAME) 936 937 /* This is how to store into the string LABEL 938 the symbol_ref name of an internal numbered label where 939 PREFIX is the class of label and NUM is the number within the class. 940 This is suitable for output with `assemble_name'. */ 941 942 #undef ASM_GENERATE_INTERNAL_LABEL 943 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 944 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM)) 945 946 /* Print debug labels as "foo = ." rather than "foo:" because they should 947 represent a byte pointer rather than an ISA-encoded address. This is 948 particularly important for code like: 949 950 $LFBxxx = . 951 .cfi_startproc 952 ... 953 .section .gcc_except_table,... 954 ... 955 .uleb128 foo-$LFBxxx 956 957 The .uleb128 requies $LFBxxx to match the FDE start address, which is 958 likewise a byte pointer rather than an ISA-encoded address. 959 960 At the time of writing, this hook is not used for the function end 961 label: 962 963 $LFExxx: 964 .end foo 965 966 */ 967 968 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 969 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) 970 971 /* This is how to output an element of a case-vector that is absolute. */ 972 973 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 974 fprintf (STREAM, "\t%s\t%sL%d\n", ptr_mode == DImode ? ".dword" : ".word", \ 975 LOCAL_LABEL_PREFIX, VALUE) 976 977 /* This is how to output an element of a case-vector. */ 978 979 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 980 do \ 981 { \ 982 fprintf (STREAM, "\t%s\t%sL%d-%sL%d\n", \ 983 ptr_mode == DImode ? ".dword" : ".word", LOCAL_LABEL_PREFIX, \ 984 VALUE, LOCAL_LABEL_PREFIX, REL); \ 985 } \ 986 while (0) 987 988 #define JUMP_TABLES_IN_TEXT_SECTION 0 989 990 /* This is how to output an assembler line 991 that says to advance the location counter 992 to a multiple of 2**LOG bytes. */ 993 994 #define ASM_OUTPUT_ALIGN(STREAM, LOG) fprintf (STREAM, "\t.align\t%d\n", (LOG)) 995 996 /* This is how to output an assembler line to advance the location 997 counter by SIZE bytes. */ 998 999 #undef ASM_OUTPUT_SKIP 1000 #define ASM_OUTPUT_SKIP(STREAM, SIZE) \ 1001 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", (SIZE)) 1002 1003 /* This is how to output a string. */ 1004 #undef ASM_OUTPUT_ASCII 1005 #define ASM_OUTPUT_ASCII loongarch_output_ascii 1006 1007 /* Define the strings to put out for each section in the object file. */ 1008 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 1009 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 1010 1011 #undef READONLY_DATA_SECTION_ASM_OP 1012 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" /* read-only data */ 1013 1014 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 1015 do \ 1016 { \ 1017 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,%s,0\n", \ 1018 TARGET_64BIT ? "addi.d" : "addi.w", \ 1019 reg_names[STACK_POINTER_REGNUM], \ 1020 reg_names[STACK_POINTER_REGNUM], \ 1021 TARGET_64BIT ? "st.d" : "st.w", reg_names[REGNO], \ 1022 reg_names[STACK_POINTER_REGNUM]); \ 1023 } \ 1024 while (0) 1025 1026 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 1027 do \ 1028 { \ 1029 fprintf (STREAM, "\t%s\t%s,%s,0\n\t%s\t%s,%s,8\n", \ 1030 TARGET_64BIT ? "ld.d" : "ld.w", reg_names[REGNO], \ 1031 reg_names[STACK_POINTER_REGNUM], \ 1032 TARGET_64BIT ? "addi.d" : "addi.w", \ 1033 reg_names[STACK_POINTER_REGNUM], \ 1034 reg_names[STACK_POINTER_REGNUM]); \ 1035 } \ 1036 while (0) 1037 1038 /* How to start an assembler comment. 1039 The leading space is important (the loongarch native assembler requires it). 1040 */ 1041 #ifndef ASM_COMMENT_START 1042 #define ASM_COMMENT_START " #" 1043 #endif 1044 1045 #undef SIZE_TYPE 1046 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 1047 1048 #undef PTRDIFF_TYPE 1049 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 1050 1051 /* The maximum number of bytes that can be copied by one iteration of 1052 a cpymemsi loop; see loongarch_block_move_loop. */ 1053 #define LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) 1054 1055 /* The maximum number of bytes that can be copied by a straight-line 1056 implementation of cpymemsi; see loongarch_block_move_straight. We want 1057 to make sure that any loop-based implementation will iterate at 1058 least twice. */ 1059 #define LARCH_MAX_MOVE_BYTES_STRAIGHT (LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) 1060 1061 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These 1062 values were determined experimentally by benchmarking with CSiBE. 1063 */ 1064 #define LARCH_CALL_RATIO 8 1065 1066 /* Any loop-based implementation of cpymemsi will have at least 1067 LARCH_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory 1068 moves, so allow individual copies of fewer elements. 1069 1070 When cpymemsi is not available, use a value approximating 1071 the length of a memcpy call sequence, so that move_by_pieces 1072 will generate inline code if it is shorter than a function call. 1073 Since move_by_pieces_ninsns counts memory-to-memory moves, but 1074 we'll have to generate a load/store pair for each, halve the 1075 value of LARCH_CALL_RATIO to take that into account. */ 1076 1077 #define MOVE_RATIO(speed) \ 1078 (HAVE_cpymemsi \ 1079 ? LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD \ 1080 : CLEAR_RATIO (speed) / 2) 1081 1082 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 1083 of the length of a memset call, but use the default otherwise. */ 1084 1085 #define CLEAR_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO) 1086 1087 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 1088 optimizing for size adjust the ratio to account for the overhead of 1089 loading the constant and replicating it across the word. */ 1090 1091 #define SET_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO - 2) 1092 1093 #ifndef USED_FOR_TARGET 1094 extern const enum reg_class loongarch_regno_to_class[]; 1095 extern int loongarch_dwarf_regno[]; 1096 1097 /* Information about a function's frame layout. */ 1098 struct GTY (()) loongarch_frame_info 1099 { 1100 /* The size of the frame in bytes. */ 1101 HOST_WIDE_INT total_size; 1102 1103 /* Bit X is set if the function saves or restores GPR X. */ 1104 unsigned int mask; 1105 1106 /* Likewise FPR X. */ 1107 unsigned int fmask; 1108 1109 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */ 1110 unsigned save_libcall_adjustment; 1111 1112 /* Offsets of fixed-point and floating-point save areas from frame 1113 bottom. */ 1114 HOST_WIDE_INT gp_sp_offset; 1115 HOST_WIDE_INT fp_sp_offset; 1116 1117 /* Offset of virtual frame pointer from stack pointer/frame bottom. */ 1118 HOST_WIDE_INT frame_pointer_offset; 1119 1120 /* Offset of hard frame pointer from stack pointer/frame bottom. */ 1121 HOST_WIDE_INT hard_frame_pointer_offset; 1122 1123 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 1124 HOST_WIDE_INT arg_pointer_offset; 1125 }; 1126 1127 struct GTY (()) machine_function 1128 { 1129 /* The next floating-point condition-code register to allocate 1130 for 8CC targets, relative to FCC_REG_FIRST. */ 1131 unsigned int next_fcc; 1132 1133 /* The number of extra stack bytes taken up by register varargs. 1134 This area is allocated by the callee at the very top of the frame. */ 1135 int varargs_size; 1136 1137 /* The current frame information, calculated by loongarch_compute_frame_info. 1138 */ 1139 struct loongarch_frame_info frame; 1140 }; 1141 #endif 1142 1143 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1144 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) 1145 1146 /* Do emit .note.GNU-stack by default. */ 1147 #ifndef NEED_INDICATE_EXEC_STACK 1148 #define NEED_INDICATE_EXEC_STACK 1 1149 #endif 1150 1151 /* The `Q' extension is not yet supported. */ 1152 /* TODO: according to march. */ 1153 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) 1154 1155 /* The largest type that can be passed in floating-point registers. */ 1156 /* TODO: according to mabi. */ 1157 #define UNITS_PER_FP_ARG \ 1158 (TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT_ABI ? 8 : 4) : 0) 1159 1160 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) 1161 1162 /* LoongArch maintains ICache/DCache coherency by hardware, 1163 we just need "ibar" to avoid instruction hazard here. */ 1164 #undef CLEAR_INSN_CACHE 1165 #define CLEAR_INSN_CACHE(beg, end) __builtin_loongarch_ibar (0) 1166