| /llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 351 getShuffleExtract(ExtractElementInst * Ext0,ExtractElementInst * Ext1,unsigned PreferredExtractIndex=InvalidIndex) const getShuffleExtract() argument
401 isExtractExtractCheap(ExtractElementInst * Ext0,ExtractElementInst * Ext1,const Instruction & I,ExtractElementInst * & ConvertToShuffle,unsigned PreferredExtractIndex) isExtractExtractCheap() argument
533 foldExtExtCmp(ExtractElementInst * Ext0,ExtractElementInst * Ext1,Instruction & I) foldExtExtCmp() argument
552 foldExtExtBinop(ExtractElementInst * Ext0,ExtractElementInst * Ext1,Instruction & I) foldExtExtBinop() argument
599 auto *Ext1 = cast<ExtractElementInst>(I1); foldExtractExtract() local
1059 auto *Ext1 = cast<ExtractElementInst>(I1); foldExtractedCmps() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9418 SDValue Ext1 = Ext.getValue(1); LowerVectorExtend() local
10348 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, LowerVecReduce() local
10360 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, LowerVecReduce() local
13391 SDValue Ext1 = Mul.getOperand(1); PerformVQDMULHCombine() local
17260 SDValue Ext1 = PerformVECREDUCE_ADDCombine() local
19281 areExtractExts(Value * Ext1,Value * Ext2) areExtractExts() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15734 areExtractExts(Value * Ext1,Value * Ext2) areExtractExts() argument
15954 auto Ext1 = cast<Instruction>(I->getOperand(0)); shouldSinkOperands() local
17635 SDValue Ext1 = Op1.getOperand(0); performUADDVAddCombine() local
17683 SDValue Ext1 = Op1.getOperand(0); performUADDVZextCombine() local
20506 SDValue Ext0, Ext1; performExtBinopLoadFold() local
21360 const SDValue Ext1 = performSignExtendSetCCCombine() local
[all...] |
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 3027 Instruction *Ext0, *Ext1; foldICmpAddConstant() local
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 12824 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); tryToFoldExtendSelectLoad() local
13492 SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); foldSextSetcc() local
22325 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); scalarizeExtractedBinop() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3751 auto Ext1 = B.buildFPExt(F32, Src1, Flags); legalizeFPow() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44854 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, scalarizeExtEltFP() local
44878 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, scalarizeExtEltFP() local
57008 SDValue Ext1 = extractSubVector(InVec.getOperand(1), 0, DAG, DL, 128); combineEXTRACT_SUBVECTOR() local
57026 SDValue Ext1 = combineEXTRACT_SUBVECTOR() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15090 SDValue Ext1 = FirstInput.getOperand(0); DAGCombineBuildVector() local
|