1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDKernelCodeT.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600Defines.h"
24 #include "R600MachineFunctionInfo.h"
25 #include "R600RegisterInfo.h"
26 #include "SIDefines.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCSectionELF.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37
38 using namespace llvm;
39
40 // TODO: This should get the default rounding mode from the kernel. We just set
41 // the default here, but this could change if the OpenCL rounding mode pragmas
42 // are used.
43 //
44 // The denormal mode here should match what is reported by the OpenCL runtime
45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
47 //
48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
49 // precision, and leaves single precision to flush all and does not report
50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
51 // CL_FP_DENORM for both.
52 //
53 // FIXME: It seems some instructions do not support single precision denormals
54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
55 // and sin_f32, cos_f32 on most parts).
56
57 // We want to use these instructions, and using fp32 denormals also causes
58 // instructions to run at the double precision rate for the device so it's
59 // probably best to just report no single precision denormals.
getFPMode(const MachineFunction & F)60 static uint32_t getFPMode(const MachineFunction &F) {
61 const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
62 // TODO: Is there any real use for the flush in only / flush out only modes?
63
64 uint32_t FP32Denormals =
65 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
66
67 uint32_t FP64Denormals =
68 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69
70 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
71 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
72 FP_DENORM_MODE_SP(FP32Denormals) |
73 FP_DENORM_MODE_DP(FP64Denormals);
74 }
75
createAMDGPUAsmPrinterPass(TargetMachine & tm,MCStreamer & Streamer)76 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
77 MCStreamer &Streamer) {
78 return new AMDGPUAsmPrinter(tm, Streamer);
79 }
80
LLVMInitializeR600AsmPrinter()81 extern "C" void LLVMInitializeR600AsmPrinter() {
82 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
83 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
84 }
85
AMDGPUAsmPrinter(TargetMachine & TM,MCStreamer & Streamer)86 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
87 : AsmPrinter(TM, Streamer) {
88 DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
89 }
90
EmitEndOfAsmFile(Module & M)91 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
92
93 // This label is used to mark the end of the .text section.
94 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
95 OutStreamer.SwitchSection(TLOF.getTextSection());
96 MCSymbol *EndOfTextLabel =
97 OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
98 OutStreamer.EmitLabel(EndOfTextLabel);
99 }
100
runOnMachineFunction(MachineFunction & MF)101 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
102
103 // The starting address of all shader programs must be 256 bytes aligned.
104 MF.setAlignment(8);
105
106 SetupMachineFunction(MF);
107
108 EmitFunctionHeader();
109
110 MCContext &Context = getObjFileLowering().getContext();
111 const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
112 ELF::SHT_PROGBITS, 0,
113 SectionKind::getReadOnly());
114 OutStreamer.SwitchSection(ConfigSection);
115
116 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
117 SIProgramInfo KernelInfo;
118 if (STM.isAmdHsaOS()) {
119 getSIProgramInfo(KernelInfo, MF);
120 EmitAmdKernelCodeT(MF, KernelInfo);
121 OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
122 } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
123 getSIProgramInfo(KernelInfo, MF);
124 EmitProgramInfoSI(MF, KernelInfo);
125 } else {
126 EmitProgramInfoR600(MF);
127 }
128
129 DisasmLines.clear();
130 HexLines.clear();
131 DisasmLineMaxLen = 0;
132
133 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
134 EmitFunctionBody();
135
136 if (isVerbose()) {
137 const MCSectionELF *CommentSection
138 = Context.getELFSection(".AMDGPU.csdata",
139 ELF::SHT_PROGBITS, 0,
140 SectionKind::getReadOnly());
141 OutStreamer.SwitchSection(CommentSection);
142
143 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
144 OutStreamer.emitRawComment(" Kernel info:", false);
145 OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
146 false);
147 OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
148 false);
149 OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
150 false);
151 OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
152 false);
153 OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
154 false);
155 OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
156 false);
157 } else {
158 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
159 OutStreamer.emitRawComment(
160 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
161 }
162 }
163
164 if (STM.dumpCode() && DisasmEnabled) {
165
166 OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
167 ELF::SHT_NOTE, 0,
168 SectionKind::getReadOnly()));
169
170 for (size_t i = 0; i < DisasmLines.size(); ++i) {
171 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
172 Comment += " ; " + HexLines[i] + "\n";
173
174 OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
175 OutStreamer.EmitBytes(StringRef(Comment));
176 }
177 }
178
179 return false;
180 }
181
EmitProgramInfoR600(const MachineFunction & MF)182 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
183 unsigned MaxGPR = 0;
184 bool killPixel = false;
185 const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
186 TM.getSubtargetImpl()->getRegisterInfo());
187 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
188 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
189
190 for (const MachineBasicBlock &MBB : MF) {
191 for (const MachineInstr &MI : MBB) {
192 if (MI.getOpcode() == AMDGPU::KILLGT)
193 killPixel = true;
194 unsigned numOperands = MI.getNumOperands();
195 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
196 const MachineOperand &MO = MI.getOperand(op_idx);
197 if (!MO.isReg())
198 continue;
199 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
200
201 // Register with value > 127 aren't GPR
202 if (HWReg > 127)
203 continue;
204 MaxGPR = std::max(MaxGPR, HWReg);
205 }
206 }
207 }
208
209 unsigned RsrcReg;
210 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
211 // Evergreen / Northern Islands
212 switch (MFI->getShaderType()) {
213 default: // Fall through
214 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
215 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
216 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
217 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
218 }
219 } else {
220 // R600 / R700
221 switch (MFI->getShaderType()) {
222 default: // Fall through
223 case ShaderType::GEOMETRY: // Fall through
224 case ShaderType::COMPUTE: // Fall through
225 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
226 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
227 }
228 }
229
230 OutStreamer.EmitIntValue(RsrcReg, 4);
231 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
232 S_STACK_SIZE(MFI->StackSize), 4);
233 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
234 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
235
236 if (MFI->getShaderType() == ShaderType::COMPUTE) {
237 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
238 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
239 }
240 }
241
getSIProgramInfo(SIProgramInfo & ProgInfo,const MachineFunction & MF) const242 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
243 const MachineFunction &MF) const {
244 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
245 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
246 uint64_t CodeSize = 0;
247 unsigned MaxSGPR = 0;
248 unsigned MaxVGPR = 0;
249 bool VCCUsed = false;
250 bool FlatUsed = false;
251 const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
252 TM.getSubtargetImpl()->getRegisterInfo());
253
254 for (const MachineBasicBlock &MBB : MF) {
255 for (const MachineInstr &MI : MBB) {
256 // TODO: CodeSize should account for multiple functions.
257 CodeSize += MI.getDesc().Size;
258
259 unsigned numOperands = MI.getNumOperands();
260 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
261 const MachineOperand &MO = MI.getOperand(op_idx);
262 unsigned width = 0;
263 bool isSGPR = false;
264
265 if (!MO.isReg()) {
266 continue;
267 }
268 unsigned reg = MO.getReg();
269 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
270 reg == AMDGPU::VCC_HI) {
271 VCCUsed = true;
272 continue;
273 } else if (reg == AMDGPU::FLAT_SCR ||
274 reg == AMDGPU::FLAT_SCR_LO ||
275 reg == AMDGPU::FLAT_SCR_HI) {
276 FlatUsed = true;
277 continue;
278 }
279
280 switch (reg) {
281 default: break;
282 case AMDGPU::SCC:
283 case AMDGPU::EXEC:
284 case AMDGPU::M0:
285 continue;
286 }
287
288 if (AMDGPU::SReg_32RegClass.contains(reg)) {
289 isSGPR = true;
290 width = 1;
291 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
292 isSGPR = false;
293 width = 1;
294 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
295 isSGPR = true;
296 width = 2;
297 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
298 isSGPR = false;
299 width = 2;
300 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
301 isSGPR = false;
302 width = 3;
303 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
304 isSGPR = true;
305 width = 4;
306 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
307 isSGPR = false;
308 width = 4;
309 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
310 isSGPR = true;
311 width = 8;
312 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
313 isSGPR = false;
314 width = 8;
315 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
316 isSGPR = true;
317 width = 16;
318 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
319 isSGPR = false;
320 width = 16;
321 } else {
322 llvm_unreachable("Unknown register class");
323 }
324 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
325 unsigned maxUsed = hwReg + width - 1;
326 if (isSGPR) {
327 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
328 } else {
329 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
330 }
331 }
332 }
333 }
334
335 if (VCCUsed)
336 MaxSGPR += 2;
337
338 if (FlatUsed)
339 MaxSGPR += 2;
340
341 // We found the maximum register index. They start at 0, so add one to get the
342 // number of registers.
343 ProgInfo.NumVGPR = MaxVGPR + 1;
344 ProgInfo.NumSGPR = MaxSGPR + 1;
345
346 if (STM.hasSGPRInitBug()) {
347 if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG)
348 llvm_unreachable("Too many SGPRs used with the SGPR init bug");
349
350 ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
351 }
352
353 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
354 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
355 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
356 // register.
357 ProgInfo.FloatMode = getFPMode(MF);
358
359 // XXX: Not quite sure what this does, but sc seems to unset this.
360 ProgInfo.IEEEMode = 0;
361
362 // Do not clamp NAN to 0.
363 ProgInfo.DX10Clamp = 0;
364
365 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
366 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
367
368 ProgInfo.FlatUsed = FlatUsed;
369 ProgInfo.VCCUsed = VCCUsed;
370 ProgInfo.CodeLen = CodeSize;
371
372 unsigned LDSAlignShift;
373 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
374 // LDS is allocated in 64 dword blocks.
375 LDSAlignShift = 8;
376 } else {
377 // LDS is allocated in 128 dword blocks.
378 LDSAlignShift = 9;
379 }
380
381 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
382 MFI->getMaximumWorkGroupSize(MF);
383
384 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
385 ProgInfo.LDSBlocks =
386 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
387
388 // Scratch is allocated in 256 dword blocks.
389 unsigned ScratchAlignShift = 10;
390 // We need to program the hardware with the amount of scratch memory that
391 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
392 // scratch memory used per thread.
393 ProgInfo.ScratchBlocks =
394 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
395 1 << ScratchAlignShift) >> ScratchAlignShift;
396
397 ProgInfo.ComputePGMRSrc1 =
398 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
399 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
400 S_00B848_PRIORITY(ProgInfo.Priority) |
401 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
402 S_00B848_PRIV(ProgInfo.Priv) |
403 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
404 S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
405 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
406
407 ProgInfo.ComputePGMRSrc2 =
408 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
409 S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
410 S_00B84C_TGID_X_EN(1) |
411 S_00B84C_TGID_Y_EN(1) |
412 S_00B84C_TGID_Z_EN(1) |
413 S_00B84C_TG_SIZE_EN(1) |
414 S_00B84C_TIDIG_COMP_CNT(2) |
415 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
416 }
417
getRsrcReg(unsigned ShaderType)418 static unsigned getRsrcReg(unsigned ShaderType) {
419 switch (ShaderType) {
420 default: // Fall through
421 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
422 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
423 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
424 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
425 }
426 }
427
EmitProgramInfoSI(const MachineFunction & MF,const SIProgramInfo & KernelInfo)428 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
429 const SIProgramInfo &KernelInfo) {
430 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
431 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
432 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
433
434 if (MFI->getShaderType() == ShaderType::COMPUTE) {
435 OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
436
437 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
438
439 OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
440 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
441
442 OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
443 OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
444
445 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
446 // 0" comment but I don't see a corresponding field in the register spec.
447 } else {
448 OutStreamer.EmitIntValue(RsrcReg, 4);
449 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
450 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
451 if (STM.isVGPRSpillingEnabled(MFI)) {
452 OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
453 OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
454 }
455 }
456
457 if (MFI->getShaderType() == ShaderType::PIXEL) {
458 OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
459 OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
460 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
461 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
462 }
463 }
464
EmitAmdKernelCodeT(const MachineFunction & MF,const SIProgramInfo & KernelInfo) const465 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
466 const SIProgramInfo &KernelInfo) const {
467 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
468 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
469 amd_kernel_code_t header;
470
471 memset(&header, 0, sizeof(header));
472
473 header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
474 header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
475
476 header.struct_byte_size = sizeof(amd_kernel_code_t);
477
478 header.target_chip = STM.getAmdKernelCodeChipID();
479
480 header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
481
482 header.compute_pgm_resource_registers =
483 KernelInfo.ComputePGMRSrc1 |
484 (KernelInfo.ComputePGMRSrc2 << 32);
485
486 // Code Properties:
487 header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
488 AMD_CODE_PROPERTY_IS_PTR64;
489
490 if (KernelInfo.FlatUsed)
491 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
492
493 if (KernelInfo.ScratchBlocks)
494 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
495
496 header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
497 header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
498
499 // MFI->ABIArgOffset is the number of bytes for the kernel arguments
500 // plus 36. 36 is the number of bytes reserved at the begining of the
501 // input buffer to store work-group size information.
502 // FIXME: We should be adding the size of the implicit arguments
503 // to this value.
504 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
505
506 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
507 header.workitem_vgpr_count = KernelInfo.NumVGPR;
508
509 // FIXME: What values do I put for these alignments
510 header.kernarg_segment_alignment = 0;
511 header.group_segment_alignment = 0;
512 header.private_segment_alignment = 0;
513
514 header.code_type = 1; // HSA_EXT_CODE_KERNEL
515
516 header.wavefront_size = STM.getWavefrontSize();
517
518 const MCSectionELF *VersionSection = OutContext.getELFSection(".hsa.version",
519 ELF::SHT_PROGBITS, 0, SectionKind::getReadOnly());
520 OutStreamer.SwitchSection(VersionSection);
521 OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
522 Twine(header.hsail_version_major) + "." +
523 Twine(header.hsail_version_minor) + ":" +
524 "AMD:" +
525 Twine(header.amd_code_version_major) + "." +
526 Twine(header.amd_code_version_minor) + ":" +
527 "GFX8.1:0").str());
528
529 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
530
531 if (isVerbose()) {
532 OutStreamer.emitRawComment("amd_code_version_major = " +
533 Twine(header.amd_code_version_major), false);
534 OutStreamer.emitRawComment("amd_code_version_minor = " +
535 Twine(header.amd_code_version_minor), false);
536 OutStreamer.emitRawComment("struct_byte_size = " +
537 Twine(header.struct_byte_size), false);
538 OutStreamer.emitRawComment("target_chip = " +
539 Twine(header.target_chip), false);
540 OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
541 Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
542 OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
543 Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
544 OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
545 Twine((bool)(header.code_properties &
546 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
547 OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
548 Twine((bool)(header.code_properties &
549 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
550 OutStreamer.emitRawComment("private_element_size = 2 ", false);
551 OutStreamer.emitRawComment("is_ptr64 = " +
552 Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
553 OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
554 Twine(header.workitem_private_segment_byte_size),
555 false);
556 OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
557 Twine(header.workgroup_group_segment_byte_size),
558 false);
559 OutStreamer.emitRawComment("gds_segment_byte_size = " +
560 Twine(header.gds_segment_byte_size), false);
561 OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
562 Twine(header.kernarg_segment_byte_size), false);
563 OutStreamer.emitRawComment("wavefront_sgpr_count = " +
564 Twine(header.wavefront_sgpr_count), false);
565 OutStreamer.emitRawComment("workitem_vgpr_count = " +
566 Twine(header.workitem_vgpr_count), false);
567 OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
568 OutStreamer.emitRawComment("wavefront_size = " +
569 Twine((int)header.wavefront_size), false);
570 OutStreamer.emitRawComment("optimization_level = " +
571 Twine(header.optimization_level), false);
572 OutStreamer.emitRawComment("hsail_profile = " +
573 Twine(header.hsail_profile), false);
574 OutStreamer.emitRawComment("hsail_machine_model = " +
575 Twine(header.hsail_machine_model), false);
576 OutStreamer.emitRawComment("hsail_version_major = " +
577 Twine(header.hsail_version_major), false);
578 OutStreamer.emitRawComment("hsail_version_minor = " +
579 Twine(header.hsail_version_minor), false);
580 }
581
582 OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
583 }
584