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Searched defs:ElemsPerVReg (Results 1 – 1 of 1) sorted by relevance

/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4043 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); lowerBUILD_VECTOR() local
4988 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); lowerShuffleViaVRegSplitting() local
8481 unsigned ElemsPerVReg = *VLEN / ElemVT.getFixedSizeInBits(); lowerINSERT_VECTOR_ELT() local
8692 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); lowerEXTRACT_VECTOR_ELT() local
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