1 /* $NetBSD: if_epic_pci.c,v 1.43 2022/09/24 18:12:42 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * PCI bus front-end for the Standard Microsystems Corp. 83C170
35 * Ethernet PCI Integrated Controller (EPIC/100) driver.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: if_epic_pci.c,v 1.43 2022/09/24 18:12:42 thorpej Exp $");
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/mbuf.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
46 #include <sys/ioctl.h>
47 #include <sys/errno.h>
48 #include <sys/device.h>
49
50 #include <net/if.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_ether.h>
54
55 #include <sys/bus.h>
56 #include <sys/intr.h>
57
58 #include <dev/mii/miivar.h>
59
60 #include <dev/ic/smc83c170reg.h>
61 #include <dev/ic/smc83c170var.h>
62
63 #include <dev/pci/pcivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcidevs.h>
66
67 /*
68 * PCI configuration space registers used by the EPIC.
69 */
70 #define EPIC_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
71 #define EPIC_PCI_MMBA PCI_BAR(1) /* memory mapped base */
72
73 struct epic_pci_softc {
74 struct epic_softc sc_epic; /* real EPIC softc */
75
76 /* PCI-specific goo. */
77 void *sc_ih; /* interrupt handle */
78 };
79
80 static int epic_pci_match(device_t, cfdata_t, void *);
81 static void epic_pci_attach(device_t, device_t, void *);
82
83 CFATTACH_DECL_NEW(epic_pci, sizeof(struct epic_pci_softc),
84 epic_pci_match, epic_pci_attach, NULL, NULL);
85
86 static const struct epic_pci_product {
87 uint32_t epp_prodid; /* PCI product ID */
88 const char *epp_name; /* device name */
89 } epic_pci_products[] = {
90 { PCI_PRODUCT_SMC_83C170, "SMC 83c170 Fast Ethernet" },
91 { PCI_PRODUCT_SMC_83C175, "SMC 83c175 Fast Ethernet" },
92 { 0, NULL },
93 };
94
95 static const struct epic_pci_product *
epic_pci_lookup(const struct pci_attach_args * pa)96 epic_pci_lookup(const struct pci_attach_args *pa)
97 {
98 const struct epic_pci_product *epp;
99
100 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SMC)
101 return NULL;
102
103 for (epp = epic_pci_products; epp->epp_name != NULL; epp++)
104 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid)
105 return epp;
106
107 return NULL;
108 }
109
110 static const struct epic_pci_subsys_info {
111 pcireg_t subsysid;
112 int flags;
113 } epic_pci_subsys_info[] = {
114 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa015), /* SMC9432BTX */
115 EPIC_HAS_BNC },
116 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa024), /* SMC9432BTX1 */
117 EPIC_HAS_BNC },
118 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa016), /* SMC9432FTX */
119 EPIC_HAS_MII_FIBER | EPIC_DUPLEXLED_ON_694 },
120 { 0xffffffff,
121 0 }
122 };
123
124 static const struct epic_pci_subsys_info *
epic_pci_subsys_lookup(const struct pci_attach_args * pa)125 epic_pci_subsys_lookup(const struct pci_attach_args *pa)
126 {
127 pci_chipset_tag_t pc = pa->pa_pc;
128 pcireg_t reg;
129 const struct epic_pci_subsys_info *esp;
130
131 reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
132
133 for (esp = epic_pci_subsys_info; esp->subsysid != 0xffffffff; esp++)
134 if (esp->subsysid == reg)
135 return esp;
136
137 return NULL;
138 }
139
140 static int
epic_pci_match(device_t parent,cfdata_t cf,void * aux)141 epic_pci_match(device_t parent, cfdata_t cf, void *aux)
142 {
143 struct pci_attach_args *pa = aux;
144
145 if (epic_pci_lookup(pa) != NULL)
146 return 1;
147
148 return 0;
149 }
150
151 static void
epic_pci_attach(device_t parent,device_t self,void * aux)152 epic_pci_attach(device_t parent, device_t self, void *aux)
153 {
154 struct epic_pci_softc *psc = device_private(self);
155 struct epic_softc *sc = &psc->sc_epic;
156 struct pci_attach_args *pa = aux;
157 pci_chipset_tag_t pc = pa->pa_pc;
158 pci_intr_handle_t ih;
159 const char *intrstr = NULL;
160 const struct epic_pci_product *epp;
161 const struct epic_pci_subsys_info *esp;
162 bus_space_tag_t iot, memt;
163 bus_space_handle_t ioh, memh;
164 int ioh_valid, memh_valid;
165 int error;
166 char intrbuf[PCI_INTRSTR_LEN];
167
168 sc->sc_dev = self;
169
170 epp = epic_pci_lookup(pa);
171 if (epp == NULL) {
172 aprint_normal("\n");
173 panic("%s: impossible", __func__);
174 }
175
176 pci_aprint_devinfo_fancy(pa, "Ethernet controller", epp->epp_name, 1);
177
178 /* power up chip */
179 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
180 NULL)) && error != EOPNOTSUPP) {
181 aprint_error_dev(self, "cannot activate %d\n", error);
182 return;
183 }
184
185 /*
186 * Map the device.
187 */
188 ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA,
189 PCI_MAPREG_TYPE_IO, 0,
190 &iot, &ioh, NULL, NULL) == 0);
191 memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA,
192 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
193 &memt, &memh, NULL, NULL) == 0);
194
195 if (memh_valid) {
196 sc->sc_st = memt;
197 sc->sc_sh = memh;
198 } else if (ioh_valid) {
199 sc->sc_st = iot;
200 sc->sc_sh = ioh;
201 } else {
202 aprint_error_dev(self, "unable to map device registers\n");
203 return;
204 }
205
206 sc->sc_dmat = pa->pa_dmat;
207
208 /* Make sure bus mastering is enabled. */
209 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
210 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
211 PCI_COMMAND_MASTER_ENABLE);
212
213 /*
214 * Map and establish our interrupt.
215 */
216 if (pci_intr_map(pa, &ih)) {
217 aprint_error_dev(self, "unable to map interrupt\n");
218 return;
219 }
220 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
221 psc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, epic_intr, sc,
222 device_xname(self));
223 if (psc->sc_ih == NULL) {
224 aprint_error_dev(self, "unable to establish interrupt");
225 if (intrstr != NULL)
226 aprint_error(" at %s", intrstr);
227 aprint_error("\n");
228 return;
229 }
230 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
231
232 esp = epic_pci_subsys_lookup(pa);
233 if (esp)
234 sc->sc_hwflags = esp->flags;
235
236 /*
237 * Finish off the attach.
238 */
239 epic_attach(sc);
240 }
241