1 /* $NetBSD: enable.h,v 1.5 2024/06/19 15:24:37 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass and Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * System Enable Register contents 34 */ 35 #define ENA_PAR_GEN 0x01 /* enable parity generation */ 36 #define ENA_SOFT_INT_1 0x02 /* software interrupt on level 1 */ 37 #define ENA_SOFT_INT_2 0x04 /* software interrupt on level 2 */ 38 #define ENA_SOFT_INT_3 0x08 /* software interrupt on level 3 */ 39 #define ENA_PAR_CHECK 0x10 /* enable parity checking and errors */ 40 #define ENA_SDVMA 0x20 /* enable DVMA */ 41 #define ENA_INTS 0x40 /* enable interrupts */ 42 #define ENA_NOTBOOT 0x80 /* non-boot state */ 43 44 /* 45 * The Sun2 enable register is the ancestor of the Sun3 interrupt 46 * register. It can't be memory-mapped (and thus be manipulated with 47 * the single-instruction (read: atomic) bit instructions) since it's 48 * in control space. SunOS seems reluctant to raise SPL (maybe it 49 * doesn't help?) to manipulate it, so we won't either, but that means 50 * we have to also do as it does and have these bizarre functions. 51 */ 52 #ifdef _KERNEL 53 #define ENABLE_REG_SOFT_UNDEF (0) 54 extern volatile u_short enable_reg_soft; 55 u_short enable_reg_and(u_short); 56 u_short enable_reg_or(u_short); 57 #endif /* _KERNEL */ 58