1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef __T4_HW_H 7 #define __T4_HW_H 8 9 enum { 10 NCHAN = 4, /* # of HW channels */ 11 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 12 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 13 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 14 NMTUS = 16, /* size of MTU table */ 15 NCCTRL_WIN = 32, /* # of congestion control windows */ 16 MBOX_LEN = 64, /* mailbox size in bytes */ 17 UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */ 18 }; 19 20 enum { 21 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 22 }; 23 24 enum { 25 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 26 }; 27 28 enum { 29 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 30 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 31 SGE_FL_BUFFER_SIZE_NUM = 16, /* # of freelist buffser size regs */ 32 }; 33 34 /* PCI-e memory window access */ 35 enum pcie_memwin { 36 MEMWIN_NIC = 0, 37 }; 38 39 enum { 40 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 41 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */ 42 /* max no. of desc allowed in WR */ 43 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE, 44 }; 45 46 enum { 47 TCB_SIZE = 128, /* TCB size */ 48 }; 49 50 struct sge_qstat { /* data written to SGE queue status entries */ 51 __be32 qid; 52 __be16 cidx; 53 __be16 pidx; 54 }; 55 56 /* 57 * Structure for last 128 bits of response descriptors 58 */ 59 struct rsp_ctrl { 60 __be32 hdrbuflen_pidx; 61 __be32 pldbuflen_qid; 62 union { 63 u8 type_gen; 64 __be64 last_flit; 65 } u; 66 }; 67 68 #define S_RSPD_NEWBUF 31 69 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 70 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 71 72 #define S_RSPD_LEN 0 73 #define M_RSPD_LEN 0x7fffffff 74 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 75 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 76 77 #define S_RSPD_GEN 7 78 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 79 #define F_RSPD_GEN V_RSPD_GEN(1U) 80 81 #define S_RSPD_TYPE 4 82 #define M_RSPD_TYPE 0x3 83 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 84 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 85 86 /* Rx queue interrupt deferral field: timer index */ 87 #define S_QINTR_CNT_EN 0 88 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 89 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 90 91 #define S_QINTR_TIMER_IDX 1 92 #define M_QINTR_TIMER_IDX 0x7 93 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 94 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 95 96 /* 97 * Flash layout. 98 */ 99 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 100 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 101 102 enum { 103 /* 104 * Various Expansion-ROM boot images, etc. 105 */ 106 FLASH_EXP_ROM_START_SEC = 0, 107 FLASH_EXP_ROM_NSECS = 6, 108 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 109 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 110 111 /* 112 * Location of firmware image in FLASH. 113 */ 114 FLASH_FW_START_SEC = 8, 115 FLASH_FW_NSECS = 16, 116 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 117 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 118 119 /* 120 * Location of bootstrap firmware image in FLASH. 121 */ 122 FLASH_FWBOOTSTRAP_START_SEC = 27, 123 FLASH_FWBOOTSTRAP_NSECS = 1, 124 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 125 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 126 127 /* 128 * Location of Firmware Configuration File in FLASH. 129 */ 130 FLASH_CFG_START_SEC = 31, 131 FLASH_CFG_NSECS = 1, 132 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 133 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 134 135 /* 136 * We don't support FLASH devices which can't support the full 137 * standard set of sections which we need for normal operations. 138 */ 139 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 140 }; 141 142 #undef FLASH_START 143 #undef FLASH_MAX_SIZE 144 145 #endif /* __T4_HW_H */ 146