/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 195 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local 203 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() 210 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() 278 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local 625 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local 754 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local 891 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in analyzeVGPRToSGPRCopy() local
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H A D | AMDGPUInstructionSelector.cpp | 109 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local 500 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local 593 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local 654 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local 857 const TargetRegisterClass *DstRC = in selectG_INSERT() local 1411 const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank); in selectRelocConstant() local 2170 const TargetRegisterClass *DstRC = in selectG_TRUNC() local 2312 const TargetRegisterClass *DstRC = in selectG_SZA_EXT() local 2501 const TargetRegisterClass *DstRC = in selectG_CONSTANT() local 2824 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB); in selectG_PTRMASK() local [all …]
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H A D | SIInstrInfo.cpp | 2901 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); in insertSelect() local 4365 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction() local 5547 const TargetRegisterClass *DstRC, in legalizeGenericOperand() 5919 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands() local 5947 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in legalizeOperands() local
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 177 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local 240 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 285 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local 313 const TargetRegisterClass *DstRC = in selectCopy() local 722 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() 731 const TargetRegisterClass *DstRC, const unsigned SrcReg, in selectTurnIntoCOPY() 766 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt() local 895 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext() local 1209 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitExtractSubreg() local 1249 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitInsertSubreg() local
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 148 const TargetRegisterClass *DstRC, in isCrossCopy() 432 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local 481 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
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H A D | MachineCombiner.cpp | 178 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local 187 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local 195 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
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H A D | RegisterCoalescer.cpp | 493 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local 1372 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local 1914 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
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H A D | MachineVerifier.cpp | 1061 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst); in verifyPreISelGenericInstruction() local 1872 const TargetRegisterClass *DstRC = in visitMachineInstrBefore() local
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H A D | PeepholeOptimizer.cpp | 476 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
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H A D | PPCVSXSwapRemoval.cpp | 924 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 108 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local
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H A D | AArch64InstructionSelector.cpp | 952 const TargetRegisterClass *DstRC; in selectCopy() local 3127 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local 3440 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local 3982 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, in emitScalarToVector() 4047 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local 4118 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local 4713 const TargetRegisterClass *DstRC = in emitVectorConcat() local 5257 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in emitLaneInsert() local 5517 const TargetRegisterClass *DstRC = in tryOptBuildVecToSubregToReg() local 5550 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in selectBuildVector() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.cpp | 315 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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/openbsd-src/gnu/llvm/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 204 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local 480 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 355 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 382 const TargetRegisterClass *DstRC, in shouldCoalesce()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 130 const TargetRegisterClass *DstRC = in selectCopy() local
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 154 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local 615 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 971 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 880 const TargetRegisterClass *DstRC, in shouldCoalesce()
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H A D | ARMFastISel.cpp | 2041 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local 2061 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC() local
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 1075 const TargetRegisterClass *DstRC, in shouldCoalesce()
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