/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 154 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local 162 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() 169 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() 237 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local 589 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local 684 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
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H A D | AMDGPUInstructionSelector.cpp | 104 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local 477 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local 516 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local 577 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local 725 const TargetRegisterClass *DstRC = in selectG_INSERT() local 1133 const TargetRegisterClass *DstRC = in selectRelocConstant() local 1858 const TargetRegisterClass *DstRC in selectG_TRUNC() local 2000 const TargetRegisterClass *DstRC = in selectG_SZA_EXT() local 2166 const TargetRegisterClass *DstRC = in selectG_CONSTANT() local 2503 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB, in selectG_PTRMASK() local [all …]
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H A D | SIInstrInfo.cpp | 2545 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); in insertSelect() local 3952 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction() local 5084 const TargetRegisterClass *DstRC, in legalizeGenericOperand() 5452 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands() local 5480 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in legalizeOperands() local
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H A D | SIRegisterInfo.cpp | 2260 const TargetRegisterClass *DstRC, in shouldCoalesce()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local 226 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 250 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local 278 const TargetRegisterClass *DstRC = in selectCopy() local 684 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() 693 const TargetRegisterClass *DstRC, const unsigned SrcReg, in selectTurnIntoCOPY() 728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt() local 857 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext() local 1171 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitExtractSubreg() local 1211 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitInsertSubreg() local
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H A D | X86InstrInfo.cpp | 6381 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand() local 6464 const TargetRegisterClass *DstRC = nullptr; in unfoldMemoryOperand() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 151 const TargetRegisterClass *DstRC, in isCrossCopy() 435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local 484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
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H A D | RegisterCoalescer.cpp | 479 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local 1351 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local 1882 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
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H A D | PeepholeOptimizer.cpp | 477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
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H A D | MachineVerifier.cpp | 1714 const TargetRegisterClass *DstRC = in visitMachineInstrBefore() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
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H A D | PPCVSXSwapRemoval.cpp | 922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.cpp | 282 const TargetRegisterClass *DstRC, in shouldCoalesce()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 204 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local 485 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 865 const TargetRegisterClass *DstRC; in selectCopy() local 2829 const TargetRegisterClass *DstRC = in select() local 3151 const TargetRegisterClass *DstRC = in select() local 3630 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, in emitScalarToVector() 3695 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local 3762 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local 4349 const TargetRegisterClass *DstRC = in emitVectorConcat() local 4655 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in emitLaneInsert() local 4840 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in selectBuildVector() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 349 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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H A D | HexagonGenInsert.cpp | 686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 379 const TargetRegisterClass *DstRC, in shouldCoalesce()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 159 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local 614 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 783 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 857 const TargetRegisterClass *DstRC, in shouldCoalesce()
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H A D | ARMFastISel.cpp | 2037 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local 2057 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 1026 const TargetRegisterClass *DstRC, in shouldCoalesce()
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