Searched defs:DstR (Results 1 – 8 of 8) sorted by relevance
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | RDFCopy.cpp | 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); interpretAsCopy() local
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| H A D | HexagonRDFOpt.cpp | 118 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
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| H A D | HexagonTfrCleanup.cpp | 203 unsigned DstR = MI->getOperand(0).getReg(); rewriteIfImm() local
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| H A D | HexagonFrameLowering.cpp | 1724 Register DstR = MI->getOperand(0).getReg(); expandCopy() local
1782 Register DstR = MI->getOperand(0).getReg(); expandLoadInt() local
1849 Register DstR = MI->getOperand(0).getReg(); expandLoadVecPred() local
1947 Register DstR = MI->getOperand(0).getReg(); expandLoadVec2() local
2017 Register DstR = MI->getOperand(0).getReg(); expandLoadVec() local
2460 Register DstR = MI.getOperand(0).getReg(); optimizeSpillSlots() local
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| H A D | HexagonExpandCondsets.cpp | 646 genCondTfrFor(MachineOperand & SrcOp,MachineBasicBlock::iterator At,unsigned DstR,unsigned DstSR,const MachineOperand & PredOp,bool PredSense,bool ReadUndef,bool ImpUse) genCondTfrFor() argument
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| H A D | HexagonSplitDouble.cpp | 1000 Register DstR = MI->getOperand(0).getReg(); in splitInstr() local
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| H A D | HexagonGenInsert.cpp | 674 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 704 const Register DstR = Dst.getReg(); in processInstructionForSlowLEA() local
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