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Searched defs:DstLo (Results 1 – 9 of 9) sorted by relevance

/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); expandMI() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp717 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
H A DMipsSEFrameLowering.cpp268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); expandCopyACC() local
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1985 auto DstLo = MRI.createGenericVirtualRegister(s64); legalizeAtomicCmpxchg128() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1949 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); expandLoadVec2() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp2187 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); expandPostRAPseudo() local
2262 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); expandPostRAPseudo() local
H A DAMDGPURegisterBankInfo.cpp1585 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); applyMappingMAD_64_32() local
H A DAMDGPUInstructionSelector.cpp370 Register DstLo = MRI->createVirtualRegister(&HalfRC); selectG_ADD_SUB() local
H A DSIISelLowering.cpp5281 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); EmitInstrWithCustomInserter() local