/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 407 bool llvm::expandDivision(BinaryOperator *Div) { in expandDivision() 552 bool llvm::expandDivisionUpTo32Bits(BinaryOperator *Div) { in expandDivisionUpTo32Bits() 600 bool llvm::expandDivisionUpTo64Bits(BinaryOperator *Div) { in expandDivisionUpTo64Bits()
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MVETailPredication.cpp | 327 const SCEV *Div = SE->getUDivExpr( in IsSafeActiveMask() local
|
H A D | ARMISelLowering.cpp | 20733 SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor); LowerDivRem() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMatInt.cpp | 367 Div = 5; in generateInstSeq() local [all...] |
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
H A D | NVPTX.cpp | 141 const unsigned Div = std::min<unsigned>(MaxSize, Alignment); coerceToIntArrayWithLimit() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | DivRemPairs.cpp | 56 Instruction *Div; in matchExpandedRem() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVPrepareFunctions.cpp | 229 Value *Div = IRB.CreateUDiv(Mul, UMulFunc->getArg(0)); buildUMulWithOverflowFunc() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | LoopCacheAnalysis.cpp | 432 const SCEV *Div = SE.getUDivExactExpr(AccessFn, ElemSize); delinearize() local
|
H A D | BranchProbabilityInfo.cpp | 501 uint32_t Div = static_cast<uint32_t>( in calcMetadataWeights() local
|
H A D | ScalarEvolution.cpp | 1777 if (auto *Div = dyn_cast<SCEVUDivExpr>(Op)) getZeroExtendExprImpl() local 3515 const SCEV *Div = getUDivExpr(Op, RHSC); getUDivExpr() local 15211 if (auto *Div = dyn_cast<SCEVUDivExpr>(MulLHS)) applyLoopGuards() local
|
/freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCExpr.h | 489 Div, ///< Signed division. global() enumerator
|
/freebsd-src/contrib/llvm-project/llvm/lib/IR/ |
H A D | ConstantFold.cpp | 1686 Constant *Div = ConstantFoldGetElementPtr() local
|
H A D | AsmWriter.cpp | 1391 } else if (const PossiblyExactOperator *Div = WriteOptimizationInfo() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 1958 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); LowerDIVREM24() local 2139 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE); LowerUDIVREM64() local 2292 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); LowerSDIVREM() local 2316 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); LowerFREM() local [all...] |
H A D | AMDGPUCodeGenPrepare.cpp | 1294 Value *Div = Builder.CreateAdd(IQ, JQ); expandDivRem24Impl() local
|
H A D | AMDGPULegalizerInfo.cpp | 2389 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); legalizeFrem() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 1559 SDValue Div = DAG.getNode(DivOpc, DL, VT, Dividend, Divisor, Mask, EVL); ExpandVP_REM() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCWin64EH.cpp | 265 const MCSymbol *RHS, int Div) { in GetSubDivExpr()
|
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 308 HANDLEBINOP(Div) HANDLEBINOP() argument
|
/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 377 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0); visitMul() local [all...] |
H A D | InstCombineCompares.cpp | 2613 foldICmpDivConstant(ICmpInst & Cmp,BinaryOperator * Div,const APInt & C) foldICmpDivConstant() argument 4376 Instruction *Div; foldMultiplicationOverflowCheck() local [all...] |
/freebsd-src/contrib/llvm-project/clang/lib/AST/Interp/ |
H A D | Interp.h | 429 bool Div(InterpState &S, CodePtr OpPC) { Div() function
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 8108 ConvertOmodDiv(int64_t & Div) ConvertOmodDiv() argument
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 12595 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); emitProbedAlloca() local
|
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 25965 SDValue Div = DAG.getNode(Op.getOpcode(), dl, WideVT, Op0, Op1); LowerFixedLengthVectorIntDivideToSVE() local [all...] |