| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFormMemoryClauses.cpp | 152 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs, in canBundle()
219 RegUse &Defs, RegUse &Uses) const { in collectRegUses()
247 RegUse &Defs, RegUse &Uses, in processRegUses()
303 RegUse Defs, Uses; in runOnMachineFunction() local
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| H A D | SIPostRABundler.cpp | 49 SmallSet<Register, 16> Defs; member in __anon9dbd22ff0111::SIPostRABundler
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| H A D | SIFixSGPRCopies.cpp | 425 auto &Defs = Init.second; in hoistAndMergeSGPRInits() local
517 auto &Defs = Init.second; in hoistAndMergeSGPRInits() local
530 auto &Defs = Init.second; in hoistAndMergeSGPRInits() local
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| H A D | SIFoldOperands.cpp | 497 SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs, in getRegSeqInit()
576 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; in tryToFoldACImm() local
754 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; in foldOperand() local
1520 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; in tryFoldRegSequence() local
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| /netbsd-src/external/apache2/llvm/dist/clang/utils/TableGen/ |
| H A D | ClangDataCollectorsEmitter.cpp | 8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local
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| H A D | RISCVVEmitter.cpp | 901 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createHeader() local
988 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createBuiltins() local
1007 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createCodeGen() local
1173 std::vector<std::unique_ptr<RVVIntrinsic>> &Defs, raw_ostream &OS, in emitArchMacroAndBody()
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| H A D | SveEmitter.cpp | 1230 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createHeader() local
1291 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createBuiltins() local
1322 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createCodeGenMap() local
1355 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createRangeChecks() local
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| H A D | NeonEmitter.cpp | 1994 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef()
2021 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode()
2100 SmallVectorImpl<Intrinsic *> &Defs) { in genIntrinsicRangeCheckCode()
2190 SmallVector<Intrinsic *, 128> Defs; in runHeader() local
2365 SmallVector<Intrinsic *, 128> Defs; in run() local
2474 SmallVector<Intrinsic *, 128> Defs; in runFP16() local
2551 SmallVector<Intrinsic *, 128> Defs; in runBF16() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
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| H A D | A15SDOptimizer.cpp | 400 SmallVector<unsigned, 8> Defs; in getReadDPRs() local
593 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); in runOnInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 442 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef()
485 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs()
499 SmallVectorImpl<unsigned> &Defs) { in runOnInstr()
564 SmallVector<unsigned, 4> Defs; in runOnBlock() local
762 DenseSet<unsigned> Defs, Kills; in addNewBlock() local
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| H A D | RDFLiveness.cpp | 172 SmallSet<NodeId,32> Defs; in getAllReachingDefs() local
310 NodeSet &Visited, const NodeSet &Defs) { in getAllReachingDefsRec()
316 NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) { in getAllReachingDefsRecImpl()
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| H A D | ReachingDefAnalysis.cpp | 414 MCRegister PhysReg, InstSet &Defs, in getLiveOuts()
556 SmallSet<int, 2> Defs; in isSafeToMove() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCBoolRetToInt.cpp | 73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
222 auto Defs = findAllDefs(U); in runOnUse() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 100 BitVector Defs, Uses; member
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps() local
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| H A D | HexagonExpandCondsets.cpp | 393 MachineBasicBlock *Dest) -> bool { in updateDeadsInRange()
415 SetVector<MachineBasicBlock*> Defs; in updateDeadsInRange() local
795 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, in canMoveOver()
969 ReferenceMap Uses, Defs; in predicate() local
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| H A D | HexagonBitSimplify.cpp | 271 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
290 RegisterSet &Defs) { in getInstrDefs()
1471 RegisterSet Defs; in processBlock() local
1599 RegisterSet Defs; in processBlock() local
2713 RegisterSet Defs; in processBlock() local
2970 RegisterSet Defs; in getDefReg() local
3168 RegisterSet Defs; in processLoop() local
3235 RegisterSet Defs; in processLoop() local
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| H A D | HexagonRDFOpt.cpp | 256 NodeList Defs; in rewrite() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | MemorySSAUpdater.cpp | 155 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
182 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
263 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
273 if (auto *Defs = MSSA->getWritableBlockDefs(StartBlock)) { in insertUse() local
470 auto *Defs = MSSA->getWritableBlockDefs(NewDef->getBlock()); in fixupDefs() local
498 if (auto *Defs = MSSA->getWritableBlockDefs(FixupBlock)) { in fixupDefs() local
868 MemorySSA::DefsList *Defs = MSSA->getWritableBlockDefs(BB); in applyInsertUpdates() local
1241 auto *Defs = MSSA->getWritableBlockDefs(From); in moveAllAccesses() local
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| H A D | MemorySSA.cpp | 535 auto *Defs = MSSA.getBlockDefs(Node->getBlock()); in getWalkTarget() local
1529 DefsList *Defs = nullptr; in buildMemorySSA() local
1607 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1614 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1623 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1636 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsBefore() local
1837 std::unique_ptr<DefsList> &Defs = DefsIt->second; in removeFromLists() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CTagsEmitter.cpp | 66 const auto &Defs = Records.getDefs(); in run() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.h | 49 DenseMap<unsigned, PredSet> Defs; variable
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | ParallelSnippetGenerator.cpp | 189 BitVector Defs(State.getRegInfo().getNumRegs()); in generateCodeTemplates() local
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| H A D | MCInstrDescView.h | 208 SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1. member
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 167 Reg2SUnitsMap Defs; variable
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