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Searched defs:Defs (Results 1 – 25 of 61) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp150 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs, in canBundle() argument
217 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
245 RegUse &Defs, RegUse &Uses, in processRegUses() argument
301 RegUse Defs, Uses; runOnMachineFunction() local
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H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anon30cbefe60111::SIPostRABundler
H A DSIFixSGPRCopies.cpp469 auto &Defs = Init.second; hoistAndMergeSGPRInits() local
561 auto &Defs = Init.second; hoistAndMergeSGPRInits() local
574 auto &Defs = Init.second; hoistAndMergeSGPRInits() local
H A DSIFoldOperands.cpp656 getRegSeqInit(SmallVectorImpl<std::pair<MachineOperand *,unsigned>> & Defs,Register UseReg,uint8_t OpTy) const getRegSeqInit() argument
726 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; tryToFoldACImm() local
891 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; foldOperand() local
1740 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; tryFoldRegSequence() local
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/freebsd-src/contrib/llvm-project/clang/utils/TableGen/
H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local
H A DSveEmitter.cpp1219 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createCoreHeaderIntrinsics() local
1426 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createBuiltins() local
1466 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createCodeGenMap() local
1499 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createRangeChecks() local
1623 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMEBuiltins() local
1649 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMECodeGenMap() local
1683 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMERangeChecks() local
1719 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createBuiltinZAState() local
1759 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createStreamingAttrs() local
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H A DNeonEmitter.cpp2013 for (auto *Def : Defs) { in genBuiltinsDef() argument
2047 genStreamingSVECompatibleList(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genStreamingSVECompatibleList() argument
2073 genOverloadTypeCheckCode(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genOverloadTypeCheckCode() argument
2153 genIntrinsicRangeCheckCode(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genIntrinsicRangeCheckCode() argument
2243 SmallVector<Intrinsic *, 128> Defs; runHeader() local
2406 SmallVector<Intrinsic *, 128> Defs; run() local
2515 SmallVector<Intrinsic *, 128> Defs; runFP16() local
2624 SmallVector<Intrinsic *, 128> Defs; runBF16() local
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H A DRISCVVEmitter.cpp419 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createBuiltins() local
450 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createCodeGen() local
747 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createSema() local
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp432 HandlePhysRegDef(Register Reg,MachineInstr * MI,SmallVectorImpl<unsigned> & Defs) HandlePhysRegDef() argument
471 UpdatePhysRegDefs(MachineInstr & MI,SmallVectorImpl<unsigned> & Defs) UpdatePhysRegDefs() argument
482 runOnInstr(MachineInstr & MI,SmallVectorImpl<unsigned> & Defs,unsigned NumRegs) runOnInstr() argument
546 SmallVector<unsigned, 4> Defs; runOnBlock() local
826 DenseSet<unsigned> Defs, Kills; addNewBlock() local
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H A DRDFLiveness.cpp168 SmallSet<NodeId, 32> Defs; in getAllReachingDefs() local
305 NodeSet &Visited, const NodeSet &Defs) { in getAllReachingDefsRec()
311 NodeSet &Visited, const NodeSet &Defs, in getAllReachingDefsRecImpl()
H A DReachingDefAnalysis.cpp418 MCRegister PhysReg, InstSet &Defs, in getLiveOuts() argument
560 SmallSet<int, 2> Defs; in isSafeToMove() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp137 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
195 RegisterSet Defs, Uses; in InsertITInstructions() local
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H A DA15SDOptimizer.cpp398 SmallVector<unsigned, 8> Defs; in getReadDPRs() local
591 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); in runOnInstruction() local
/freebsd-src/contrib/llvm-project/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp148 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
175 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
257 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
267 if (auto *Defs = MSSA->getWritableBlockDefs(StartBlock)) { insertUse() local
470 auto *Defs = MSSA->getWritableBlockDefs(NewDef->getBlock()); fixupDefs() local
497 if (auto *Defs = MSSA->getWritableBlockDefs(FixupBlock)) { fixupDefs() local
847 MemorySSA::DefsList *Defs = MSSA->getWritableBlockDefs(BB); applyInsertUpdates() local
1216 auto *Defs = MSSA->getWritableBlockDefs(From); moveAllAccesses() local
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H A DMemorySSA.cpp531 auto *Defs = MSSA.getBlockDefs(Node->getBlock()); getWalkTarget() local
1514 DefsList *Defs = nullptr; buildMemorySSA() local
1584 auto *Defs = getOrCreateDefsList(BB); insertIntoListsForBlock() local
1591 auto *Defs = getOrCreateDefsList(BB); insertIntoListsForBlock() local
1600 auto *Defs = getOrCreateDefsList(BB); insertIntoListsForBlock() local
1613 auto *Defs = getOrCreateDefsList(BB); insertIntoListsBefore() local
1827 std::unique_ptr<DefsList> &Defs = DefsIt->second; removeFromLists() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp74 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
221 auto Defs = findAllDefs(U); in runOnUse() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
182 BitVector Defs(NR), Uses(NR); in buildMaps() local
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H A DHexagonExpandCondsets.cpp417 SetVector<MachineBasicBlock*> Defs; in updateDeadsInRange() local
395 __anon95dbea3e0702(SetVector<MachineBasicBlock*> &Defs, MachineBasicBlock *Dest) updateDeadsInRange() argument
817 canMoveOver(MachineInstr & MI,ReferenceMap & Defs,ReferenceMap & Uses) canMoveOver() argument
990 ReferenceMap Uses, Defs; predicate() local
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H A DHexagonBitSimplify.cpp299 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
318 RegisterSet &Defs) { in getInstrDefs() argument
1498 RegisterSet Defs; in processBlock() local
1626 RegisterSet Defs; processBlock() local
2738 RegisterSet Defs; processBlock() local
2995 RegisterSet Defs; getDefReg() local
3191 RegisterSet Defs; processLoop() local
3257 RegisterSet Defs; processLoop() local
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H A DHexagonRDFOpt.cpp258 NodeList Defs; rewrite() local
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DCTagsEmitter.cpp70 const auto &Defs = Records.getDefs(); run() local
H A DCodeGenIntrinsics.cpp
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.h48 DenseMap<unsigned, PredSet> Defs; variable
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon164cd6680111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon164cd6680111::MemDefsUses
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h169 RegUnit2SUnitsMap Defs; global() variable

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