| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveIntervalCalc.cpp | 45 SlotIndex DefIdx = in createDeadDef() local
190 unsigned DefIdx; in extendToUses() local
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| H A D | TargetSchedule.cpp | 158 unsigned DefIdx = 0; in findDefIdx() local
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
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| H A D | TargetInstrInfo.cpp | 1090 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1259 unsigned DefIdx, in getOperandLatency()
1284 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1311 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1336 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| H A D | LiveRangeEdit.cpp | 149 SlotIndex DefIdx; in canRematerializeAt() local
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| H A D | RenameIndependentSubregs.cpp | 335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
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| H A D | MachineCombiner.cpp | 200 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth() local
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| H A D | MachineInstr.cpp | 289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
895 unsigned DefIdx; in getRegClassConstraint() local
1099 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands()
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| H A D | MachineVerifier.cpp | 1882 unsigned DefIdx; in visitMachineOperand() local
2114 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef()
2286 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
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| H A D | TargetRegisterInfo.cpp | 391 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.h | 141 unsigned DefIdx; variable
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| H A D | ScheduleDAGSDNodes.cpp | 477 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
655 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| H A D | MCSubtargetInfo.h | 176 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 621 int DefIdx = SwapMap[DefMI]; in formWebs() local
725 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
801 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| H A D | PPCInstrInfo.h | 320 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
328 unsigned DefIdx) const override { in hasLowDefLatency()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
573 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 525 unsigned DefIdx = 0; in getDefIndex() local
629 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
682 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeValues() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 204 unsigned DefIdx = 0; in tryInlineAsm() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 3844 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3885 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3988 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
4099 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
4332 unsigned DefIdx, in getOperandLatency()
4368 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
4428 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4776 unsigned DefIdx, in hasHighOperandLatency()
5337 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
5364 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1223 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
1237 unsigned DefIdx, in getExtractSubregLikeInputs()
1251 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1627 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 435 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 495 int DefIdx = -1; in restoreLatency() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 650 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot(); in moveAndTeeForMultiUse() local
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