1 /* $NetBSD: pciide_sii3112_reg.h,v 1.3 2005/12/11 12:22:50 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_PCI_PCIIDE_SII3112_REG_H_ 39 #define _DEV_PCI_PCIIDE_SII3112_REG_H_ 40 41 /* 42 * PCI configuration space registers. 43 */ 44 45 #define SII3112_PCI_CFGCTL 0x40 46 #define CFGCTL_CFGWREN (1U << 0) /* enable cfg writes */ 47 #define CFGCTL_BA5INDEN (1U << 1) /* BA5 indirect access enable */ 48 49 #define SII3112_PCI_SWDATA 0x44 50 51 #define SII3112_PCI_BM_IDE0 0x70 52 /* == BAR4+0x00 */ 53 54 #define SII3112_PCI_PRD_IDE0 0x74 55 /* == BAR4+0x04 */ 56 57 #define SII3112_PCI_BM_IDE1 0x78 58 /* == BAR4+0x08 */ 59 60 #define SII3112_PCI_PRD_IDE1 0x7c 61 /* == BAR4+0x0c */ 62 63 #define SII3112_DTM_IDE0 0x80 /* Data Transfer Mode - IDE0 */ 64 #define SII3112_DTM_IDE1 0x84 /* Data Transfer Mode - IDE1 */ 65 #define DTM_IDEx_PIO 0x00000000 /* PCI DMA, IDE PIO (or 1) */ 66 #define DTM_IDEx_DMA 0x00000002 /* PCI DMA, IDE DMA (or 3) */ 67 68 69 #define SII3112_SCS_CMD 0x88 /* System Config Status */ 70 #define SCS_CMD_PBM_RESET (1U << 0) /* PBM module reset */ 71 #define SCS_CMD_ARB_RESET (1U << 1) /* ARB module reset */ 72 #define SCS_CMD_FF1_RESET (1U << 4) /* IDE1 FIFO reset */ 73 #define SCS_CMD_FF0_RESET (1U << 5) /* IDE0 FIFO reset */ 74 #define SCS_CMD_IDE1_RESET (1U << 6) /* IDE1 module reset */ 75 #define SCS_CMD_IDE0_RESET (1U << 7) /* IDE0 module reset */ 76 #define SCS_CMD_FF3_RESET (1U << 8) /* IDE3 FIFO reset (3114) */ 77 #define SCS_CMD_FF2_RESET (1U << 9) /* IDE2 FIFO reset (3114) */ 78 #define SCS_CMD_IDE3_RESET (1U << 10) /* IDE3 module reset (3114) */ 79 #define SCS_CMD_IDE2_RESET (1U << 11) /* IDE2 module reset (3114) */ 80 #define SCS_CMD_BA5_EN (1U << 16) /* BA5 is enabled (3112) */ 81 #define SCS_CMD_M66EN (1U << 16) /* 1=66MHz, 0=33MHz (3114) */ 82 #define SCS_CMD_IDE0_INT_BLOCK (1U << 22) /* IDE0 interrupt block */ 83 #define SCS_CMD_IDE1_INT_BLOCK (1U << 23) /* IDE1 interrupt block */ 84 #define SCS_CMD_IDE2_INT_BLOCK (1U << 24) /* IDE2 interrupt block */ 85 #define SCS_CMD_IDE3_INT_BLOCK (1U << 25) /* IDE3 interrupt block */ 86 87 #define SII3112_SSDR 0x8c /* System SW Data Register */ 88 89 #define SII3112_FMA_CSR 0x90 /* Flash Memory Addr - CSR */ 90 91 #define SII3112_FM_DATA 0x94 /* Flash Memory Data */ 92 93 #define SII3112_EEA_CSR 0x98 /* EEPROM Memory Addr - CSR */ 94 95 #define SII3112_EE_DATA 0x9c /* EEPROM Data */ 96 97 #define SII3112_TCS_IDE0 0xa0 /* IDEx config, status */ 98 #define SII3112_TCS_IDE1 0xb0 99 #define TCS_IDEx_BCA (1U << 1) /* buffered command active */ 100 #define TCS_IDEx_CH_RESET (1U << 2) /* channel reset */ 101 #define TCS_IDEx_VDMA_INT (1U << 10) /* virtual DMA interrupt */ 102 #define TCS_IDEx_INT (1U << 11) /* interrupt status */ 103 #define TCS_IDEx_WTT (1U << 12) /* watchdog timer timeout */ 104 #define TCS_IDEx_WTEN (1U << 13) /* watchdog timer enable */ 105 #define TCS_IDEx_WTINTEN (1U << 14) /* watchdog timer int. enable */ 106 107 #define SII3112_BA5_IND_ADDR 0xc0 /* BA5 indirect address */ 108 109 #define SII3112_BA5_IND_DATA 0xc4 /* BA5 indirect data */ 110 111 #endif /* _DEV_PCI_PCIIDE_SII3112_REG_H_ */ 112