1 /* $NetBSD: vegam_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef _VEGAM_SMUMANAGER_H 27 #define _VEGAM_SMUMANAGER_H 28 29 30 #include <pp_endian.h> 31 #include "smu75_discrete.h" 32 #include "smu7_smumgr.h" 33 34 #define SMC_RAM_END 0x40000 35 36 #define DPMTuning_Uphyst_Shift 0 37 #define DPMTuning_Downhyst_Shift 8 38 #define DPMTuning_Activity_Shift 16 39 40 #define GraphicsDPMTuning_VEGAM 0x001e6400 41 #define MemoryDPMTuning_VEGAM 0x000f3c0a 42 #define SclkDPMTuning_VEGAM 0x002d000a 43 #define MclkDPMTuning_VEGAM 0x001f100a 44 45 46 struct vegam_pt_defaults { 47 uint8_t SviLoadLineEn; 48 uint8_t SviLoadLineVddC; 49 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 50 uint8_t TDC_MAWt; 51 uint8_t TdcWaterfallCtl; 52 uint8_t DTEAmbientTempBase; 53 54 uint32_t DisplayCac; 55 uint32_t BAPM_TEMP_GRADIENT; 56 uint16_t BAPMTI_R[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; 57 uint16_t BAPMTI_RC[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; 58 }; 59 60 struct vegam_range_table { 61 uint32_t trans_lower_frequency; /* in 10khz */ 62 uint32_t trans_upper_frequency; 63 }; 64 65 struct vegam_smumgr { 66 struct smu7_smumgr smu7_data; 67 uint8_t protected_mode; 68 SMU75_Discrete_DpmTable smc_state_table; 69 struct SMU75_Discrete_Ulv ulv_setting; 70 struct SMU75_Discrete_PmFuses power_tune_table; 71 struct vegam_range_table range_table[NUM_SCLK_RANGE]; 72 const struct vegam_pt_defaults *power_tune_defaults; 73 uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK]; 74 }; 75 76 77 #endif 78