1 /* $NetBSD: dp.h,v 1.2 2021/12/18 23:45:35 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 #ifndef __NVKM_DISP_DP_H__ 5 #define __NVKM_DISP_DP_H__ 6 #define nvkm_dp(p) container_of((p), struct nvkm_dp, outp) 7 #include "outp.h" 8 9 #include <core/notify.h> 10 #include <subdev/bios.h> 11 #include <subdev/bios/dp.h> 12 13 struct nvkm_dp { 14 union { 15 struct nvkm_outp base; 16 struct nvkm_outp outp; 17 }; 18 19 struct nvbios_dpout info; 20 u8 version; 21 22 struct nvkm_i2c_aux *aux; 23 24 struct nvkm_notify hpd; 25 bool present; 26 u8 dpcd[16]; 27 28 struct mutex mutex; 29 struct { 30 atomic_t done; 31 bool mst; 32 } lt; 33 }; 34 35 int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, 36 struct nvkm_outp **); 37 38 /* DPCD Receiver Capabilities */ 39 #define DPCD_RC00_DPCD_REV 0x00000 40 #define DPCD_RC01_MAX_LINK_RATE 0x00001 41 #define DPCD_RC02 0x00002 42 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 43 #define DPCD_RC02_TPS3_SUPPORTED 0x40 44 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 45 #define DPCD_RC03 0x00003 46 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 47 #define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e 48 49 /* DPCD Link Configuration */ 50 #define DPCD_LC00_LINK_BW_SET 0x00100 51 #define DPCD_LC01 0x00101 52 #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 53 #define DPCD_LC01_LANE_COUNT_SET 0x1f 54 #define DPCD_LC02 0x00102 55 #define DPCD_LC02_TRAINING_PATTERN_SET 0x03 56 #define DPCD_LC03(l) ((l) + 0x00103) 57 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 58 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 59 #define DPCD_LC03_MAX_SWING_REACHED 0x04 60 #define DPCD_LC03_VOLTAGE_SWING_SET 0x03 61 #define DPCD_LC0F 0x0010f 62 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 63 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 64 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 65 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 66 #define DPCD_LC10 0x00110 67 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 68 #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 69 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 70 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 71 72 /* DPCD Link/Sink Status */ 73 #define DPCD_LS02 0x00202 74 #define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 75 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 76 #define DPCD_LS02_LANE1_CR_DONE 0x10 77 #define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 78 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 79 #define DPCD_LS02_LANE0_CR_DONE 0x01 80 #define DPCD_LS03 0x00203 81 #define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 82 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 83 #define DPCD_LS03_LANE3_CR_DONE 0x10 84 #define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 85 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 86 #define DPCD_LS03_LANE2_CR_DONE 0x01 87 #define DPCD_LS04 0x00204 88 #define DPCD_LS04_LINK_STATUS_UPDATED 0x80 89 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 90 #define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 91 #define DPCD_LS06 0x00206 92 #define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 93 #define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 94 #define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 95 #define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 96 #define DPCD_LS07 0x00207 97 #define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 98 #define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 99 #define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 100 #define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 101 #define DPCD_LS0C 0x0020c 102 #define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 103 #define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 104 #define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 105 #define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 106 107 /* DPCD Sink Control */ 108 #define DPCD_SC00 0x00600 109 #define DPCD_SC00_SET_POWER 0x03 110 #define DPCD_SC00_SET_POWER_D0 0x01 111 #define DPCD_SC00_SET_POWER_D3 0x03 112 #endif 113