xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/dcn10_hubbub.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: dcn10_hubbub.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2016 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #ifndef __DC_HUBBUB_DCN10_H__
29 #define __DC_HUBBUB_DCN10_H__
30 
31 #include "core_types.h"
32 #include "dchubbub.h"
33 
34 #define TO_DCN10_HUBBUB(hubbub)\
35 	container_of(hubbub, struct dcn10_hubbub, base)
36 
37 #define HUBBUB_REG_LIST_DCN_COMMON()\
38 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
39 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
40 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
41 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
42 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
43 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
44 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
45 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
46 	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
47 	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
48 	SR(DCHUBBUB_ARB_SAT_LEVEL),\
49 	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
50 	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
51 	SR(DCHUBBUB_TEST_DEBUG_INDEX), \
52 	SR(DCHUBBUB_TEST_DEBUG_DATA),\
53 	SR(DCHUBBUB_SOFT_RESET)
54 
55 #define HUBBUB_VM_REG_LIST() \
56 	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
57 	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
58 	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
59 	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)
60 
61 #define HUBBUB_SR_WATERMARK_REG_LIST()\
62 	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
63 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
64 	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
65 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
66 	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
67 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
68 	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
69 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
70 
71 #define HUBBUB_REG_LIST_DCN10(id)\
72 	HUBBUB_REG_LIST_DCN_COMMON(), \
73 	HUBBUB_VM_REG_LIST(), \
74 	HUBBUB_SR_WATERMARK_REG_LIST(), \
75 	SR(DCHUBBUB_SDPIF_FB_TOP),\
76 	SR(DCHUBBUB_SDPIF_FB_BASE),\
77 	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
78 	SR(DCHUBBUB_SDPIF_AGP_BASE),\
79 	SR(DCHUBBUB_SDPIF_AGP_BOT),\
80 	SR(DCHUBBUB_SDPIF_AGP_TOP)
81 
82 struct dcn_hubbub_registers {
83 	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
84 	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
85 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
86 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
87 	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
88 	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
89 	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
90 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
91 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
92 	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
93 	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
94 	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
95 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
96 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
97 	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
98 	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
99 	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
100 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
101 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
102 	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
103 	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
104 	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
105 	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
106 	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
107 	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
108 	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
109 	uint32_t DCHUBBUB_TEST_DEBUG_DATA;
110 	uint32_t DCHUBBUB_SDPIF_FB_TOP;
111 	uint32_t DCHUBBUB_SDPIF_FB_BASE;
112 	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
113 	uint32_t DCHUBBUB_SDPIF_AGP_BASE;
114 	uint32_t DCHUBBUB_SDPIF_AGP_BOT;
115 	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
116 	uint32_t DCHUBBUB_CRC_CTRL;
117 	uint32_t DCHUBBUB_SOFT_RESET;
118 	uint32_t DCN_VM_FB_LOCATION_BASE;
119 	uint32_t DCN_VM_FB_LOCATION_TOP;
120 	uint32_t DCN_VM_FB_OFFSET;
121 	uint32_t DCN_VM_AGP_BOT;
122 	uint32_t DCN_VM_AGP_TOP;
123 	uint32_t DCN_VM_AGP_BASE;
124 	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
125 	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
126 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
127 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
128 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
129 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
130 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
131 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
132 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
133 	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
134 	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
135 	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
136 	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
137 	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
138 	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
139 	uint32_t DCHVM_CTRL0;
140 	uint32_t DCHVM_MEM_CTRL;
141 	uint32_t DCHVM_CLK_CTRL;
142 	uint32_t DCHVM_RIOMMU_CTRL0;
143 	uint32_t DCHVM_RIOMMU_STAT0;
144 };
145 
146 /* set field name */
147 #define HUBBUB_SF(reg_name, field_name, post_fix)\
148 	.field_name = reg_name ## __ ## field_name ## post_fix
149 
150 #define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\
151 		HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
152 		HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
153 		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
154 		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
155 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
156 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
157 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
158 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
159 		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
160 		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
161 		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
162 		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
163 		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
164 		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
165 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
166 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
167 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
168 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh)
169 
170 #define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \
171 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
172 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
173 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
174 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
175 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
176 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
177 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
178 		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh)
179 
180 #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
181 		HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
182 		HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
183 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
184 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
185 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
186 		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
187 		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
188 		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)
189 
190 #define DCN_HUBBUB_REG_FIELD_LIST(type) \
191 		type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
192 		type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
193 		type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
194 		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
195 		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
196 		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
197 		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
198 		type DCHUBBUB_ARB_SAT_LEVEL;\
199 		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
200 		type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
201 		type DCHUBBUB_GLOBAL_SOFT_RESET; \
202 		type SDPIF_FB_TOP;\
203 		type SDPIF_FB_BASE;\
204 		type SDPIF_FB_OFFSET;\
205 		type SDPIF_AGP_BASE;\
206 		type SDPIF_AGP_BOT;\
207 		type SDPIF_AGP_TOP;\
208 		type FB_BASE;\
209 		type FB_TOP;\
210 		type FB_OFFSET;\
211 		type AGP_BOT;\
212 		type AGP_TOP;\
213 		type AGP_BASE;\
214 		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
215 		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\
216 		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\
217 		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\
218 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
219 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
220 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
221 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
222 		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
223 		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
224 
225 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
226 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
227 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\
228 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\
229 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\
230 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\
231 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\
232 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
233 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
234 
235 #define HUBBUB_HVM_REG_FIELD_LIST(type) \
236 		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
237 		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
238 		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
239 		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
240 		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
241 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
242 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
243 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
244 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
245 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
246 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
247 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
248 		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
249 		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
250 		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
251 		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
252 		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
253 		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
254 		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
255 		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
256 		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
257 		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
258 		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
259 		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
260 		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
261 		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
262 		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
263 		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
264 		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
265 		type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
266 		type HOSTVM_INIT_REQ; \
267 		type HVM_GPUVMRET_PWR_REQ_DIS; \
268 		type HVM_GPUVMRET_FORCE_REQ; \
269 		type HVM_GPUVMRET_POWER_STATUS; \
270 		type HVM_DISPCLK_R_GATE_DIS; \
271 		type HVM_DISPCLK_G_GATE_DIS; \
272 		type HVM_DCFCLK_R_GATE_DIS; \
273 		type HVM_DCFCLK_G_GATE_DIS; \
274 		type TR_REQ_REQCLKREQ_MODE; \
275 		type TW_RSP_COMPCLKREQ_MODE; \
276 		type HOSTVM_PREFETCH_REQ; \
277 		type HOSTVM_POWERSTATUS; \
278 		type RIOMMU_ACTIVE; \
279 		type HOSTVM_PREFETCH_DONE
280 
281 struct dcn_hubbub_shift {
282 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
283 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
284 	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
285 };
286 
287 struct dcn_hubbub_mask {
288 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
289 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
290 	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
291 };
292 
293 struct dc;
294 
295 struct dcn10_hubbub {
296 	struct hubbub base;
297 	const struct dcn_hubbub_registers *regs;
298 	const struct dcn_hubbub_shift *shifts;
299 	const struct dcn_hubbub_mask *masks;
300 	unsigned int debug_test_index_pstate;
301 	struct dcn_watermark_set watermarks;
302 };
303 
304 void hubbub1_update_dchub(
305 	struct hubbub *hubbub,
306 	struct dchub_init_data *dh_data);
307 
308 bool hubbub1_verify_allow_pstate_change_high(
309 	struct hubbub *hubbub);
310 
311 void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
312 
313 void hubbub1_program_watermarks(
314 		struct hubbub *hubbub,
315 		struct dcn_watermark_set *watermarks,
316 		unsigned int refclk_mhz,
317 		bool safe_to_lower);
318 
319 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
320 
321 bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
322 
323 void hubbub1_toggle_watermark_change_req(
324 		struct hubbub *hubbub);
325 
326 void hubbub1_wm_read_state(struct hubbub *hubbub,
327 		struct dcn_hubbub_wm *wm);
328 
329 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
330 void hubbub1_construct(struct hubbub *hubbub,
331 	struct dc_context *ctx,
332 	const struct dcn_hubbub_registers *hubbub_regs,
333 	const struct dcn_hubbub_shift *hubbub_shift,
334 	const struct dcn_hubbub_mask *hubbub_mask);
335 
336 void hubbub1_program_urgent_watermarks(
337 		struct hubbub *hubbub,
338 		struct dcn_watermark_set *watermarks,
339 		unsigned int refclk_mhz,
340 		bool safe_to_lower);
341 void hubbub1_program_stutter_watermarks(
342 		struct hubbub *hubbub,
343 		struct dcn_watermark_set *watermarks,
344 		unsigned int refclk_mhz,
345 		bool safe_to_lower);
346 void hubbub1_program_pstate_watermarks(
347 		struct hubbub *hubbub,
348 		struct dcn_watermark_set *watermarks,
349 		unsigned int refclk_mhz,
350 		bool safe_to_lower);
351 
352 #endif
353