1 /* 2 * Program Status Registers 3 */ 4 #define PsrMusr 0x00000010 /* mode */ 5 #define PsrMfiq 0x00000011 6 #define PsrMirq 0x00000012 7 #define PsrMsvc 0x00000013 8 #define PsrMabt 0x00000017 9 #define PsrMund 0x0000001B 10 #define PsrMsys 0x0000001F 11 #define PsrMask 0x0000001F 12 13 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 14 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 15 16 #define PsrV 0x10000000 /* overflow */ 17 #define PsrC 0x20000000 /* carry/borrow/extend */ 18 #define PsrZ 0x40000000 /* zero */ 19 #define PsrN 0x80000000 /* negative/less than */ 20 21 /* 22 * Coprocessors 23 */ 24 #define CpFP 10 /* float FP, VFP cfg. */ 25 #define CpDFP 11 /* double FP */ 26 #define CpSC 15 /* System Control */ 27 28 /* 29 * opcode 1 30 */ 31 #define CpDef 0 /* default */ 32 #define CpL2 1 /* L2 cache operations */ 33 34 /* 35 * Primary (CRn) CpSC registers. 36 */ 37 #define CpID 0 /* ID and cache type */ 38 #define CpCONTROL 1 /* miscellaneous control */ 39 #define CpTTB 2 /* Translation Table Base */ 40 #define CpDAC 3 /* Domain Access Control */ 41 #define CpFSR 5 /* Fault Status */ 42 #define CpFAR 6 /* Fault Address */ 43 #define CpCACHE 7 /* cache/write buffer control */ 44 #define CpTLB 8 /* TLB control */ 45 #define CpCLD 9 /* Cache Lockdown */ 46 #define CpTLD 10 /* TLB Lockdown */ 47 #define CpPID 13 /* Process ID */ 48 #define CpTESTCFG 15 /* test config. (arm926) */ 49 50 /* 51 * CpID Secondary (CRm) registers. 52 */ 53 #define CpIDidct 0 54 /* 55 * CpID op1==0 opcode2 fields. 56 */ 57 #define CpIDid 0 /* main ID */ 58 #define CpIDct 1 /* cache type */ 59 60 /* 61 * CpCONTROL 62 */ 63 #define CpCmmu 0x00000001 /* M: MMU enable */ 64 #define CpCalign 0x00000002 /* A: alignment fault enable */ 65 #define CpCdcache 0x00000004 /* C: data cache on */ 66 #define CpCwb 0x00000008 /* W: write buffer turned on */ 67 #define CpCi32 0x00000010 /* P: 32-bit program space */ 68 #define CpCd32 0x00000020 /* D: 32-bit data space */ 69 #define CpCbe 0x00000080 /* B: big-endian operation */ 70 #define CpCsystem 0x00000100 /* S: system permission */ 71 #define CpCrom 0x00000200 /* R: ROM permission */ 72 #define CpCicache 0x00001000 /* I: instruction cache on */ 73 #define CpChv 0x00002000 /* V: high vectors */ 74 75 /* 76 * CpCACHE Secondary (CRm) registers and opcode2 fields. 77 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback. 78 * In arm arch v6, these must be available in user mode: 79 * CpCACHEinvi, CpCACHEwait (prefetch flush) 80 * CpCACHEwb, CpCACHEwait (DSB: data sync barrier) 81 * CpCACHEwb, CpCACHEdmbarr (DMB: data memory barrier) 82 */ 83 #define CpCACHEintr 0 /* interrupt */ 84 #define CpCACHEinvi 5 /* instruction */ 85 #define CpCACHEinvd 6 /* data */ 86 #define CpCACHEinvu 7 /* unified (I+D) */ 87 #define CpCACHEwb 10 /* writeback D */ 88 #define CpCACHEwbu 11 /* writeback U (not 926ejs) */ 89 #define CpCACHEwbi 14 /* writeback D + invalidate */ 90 #define CpCACHEwbui 15 /* writeback U + inval (not 926ejs) */ 91 92 /* 93 * the 926ejs manual says that we can't use CpCACHEall nor CpCACHEwait 94 * for writeback operations on the 926ejs, except for CpCACHEwb + CpCACHEwait, 95 * which means `drain write buffer'. 96 */ 97 #define CpCACHEall 0 /* entire */ 98 #define CpCACHEse 1 /* single entry */ 99 #define CpCACHEsi 2 /* set/index */ 100 #define CpCACHEtest 3 /* test loop */ 101 #define CpCACHEwait 4 /* wait */ 102 #define CpCACHEdmbarr 5 /* wb: data memory barrier */ 103 104 /* 105 * CpTLB Secondary (CRm) registers and opcode2 fields. 106 */ 107 #define CpTLBinvi 5 /* instruction */ 108 #define CpTLBinvd 6 /* data */ 109 #define CpTLBinvu 7 /* unified */ 110 111 #define CpTLBinv 0 /* invalidate all */ 112 #define CpTLBinvse 1 /* invalidate single entry */ 113 114 /* 115 * CpTESTCFG Secondary (CRm) registers and opcode2 fields; sheeva only. 116 * opcode1 == CpL2 (1). L2 cache operations block the CPU until finished. 117 * Specifically, write-back (clean) blocks until all dirty lines have been 118 * drained from the L2 buffers. 119 */ 120 #define CpTCl2cfg 1 121 #define CpTCl2flush 9 /* cpu blocks until flush done */ 122 #define CpTCl2waylck 10 123 #define CpTCl2inv 11 124 #define CpTCl2perfctl 12 125 #define CpTCl2perfcnt 13 126 127 /* CpTCl2cfg */ 128 #define CpTCl2conf 0 129 130 /* CpTCl2conf bits */ 131 #define CpTCldcstream (1<<29) /* D cache streaming switch */ 132 #define CpTCl2wralloc (1<<28) /* cache write allocate */ 133 #define CpTCl2prefdis (1<<24) /* l2 cache prefetch disable */ 134 #define CpTCl2ena (1<<22) /* l2 cache enable */ 135 136 /* CpTCl2flush & CpTCl2inv */ 137 #define CpTCl2all 0 138 #define CpTCl2seva 1 139 #define CpTCl2way 2 140 #define CpTCl2sepa 3 141 #define CpTCl2valow 4 142 #define CpTCl2vahigh 5 /* also triggers flush or inv */ 143 144 /* CpTCl2flush 145 #define CpTCecccnt 6 /* ecc error count */ 146 #define CpTCeccthr 7 /* ecc error threshold */ 147 148 /* CpTCl2waylck */ 149 #define CpTCl2waylock 7 150 151 /* CpTCl2inv */ 152 #define CpTCl2erraddr 7 /* ecc error address */ 153 154 /* CpTCl2perfctl */ 155 #define CpTCl2perf0ctl 0 156 #define CpTCl2perf1ctl 1 157 158 /* CpTCl2perfcnt */ 159 #define CpTCl2perf0low 0 160 #define CpTCl2perf0high 1 161 #define CpTCl2perf1low 2 162 #define CpTCl2perf1high 3 163 164 /* 165 * MMU page table entries. 166 * Mbo (0x10) bit is implementation-defined and mandatory on some pre-v7 arms. 167 */ 168 #define Mbo 0x10 /* must be 1 on earlier arms */ 169 #define Fault 0x00000000 /* L[12] pte: unmapped */ 170 171 #define Coarse (Mbo|1) /* L1 */ 172 #define Section (Mbo|2) /* L1 1MB */ 173 #define Fine (Mbo|3) /* L1 */ 174 175 #define Large 0x00000001u /* L2 64KB */ 176 #define Small 0x00000002u /* L2 4KB */ 177 #define Tiny 0x00000003u /* L2 1KB, deprecated */ 178 #define Buffered 0x00000004u /* L[12]: write-back not -thru */ 179 #define Cached 0x00000008u /* L[12] */ 180 181 #define Dom0 0 182 #define Noaccess 0 /* AP, DAC */ 183 #define Krw 1 /* AP */ 184 #define Uro 2 /* AP */ 185 #define Urw 3 /* AP */ 186 #define Client 1 /* DAC */ 187 #define Manager 3 /* DAC */ 188 189 #define AP(n, v) F((v), ((n)*2)+4, 2) 190 #define L1AP(ap) (AP(3, (ap))) /* in L1, only Sections have AP */ 191 #define L2AP(ap) (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap))) /* pre-armv7 */ 192 #define DAC(n, v) F((v), (n)*2, 2) 193 194 #define HVECTORS 0xffff0000 /* addr of vectors */ 195