| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 179 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 474 int64_t CmpImm = 0, CmpMask = 0; findInductionRegister() local
1453 int64_t CmpMask = 0, CmpValue = 0; loopCountMayWrapOrUnderFlow() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 624 Value *CmpMask = IC.Builder.CreateICmpNE( instCombineIntrinsic() local
|
| H A D | SIInstrInfo.cpp | 9700 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
9759 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
|
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2789 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
2826 isSuitableForMask(MachineInstr * & MI,Register SrcReg,int CmpMask,bool CommonUse) isSuitableForMask() argument
3015 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
3303 int64_t CmpMask, CmpValue; shouldSink() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 671 int64_t CmpMask, CmpValue; optimizeCmpInstr() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4766 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
5204 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
[all...] |
| H A D | X86ISelLowering.cpp | 25949 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask, SDValue(), LowerINTRINSIC_WO_CHAIN() local
46954 APInt CmpMask = APInt::getLowBitsSet(32, IsAnyOf ? 0 : BCNumElts); combineSetCCMOVMSK() local
46971 APInt CmpMask = APInt::getLowBitsSet(32, IsAnyOf ? 0 : NumElts / 2); combineSetCCMOVMSK() local
47054 unsigned CmpMask = IsAnyOf ? 0 : 0xFFFFFFFF; combineSetCCMOVMSK() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1175 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
1536 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
|
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2768 int64_t CmpMask, CmpValue; optimizeCmpPostRA() local
|