| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 592 buildUAddo(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1) buildUAddo() argument
598 buildUSubo(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1) buildUSubo() argument
604 buildSAddo(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1) buildSAddo() argument
610 buildSSubo(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1) buildSSubo() argument
629 buildUAdde(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1,const SrcOp & CarryIn) buildUAdde() argument
637 buildUSube(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1,const SrcOp & CarryIn) buildUSube() argument
645 buildSAdde(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1,const SrcOp & CarryIn) buildSAdde() argument
653 buildSSube(const DstOp & Res,const DstOp & CarryOut,const SrcOp & Op0,const SrcOp & Op1,const SrcOp & CarryIn) buildSSube() argument
[all...] |
| /llvm-project/clang/test/SemaCXX/ |
| H A D | builtins-overflow.cpp | 100 T CarryOut; member
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| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 374 auto CarryOut = InvertCarryFlag(Subtarget, CurDAG, Dl, SDValue(NewNode, 1)); in selectSubCarry() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 926 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst); pseudoOpConvertToVOP2() local
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| H A D | AMDGPULegalizerInfo.cpp | 3958 Carry CarryOut; buildMultiply() local
4105 if (Register CarryOut = mergeCarry(Accum[2 * i - 1], OddCarryIn)) buildMultiply() local
4109 if (Register CarryOut = mergeCarry(Accum[2 * i], EvenCarryIn)) buildMultiply() local
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| H A D | AMDGPURegisterBankInfo.cpp | 2602 Register CarryOut = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); applyMappingImpl() local
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| /llvm-project/clang/lib/AST/Interp/ |
| H A D | InterpBuiltin.cpp | |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 1956 Value *CarryOut = Builder.CreateExtractValue(Ret, {1}, "ext"); in createAddCarry() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5859 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); narrowScalarAddSub() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 5000 llvm::Value *CarryOut = Builder.CreateZExt(Builder.CreateOr(Carry1, Carry2), EmitBuiltinExpr() local
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| /llvm-project/clang/lib/AST/ |
| H A D | ExprConstant.cpp | 12976 APSInt LHS, RHS, CarryIn, CarryOut, Result; VisitBuiltinCallExpr() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 55244 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1)); combineADC() local
[all...] |