1 /* $NetBSD: octeon_corereg.h,v 1.5 2020/08/04 01:59:46 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _OCTEON_COREREG_H_ 30 #define _OCTEON_COREREG_H_ 31 32 /* ---- register bits */ 33 34 /* 35 * Cavium Networks-Specific Coprocessor 0 Registers 36 */ 37 38 /* CacheErr (Icache) */ 39 40 #define CP0_CACHEERRI_XXX_63_55 UINT64_C(0xff80000000000000) 41 #define CP0_CACHEERRI_BADCOLF UINT64_C(0x007f000000000000) 42 #define CP0_CACHEERRI_XXX_47 UINT64_C(0x0000800000000000) 43 #define CP0_CACHEERRI_BADCOL UINT64_C(0x00007f0000000000) 44 #define CP0_CACHEERRI_XXX_39_37 UINT64_C(0x000000e000000000) 45 #define CP0_CACHEERRI_LRUFAIL UINT64_C(0x0000001000000000) 46 #define CP0_CACHEERRI_AESFAIL UINT64_C(0x0000000800000000) 47 #define CP0_CACHEERRI_HSHFAIL UINT64_C(0x0000000400000000) 48 #define CP0_CACHEERRI_BHTBROKE UINT64_C(0x0000000200000000) 49 #define CP0_CACHEERRI_ICBROKE UINT64_C(0x0000000100000000) 50 #define CP0_CACHEERRI_XXX_31_15 UINT64_C(0x00000000ffff8000) 51 #define CP0_CACHEERRI_QW UINT64_C(0x0000000000006000) 52 #define CP0_CACHEERRI_ROW UINT64_C(0x0000000000001800) 53 #define CP0_CACHEERRI_SET UINT64_C(0x00000000000007e0) 54 #define CP0_CACHEERRI_WAY UINT64_C(0x0000000000000018) 55 #define CP0_CACHEERRI_XXX_2_1 UINT64_C(0x0000000000000006) 56 #define CP0_CACHEERRI_DPERR UINT64_C(0x0000000000000001) 57 58 /* CacheErr (Dcache) */ 59 60 #define CP0_CACHEERRD_XXX_63_13 UINT64_C(0xffffffffffffe000) 61 #define CP0_CACHEERRD_SET UINT64_C(0x0000000000001f80) 62 #define CP0_CACHEERRD_VA63 UINT64_C(0x0000000000000078) 63 #define CP0_CACHEERRD_XXX_2_1 UINT64_C(0x0000000000000006) 64 #define CP0_CACHEERRD_PERR UINT64_C(0x0000000000000001) 65 66 /* TagLo Register (Icache) */ 67 68 #define CP0_TAGLOI_R UINT64_C(0xc000000000000000) 69 #define CP0_TAGLOI_XXX_61_60 UINT64_C(0x3000000000000000) 70 #define CP0_TAGLOI_ASID UINT64_C(0x0f00000000000000) 71 #define CP0_TAGLOI_XXX_51_49 UINT64_C(0x00f0000000000000) 72 #define CP0_TAGLOI_TAG UINT64_C(0x000fffffffffe000) 73 #define CP0_TAGLOI_INDEX UINT64_C(0x0000000000001f80) 74 #define CP0_TAGLOI_XXX_6_2 UINT64_C(0x000000000000007c) 75 #define CP0_TAGLOI_G UINT64_C(0x0000000000000002) 76 #define CP0_TAGLOI_VALID UINT64_C(0x0000000000000001) 77 78 /* TagLo Register (Dcache) */ 79 80 #define CP0_TAGLOD_R UINT64_C(0xc000000000000000) 81 #define CP0_TAGLOD_XXX_61_60 UINT64_C(0x3000000000000000) 82 #define CP0_TAGLOD_ASID UINT64_C(0x0f00000000000000) 83 #define CP0_TAGLOD_XXX_51_49 UINT64_C(0x00f0000000000000) 84 #define CP0_TAGLOD_TAG UINT64_C(0x000fffffffffff80) 85 #define CP0_TAGLOD_XXX_6_2 UINT64_C(0x000000000000007c) 86 #define CP0_TAGLOD_G UINT64_C(0x0000000000000002) 87 #define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001) 88 89 /* CvmCtl Register */ 90 /* CVMCTL_STEPRATE to CVMCTL_TLBBRFTDIS are available on cnMIPS III cores */ 91 92 #define CP0_CVMCTL_XXX_63_43 UINT64_C(0xfffff80000000000) 93 #define CP0_CVMCTL_STEPRATE UINT64_C(0x0000078000000000) 94 #define CP0_CVMCTL_ZUC UINT64_C(0x0000004000000000) 95 #define CP0_CVMCTL_CAMELLIA UINT64_C(0x0000002000000000) 96 #define CP0_CVMCTL_USEMAK UINT64_C(0x0000001000000000) 97 #define CP0_CVMCTL_SMS4 UINT64_C(0x0000000800000000) 98 #define CP0_CVMCTL_DISABLEPAUSE UINT64_C(0x0000000400000000) 99 #define CP0_CVMCTL_SNOW3G UINT64_C(0x0000000200000000) 100 #define CP0_CVMCTL_TLBBRFTDIS UINT64_C(0x0000000100000000) 101 #define CP0_CVMCTL_FUSE_STARTBIT UINT64_C(0x0000000080000000) 102 #define CP0_CVMCTL_XXX_30 UINT64_C(0x0000000040000000) 103 #define CP0_CVMCTL_KASUMI UINT64_C(0x0000000020000000) 104 #define CP0_CVMCTL_NODFA_CP21 UINT64_C(0x0000000010000000) 105 #define CP0_CVMCTL_NOMUL UINT64_C(0x0000000008000000) 106 #define CP0_CVMCTL_NOCRYPTO UINT64_C(0x0000000004000000) 107 #define CP0_CVMCTL_RST_SHT UINT64_C(0x0000000002000000) 108 #define CP0_CVMCTL_BIST_DIS UINT64_C(0x0000000001000000) 109 #define CP0_CVMCTL_DISSETPRED UINT64_C(0x0000000000800000) 110 #define CP0_CVMCTL_DISJRPRED UINT64_C(0x0000000000400000) 111 #define CP0_CVMCTL_DISICACHE UINT64_C(0x0000000000200000) 112 #define CP0_CVMCTL_DISWAIT UINT64_C(0x0000000000100000) 113 #define CP0_CVMCTL_DEFET UINT64_C(0x0000000000080000) 114 #define CP0_CVMCTL_DISCO UINT64_C(0x0000000000040000) 115 #define CP0_CVMCTL_DISCE UINT64_C(0x0000000000020000) 116 #define CP0_CVMCTL_DDCLK UINT64_C(0x0000000000010000) 117 #define CP0_CVMCTL_DCICLK UINT64_C(0x0000000000008000) 118 #define CP0_CVMCTL_REPUN UINT64_C(0x0000000000004000) 119 #define CP0_CVMCTL_IPREF UINT64_C(0x0000000000002000) 120 #define CP0_CVMCTL_USEUN UINT64_C(0x0000000000001000) 121 #define CP0_CVMCTL_DISIOCACHE UINT64_C(0x0000000000000800) 122 #define CP0_CVMCTL_IRAND UINT64_C(0x0000000000000400) 123 #define CP0_CVMCTL_IPPCI UINT64_C(0x0000000000000380) 124 #define CP0_CVMCTL_IPTI UINT64_C(0x0000000000000070) 125 #define CP0_CVMCTL_XXX_3_2 UINT64_C(0x000000000000000c) 126 #define CP0_CVMCTL_LE UINT64_C(0x0000000000000002) 127 #define CP0_CVMCTL_USELY UINT64_C(0x0000000000000001) 128 129 /* CvmMemCtl Register */ 130 131 #define CP0_CVMMEMCTL_TLBBIST UINT64_C(0x8000000000000000) 132 #define CP0_CVMMEMCTL_L1CBIST UINT64_C(0x4000000000000000) 133 #define CP0_CVMMEMCTL_L1DBIST UINT64_C(0x2000000000000000) 134 #define CP0_CVMMEMCTL_DCMBIST UINT64_C(0x1000000000000000) 135 #define CP0_CVMMEMCTL_PTGBIST UINT64_C(0x0800000000000000) 136 #define CP0_CVMMEMCTL_WBFBIST UINT64_C(0x0400000000000000) 137 #define CP0_CVMMEMCTL_XXX_57_36 UINT64_C(0x03fffff000000000) 138 #define CP0_CVMMEMCTL_DISMARKWBLONGTO UINT64_C(0x0000000800000000) 139 #define CP0_CVMMEMCTL_DISMRGCLRWBTO UINT64_C(0x0000000400000000) 140 #define CP0_CVMMEMCTL_IOBDMASCRMSB UINT64_C(0x0000000300000000) 141 #define CP0_CVMMEMCTL_SYNCWSMARKED UINT64_C(0x0000000080000000) 142 #define CP0_CVMMEMCTL_DISSYNCWS UINT64_C(0x0000000040000000) 143 #define CP0_CVMMEMCTL_DISWBFST UINT64_C(0x0000000020000000) 144 #define CP0_CVMMEMCTL_XKMEMENAS UINT64_C(0x0000000010000000) 145 #define CP0_CVMMEMCTL_XKMEMENAU UINT64_C(0x0000000008000000) 146 #define CP0_CVMMEMCTL_XKIOENAS UINT64_C(0x0000000004000000) 147 #define CP0_CVMMEMCTL_XKIOENAU UINT64_C(0x0000000002000000) 148 #define CP0_CVMMEMCTL_ALLSYNCW UINT64_C(0x0000000001000000) 149 #define CP0_CVMMEMCTL_NOMERGE UINT64_C(0x0000000000800000) 150 #define CP0_CVMMEMCTL_DIDTTO UINT64_C(0x0000000000600000) 151 #define CP0_CVMMEMCTL_CSRCLKALWYS UINT64_C(0x0000000000100000) 152 #define CP0_CVMMEMCTL_MCLKALWYS UINT64_C(0x0000000000080000) 153 #define CP0_CVMMEMCTL_WBFLTIME UINT64_C(0x0000000000070000) 154 #define CP0_CVMMEMCTL_ISTRNOL2 UINT64_C(0x0000000000008000) 155 #define CP0_CVMMEMCTL_WBTHRESH UINT64_C(0x0000000000007800) 156 #define CP0_CVMMEMCTL_XXX_10_9 UINT64_C(0x0000000000000600) 157 #define CP0_CVMMEMCTL_CVMSEGENAK UINT64_C(0x0000000000000100) 158 #define CP0_CVMMEMCTL_CVMSEGENAS UINT64_C(0x0000000000000080) 159 #define CP0_CVMMEMCTL_CVMSEGENAU UINT64_C(0x0000000000000040) 160 #define CP0_CVMMEMCTL_LMEMSZ UINT64_C(0x000000000000003f) 161 162 /* CvmCount Register */ 163 164 /* Multi-Core Debug Register */ 165 166 #define CP0_MCD_XXX_63_17 UINT64_C(0xfffffffffffe0000) 167 #define CP0_MCD_DEXCC UINT64_C(0x0000000000010000) 168 #define CP0_MCD_CGSTP UINT64_C(0x0000000000008000) 169 #define CP0_MCD_CVGSTP UINT64_C(0x0000000000004000) 170 #define CP0_MCD_CVDM UINT64_C(0x0000000000002000) 171 #define CP0_MCD_GSDB UINT64_C(0x0000000000001000) 172 #define CP0_MCD_XXX_11 UINT64_C(0x0000000000000800) 173 #define CP0_MCD_MSKM2 UINT64_C(0x0000000000000400) 174 #define CP0_MCD_MSKM1 UINT64_C(0x0000000000000200) 175 #define CP0_MCD_MMC0 UINT64_C(0x0000000000000100) 176 #define CP0_MCD_XXX_7 UINT64_C(0x0000000000000080) 177 #define CP0_MCD_PLS2 UINT64_C(0x0000000000000040) 178 #define CP0_MCD_PLS1 UINT64_C(0x0000000000000020) 179 #define CP0_MCD_PLS0 UINT64_C(0x0000000000000010) 180 #define CP0_MCD_XXX_3 UINT64_C(0x0000000000000008) 181 #define CP0_MCD_MCD2 UINT64_C(0x0000000000000004) 182 #define CP0_MCD_MCD1 UINT64_C(0x0000000000000002) 183 #define CP0_MCD_MCD0 UINT64_C(0x0000000000000001) 184 185 /* ---- operations */ 186 187 /* 188 * OCTEON Configuration and Status Registers (CSRs) 189 */ 190 191 #define CSR_COP0 /* Core coprosessor 0 registers */ 192 #define CSR_COP2 /* Core coprosessor 2 registers */ 193 #define CSR_COREEJTAG /* Core EJTAG registers */ 194 #define CSR_COREEJTAGTAP /* Core EJTAG TAP registers */ 195 #define CSR_NCB /* NCB registers */ 196 #define CSR_RSL /* RSL registers */ 197 #define CSR_PCICONFIG /* PCICONFIG registers */ 198 #define CSR_PCI /* PCI registers */ 199 #define CSR_PCINCB /* PCI_NCB registers */ 200 #define CSR_JTAGTAP /* JTAG TAP registers */ 201 #define CSR_TWSICORE /* TWSI Core registers */ 202 203 /* XXX */ 204 205 #endif /* _OCTEON_COREREG_H_ */ 206