1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 /* 6 * Sizes 7 */ 8 9 #define BI2BY 8 /* bits per byte */ 10 #define BI2WD 32 /* bits per word */ 11 #define BY2WD 4 /* bytes per word */ 12 #define BY2V 8 /* bytes per vlong */ 13 14 #define MAXBY2PG (16*1024) /* rounding for UTZERO in executables; see mkfile */ 15 #define UTROUND(t) ROUNDUP((t), MAXBY2PG) 16 17 #ifndef BIGPAGES 18 #define BY2PG 4096 /* bytes per page */ 19 #define PGSHIFT 12 /* log2(BY2PG) */ 20 #define PGSZ PGSZ4K 21 #define MACHSIZE (2*BY2PG) 22 #else 23 /* 16K pages work very poorly */ 24 #define BY2PG (16*1024) /* bytes per page */ 25 #define PGSHIFT 14 /* log2(BY2PG) */ 26 #define PGSZ PGSZ16K 27 #define MACHSIZE BY2PG 28 #endif 29 30 #define KSTACK 8192 /* Size of kernel stack */ 31 #define WD2PG (BY2PG/BY2WD) /* words per page */ 32 33 #define MAXMACH 1 /* max # cpus system can run; see active.machs */ 34 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */ 35 #define BLOCKALIGN 16 36 #define CACHELINESZ 32 /* mips24k */ 37 #define ICACHESIZE (64*1024) /* rb450g */ 38 #define DCACHESIZE (32*1024) /* rb450g */ 39 40 #define MASK(w) FMASK(0, w) 41 42 /* 43 * Time 44 */ 45 #define HZ 100 /* clock frequency */ 46 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 47 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 48 49 /* 50 * CP0 registers 51 */ 52 53 #define INDEX 0 54 #define RANDOM 1 55 #define TLBPHYS0 2 /* aka ENTRYLO0 */ 56 #define TLBPHYS1 3 /* aka ENTRYLO1 */ 57 #define CONTEXT 4 58 #define PAGEMASK 5 59 #define WIRED 6 60 #define BADVADDR 8 61 #define COUNT 9 62 #define TLBVIRT 10 /* aka ENTRYHI */ 63 #define COMPARE 11 64 #define STATUS 12 65 #define CAUSE 13 66 #define EPC 14 67 #define PRID 15 68 #define CONFIG 16 69 #define LLADDR 17 70 #define WATCHLO 18 71 #define WATCHHI 19 72 #define DEBUG 23 73 #define DEPC 24 74 #define PERFCOUNT 25 75 #define CACHEECC 26 76 #define CACHEERR 27 77 #define TAGLO 28 78 #define TAGHI 29 79 #define ERROREPC 30 80 #define DESAVE 31 81 82 /* 83 * M(STATUS) bits 84 */ 85 #define KMODEMASK 0x0000001f 86 #define IE 0x00000001 /* master interrupt enable */ 87 #define EXL 0x00000002 /* exception level */ 88 #define ERL 0x00000004 /* error level */ 89 #define KSUPER 0x00000008 90 #define KUSER 0x00000010 91 #define KSU 0x00000018 92 //#define UX 0x00000020 /* no [USK]X 64-bit extension bits on 24k */ 93 //#define SX 0x00000040 94 //#define KX 0x00000080 95 #define INTMASK 0x0000ff00 96 #define INTR0 0x00000100 /* interrupt enable bits */ 97 #define INTR1 0x00000200 98 #define INTR2 0x00000400 99 #define INTR3 0x00000800 100 #define INTR4 0x00001000 101 #define INTR5 0x00002000 102 #define INTR6 0x00004000 103 #define INTR7 0x00008000 104 //#define DE 0x00010000 /* not on 24k */ 105 #define TS 0x00200000 /* tlb shutdown; on 24k at least */ 106 #define BEV 0x00400000 /* bootstrap exception vectors */ 107 #define RE 0x02000000 /* reverse-endian in user mode */ 108 #define FR 0x04000000 /* enable 32 FP regs */ 109 #define CU0 0x10000000 110 #define CU1 0x20000000 /* FPU enable */ 111 112 /* 113 * M(CONFIG) bits 114 */ 115 116 #define CFG_K0 7 /* kseg0 cachability */ 117 #define CFG_MM (1<<18) /* write-through merging enabled */ 118 119 /* 120 * M(CAUSE) bits 121 */ 122 123 #define BD (1<<31) /* last excep'n occurred in branch delay slot */ 124 125 /* 126 * Exception codes 127 */ 128 #define EXCMASK 0x1f /* mask of all causes */ 129 #define CINT 0 /* external interrupt */ 130 #define CTLBM 1 /* TLB modification: store to unwritable page */ 131 #define CTLBL 2 /* TLB miss (load or fetch) */ 132 #define CTLBS 3 /* TLB miss (store) */ 133 #define CADREL 4 /* address error (load or fetch) */ 134 #define CADRES 5 /* address error (store) */ 135 #define CBUSI 6 /* bus error (fetch) */ 136 #define CBUSD 7 /* bus error (data load or store) */ 137 #define CSYS 8 /* system call */ 138 #define CBRK 9 /* breakpoint */ 139 #define CRES 10 /* reserved instruction */ 140 #define CCPU 11 /* coprocessor unusable */ 141 #define COVF 12 /* arithmetic overflow */ 142 #define CTRAP 13 /* trap */ 143 #define CVCEI 14 /* virtual coherence exception (instruction) */ 144 #define CFPE 15 /* floating point exception */ 145 #define CTLBRI 19 /* tlb read-inhibit */ 146 #define CTLBXI 20 /* tlb execute-inhibit */ 147 #define CWATCH 23 /* watch exception */ 148 #define CMCHK 24 /* machine checkcore */ 149 #define CCACHERR 30 /* cache error */ 150 #define CVCED 31 /* virtual coherence exception (data) */ 151 152 /* 153 * M(CACHEECC) a.k.a. ErrCtl bits 154 */ 155 #define PE (1<<31) 156 #define LBE (1<<25) 157 #define WABE (1<<24) 158 159 /* 160 * Trap vectors 161 */ 162 163 #define UTLBMISS (KSEG0+0x000) 164 #define XEXCEPTION (KSEG0+0x080) 165 #define CACHETRAP (KSEG0+0x100) 166 #define EXCEPTION (KSEG0+0x180) 167 168 /* 169 * Magic registers 170 */ 171 172 #define USER 24 /* R24 is up-> */ 173 #define MACH 25 /* R25 is m-> */ 174 175 /* 176 * offsets in ureg.h for l.s 177 */ 178 #define Ureg_status (Uoffset+0) 179 #define Ureg_pc (Uoffset+4) 180 #define Ureg_sp (Uoffset+8) 181 #define Ureg_cause (Uoffset+12) 182 #define Ureg_badvaddr (Uoffset+16) 183 #define Ureg_tlbvirt (Uoffset+20) 184 185 #define Ureg_hi (Uoffset+24) 186 #define Ureg_lo (Uoffset+28) 187 #define Ureg_r31 (Uoffset+32) 188 #define Ureg_r30 (Uoffset+36) 189 #define Ureg_r28 (Uoffset+40) 190 #define Ureg_r27 (Uoffset+44) 191 #define Ureg_r26 (Uoffset+48) 192 #define Ureg_r25 (Uoffset+52) 193 #define Ureg_r24 (Uoffset+56) 194 #define Ureg_r23 (Uoffset+60) 195 #define Ureg_r22 (Uoffset+64) 196 #define Ureg_r21 (Uoffset+68) 197 #define Ureg_r20 (Uoffset+72) 198 #define Ureg_r19 (Uoffset+76) 199 #define Ureg_r18 (Uoffset+80) 200 #define Ureg_r17 (Uoffset+84) 201 #define Ureg_r16 (Uoffset+88) 202 #define Ureg_r15 (Uoffset+92) 203 #define Ureg_r14 (Uoffset+96) 204 #define Ureg_r13 (Uoffset+100) 205 #define Ureg_r12 (Uoffset+104) 206 #define Ureg_r11 (Uoffset+108) 207 #define Ureg_r10 (Uoffset+112) 208 #define Ureg_r9 (Uoffset+116) 209 #define Ureg_r8 (Uoffset+120) 210 #define Ureg_r7 (Uoffset+124) 211 #define Ureg_r6 (Uoffset+128) 212 #define Ureg_r5 (Uoffset+132) 213 #define Ureg_r4 (Uoffset+136) 214 #define Ureg_r3 (Uoffset+140) 215 #define Ureg_r2 (Uoffset+144) 216 #define Ureg_r1 (Uoffset+148) 217 218 /* ch and carrera used these defs */ 219 /* Sizeof(Ureg) + (R5,R6) + 16 bytes slop + retpc + ur */ 220 // #define UREGSIZE ((Ureg_r1+4-Uoffset) + 2*BY2V + 16 + BY2WD + BY2WD) 221 // #define Uoffset 8 222 223 // #define UREGSIZE (Ureg_r1 + 4 - Uoffset) /* this ought to work */ 224 #define UREGSIZE ((Ureg_r1+4-Uoffset) + 2*BY2V + 16 + BY2WD + BY2WD) 225 #define Uoffset 0 226 #define Notuoffset 8 227 228 /* 229 * MMU 230 */ 231 #define PGSZ4K (0x00<<13) 232 #define PGSZ16K (0x03<<13) /* on 24k */ 233 #define PGSZ64K (0x0F<<13) 234 #define PGSZ256K (0x3F<<13) 235 #define PGSZ1M (0xFF<<13) 236 #define PGSZ4M (0x3FF<<13) 237 // #define PGSZ8M (0x7FF<<13) /* not on 24k */ 238 #define PGSZ16M (0xFFF<<13) 239 #define PGSZ64M (0x3FFF<<13) /* on 24k */ 240 #define PGSZ256M (0xFFFF<<13) /* on 24k */ 241 242 /* mips address spaces, tlb-mapped unless marked otherwise */ 243 #define KUSEG 0x00000000 /* user process */ 244 #define KSEG0 0x80000000 /* kernel (direct mapped, cached) */ 245 #define KSEG1 0xA0000000 /* kernel (direct mapped, uncached: i/o) */ 246 #define KSEG2 0xC0000000 /* kernel, used for TSTKTOP */ 247 #define KSEG3 0xE0000000 /* kernel, used by kmap */ 248 #define KSEGM 0xE0000000 /* mask to check which seg */ 249 250 /* 251 * Fundamental addresses 252 */ 253 254 #define REBOOTADDR KADDR(0x1000) /* just above vectors */ 255 #define MACHADDR 0x80005000 /* Mach structures */ 256 #define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE)) 257 #define ROM 0xbfc00000 258 #define KMAPADDR 0xE0000000 /* kmap'd addresses */ 259 #define WIREDADDR 0xE2000000 /* address wired kernel space */ 260 261 #define PHYSCONS (KSEG1|0x18020000) /* i8250 uart */ 262 263 #define PIDXSHFT 12 264 #ifndef BIGPAGES 265 #define NCOLOR 8 266 #define PIDX ((NCOLOR-1)<<PIDXSHFT) 267 #define getpgcolor(a) (((ulong)(a)>>PIDXSHFT) % NCOLOR) 268 #else 269 /* no cache aliases are possible with pages of 16K or larger */ 270 #define NCOLOR 1 271 #define PIDX 0 272 #define getpgcolor(a) 0 273 #endif 274 #define KMAPSHIFT 15 275 276 #define PTEGLOBL (1<<0) 277 #define PTEVALID (1<<1) 278 #define PTEWRITE (1<<2) 279 #define PTERONLY 0 280 #define PTEALGMASK (7<<3) 281 #define PTENONCOHERWT (0<<3) /* cached, write-through (slower) */ 282 #define PTEUNCACHED (2<<3) 283 #define PTENONCOHERWB (3<<3) /* cached, write-back */ 284 #define PTEUNCACHEDACC (7<<3) 285 /* rest are reserved on 24k */ 286 #define PTECOHERXCL (4<<3) 287 #define PTECOHERXCLW (5<<3) 288 #define PTECOHERUPDW (6<<3) 289 290 /* how much faster is it? mflops goes from about .206 (WT) to .37 (WB) */ 291 #define PTECACHABILITY PTENONCOHERWT /* 24k erratum 48 disallows WB */ 292 // #define PTECACHABILITY PTENONCOHERWB 293 294 #define PTEPID(n) (n) 295 #define PTEMAPMEM (1024*1024) 296 #define PTEPERTAB (PTEMAPMEM/BY2PG) 297 #define SEGMAPSIZE 512 298 #define SSEGMAPSIZE 16 299 300 #define STLBLOG 15 301 #define STLBSIZE (1<<STLBLOG) /* entries in the soft TLB */ 302 /* page # bits that don't fit in STLBLOG bits */ 303 #define HIPFNBITS (BI2WD - (PGSHIFT+1) - STLBLOG) 304 #define KPTELOG 8 305 #define KPTESIZE (1<<KPTELOG) /* entries in the kfault soft TLB */ 306 307 #define TLBPID(n) ((n)&0xFF) 308 #define NTLBPID 256 /* # of pids (affects size of Mach) */ 309 #define NTLB 16 /* # of entries (mips 24k) */ 310 #define TLBOFF 1 /* first tlb entry (0 used within mmuswitch) */ 311 #define NKTLB 2 /* # of initial kfault tlb entries */ 312 #define WTLBOFF (TLBOFF+NKTLB) /* first large IO window tlb entry */ 313 #define NWTLB 0 /* # of large IO window tlb entries */ 314 #define TLBROFF (WTLBOFF+NWTLB) /* offset of first randomly-indexed entry */ 315 316 /* 317 * Address spaces 318 */ 319 #define UZERO KUSEG /* base of user address space */ 320 #define UTZERO (UZERO+MAXBY2PG) /* 1st user text address; see mkfile */ 321 #define USTKTOP (KZERO-BY2PG) /* byte just beyond user stack */ 322 #define USTKSIZE (8*1024*1024) /* size of user stack */ 323 #define TSTKTOP (KSEG2+USTKSIZE-BY2PG) /* top of temporary stack */ 324 #define TSTKSIZ (1024*1024/BY2PG) /* can be at most UTSKSIZE/BY2PG */ 325 #define KZERO KSEG0 /* base of kernel address space */ 326 #define KTZERO (KZERO+0x20000) /* first address in kernel text */ 327 #define MEMSIZE (256*MB) /* fixed memory on routerboard */ 328 #define PCIMEM 0x10000000 /* on rb450g */ 329