1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 #ifdef ucuconf 6 #include "ucu.h" 7 #else 8 #include "blast.h" 9 #endif 10 11 /* 12 * Sizes 13 */ 14 15 #define BI2BY 8 /* bits per byte */ 16 #define BI2WD 32 /* bits per word */ 17 #define BY2WD 4 /* bytes per word */ 18 #define BY2V 8 /* bytes per vlong */ 19 #define BY2PG 4096 /* bytes per page */ 20 #define WD2PG (BY2PG/BY2WD) /* words per page */ 21 #define PGSHIFT 12 /* log(BY2PG) */ 22 #define CACHELINELOG 5 23 #define CACHELINESZ (1<<CACHELINELOG) 24 #define BLOCKALIGN CACHELINESZ 25 26 #define MHz 1000000 27 28 #define BY2PTE 8 /* bytes per pte entry */ 29 #define BY2PTEG 64 /* bytes per pte group */ 30 31 #define MAXMACH 1 /* max # cpus system can run */ 32 #define MACHSIZE BY2PG 33 #define KSTACK 4096 /* Size of kernel stack */ 34 35 /* 36 * Time 37 */ 38 #define HZ 1000 /* clock frequency */ 39 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 40 41 /* 42 * Standard PPC Special Purpose Registers (OEA and VEA) 43 */ 44 #define DSISR 18 45 #define DAR 19 /* Data Address Register */ 46 #define DEC 22 /* Decrementer */ 47 #define SDR1 25 48 #define SRR0 26 /* Saved Registers (exception) */ 49 #define SRR1 27 50 #define TBRL 268 51 #define TBRU 269 /* Time base Upper/Lower (Reading) */ 52 #define SPRG0 272 /* Supervisor Private Registers */ 53 #define SPRG1 273 54 #define SPRG2 274 55 #define SPRG3 275 56 #define SPRG4 276 57 #define SPRG5 277 58 #define SPRG6 278 59 #define SPRG7 279 60 #define ASR 280 /* Address Space Register */ 61 #define EAR 282 /* External Access Register (optional) */ 62 #define TBWU 284 /* Time base Upper/Lower (Writing) */ 63 #define TBWL 285 64 #define PVR 287 /* Processor Version */ 65 #define IABR 1010 /* Instruction Address Breakpoint Register (optional) */ 66 #define DABR 1013 /* Data Address Breakpoint Register (optional) */ 67 #define FPECR 1022 /* Floating-Point Exception Cause Register (optional) */ 68 #define PIR 1023 /* Processor Identification Register (optional) */ 69 70 #define IBATU(i) (528+2*(i)) /* Instruction BAT register (upper) */ 71 #define IBATL(i) (529+2*(i)) /* Instruction BAT register (lower) */ 72 #define DBATU(i) (536+2*(i)) /* Data BAT register (upper) */ 73 #define DBATL(i) (537+2*(i)) /* Data BAT register (lower) */ 74 75 /* 76 * PPC604e-specific Special Purpose Registers (OEA) 77 */ 78 #define MMCR0 952 /* Monitor Control Register 0 */ 79 #define PMC1 953 /* Performance Monitor Counter 1 */ 80 #define PMC2 954 /* Performance Monitor Counter 2 */ 81 #define SIA 955 /* Sampled Instruction Address */ 82 #define MMCR1 956 /* Monitor Control Register 0 */ 83 #define PMC3 957 /* Performance Monitor Counter 3 */ 84 #define PMC4 958 /* Performance Monitor Counter 4 */ 85 #define SDA 959 /* Sampled Data Address */ 86 /* 87 * PPC603e-specific Special Purpose Registers 88 */ 89 #define DMISS 976 /* Data Miss Address Register */ 90 #define DCMP 977 /* Data Miss Address Register */ 91 #define HASH1 978 92 #define HASH2 979 93 #define IMISS 980 /* Instruction Miss Address Register */ 94 #define iCMP 981 /* Instruction Miss Address Register */ 95 #define RPA 982 96 #define HID0 1008 /* Hardware Implementation Dependent Register 0 */ 97 #define HID1 1009 /* Hardware Implementation Dependent Register 1 */ 98 /* 99 * PowerQUICC II (MPC 8260) Special Purpose Registers 100 */ 101 #define HID2 1011 /* Hardware Implementation Dependent Register 2 */ 102 103 #define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */ 104 #define SBIT(n) ((ushort)1<<(15-(n))) 105 #define RBIT(b,n) (1<<(8*sizeof(n)-1-(b))) 106 107 /* 108 * Bit encodings for Machine State Register (MSR) 109 */ 110 #define MSR_POW BIT(13) /* Enable Power Management */ 111 #define MSR_TGPR BIT(14) /* Temporary GPR Registers in use (603e) */ 112 #define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */ 113 #define MSR_EE BIT(16) /* External Interrupt enable */ 114 #define MSR_PR BIT(17) /* Supervisor/User privilege */ 115 #define MSR_FP BIT(18) /* Floating Point enable */ 116 #define MSR_ME BIT(19) /* Machine Check enable */ 117 #define MSR_FE0 BIT(20) /* Floating Exception mode 0 */ 118 #define MSR_SE BIT(21) /* Single Step (optional) */ 119 #define MSR_BE BIT(22) /* Branch Trace (optional) */ 120 #define MSR_FE1 BIT(23) /* Floating Exception mode 1 */ 121 #define MSR_IP BIT(25) /* Exception prefix 0x000/0xFFF */ 122 #define MSR_IR BIT(26) /* Instruction MMU enable */ 123 #define MSR_DR BIT(27) /* Data MMU enable */ 124 #define MSR_PM BIT(29) /* Performance Monitor marked mode (604e specific) */ 125 #define MSR_RI BIT(30) /* Recoverable Exception */ 126 #define MSR_LE BIT(31) /* Little-Endian enable */ 127 /* SRR1 bits for TLB operations */ 128 #define MSR_SR0 0xf0000000 /* Saved bits from CR register */ 129 #define MSR_KEY BIT(12) /* Copy of Ks or Kp bit */ 130 #define MSR_IMISS BIT(13) /* It was an I miss */ 131 #define MSR_WAY BIT(14) /* TLB set to be replaced */ 132 #define MSR_STORE BIT(15) /* Miss caused by a store */ 133 134 /* 135 * Exception codes (trap vectors) 136 */ 137 #define CRESET 0x01 138 #define CMCHECK 0x02 139 #define CDSI 0x03 140 #define CISI 0x04 141 #define CEI 0x05 142 #define CALIGN 0x06 143 #define CPROG 0x07 144 #define CFPU 0x08 145 #define CDEC 0x09 146 #define CSYSCALL 0x0C 147 #define CTRACE 0x0D /* optional */ 148 #define CFPA 0x0E /* not implemented in 603e */ 149 150 /* PPC603e-specific: */ 151 #define CIMISS 0x10 /* Instruction TLB miss */ 152 #define CLMISS 0x11 /* Data load TLB miss */ 153 #define CSMISS 0x12 /* Data store TLB miss */ 154 #define CIBREAK 0x13 155 #define CSMI 0x14 156 157 /* 158 * Magic registers 159 */ 160 161 #define MACH 30 /* R30 is m-> */ 162 #define USER 29 /* R29 is up-> */ 163 164 165 /* 166 * virtual MMU 167 */ 168 #define PTEMAPMEM (1024*1024) 169 #define PTEPERTAB (PTEMAPMEM/BY2PG) 170 #define SEGMAPSIZE 1984 171 #define SSEGMAPSIZE 16 172 #define PPN(x) ((x)&~(BY2PG-1)) 173 174 /* 175 * First pte word 176 */ 177 #define PTE0(v, vsid, h, va) (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f)) 178 179 /* 180 * Second pte word; WIMG & PP(RW/RO) common to page table and BATs 181 */ 182 #define PTE1_R BIT(23) 183 #define PTE1_C BIT(24) 184 185 #define PTE1_W BIT(25) 186 #define PTE1_I BIT(26) 187 #define PTE1_M BIT(27) 188 #define PTE1_G BIT(28) 189 190 #define PTE1_RW BIT(30) 191 #define PTE1_RO BIT(31) 192 193 /* HID0 register bits */ 194 #define HID_ICE BIT(16) 195 #define HID_DCE BIT(17) 196 #define HID_ILOCK BIT(18) 197 #define HID_DLOCK BIT(19) 198 #define HID_ICFI BIT(20) 199 #define HID_DCFI BIT(21) 200 #define HID_IFEM BIT(24) 201 202 /* 203 * Address spaces 204 */ 205 206 #define KZERO 0x80000000 /* base of kernel address space */ 207 #define KTZERO 0x80100000 /* first address in kernel text */ 208 #define UZERO 0 /* base of user address space */ 209 #define UTZERO (UZERO+BY2PG) /* first address in user text */ 210 #define UTROUND(t) ROUNDUP((t), 0x100000) 211 #define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */ 212 #define TSTKTOP KZERO /* top of temporary stack */ 213 #define TSTKSIZ 100 214 #define USTKSIZE (4*1024*1024) /* size of user stack */ 215 #define UREGSIZE ((8+40)*4) 216 #define MACHADDR (KTZERO-MAXMACH*MACHSIZE) 217 #define MACHPADDR (MACHADDR&~KZERO) 218 #define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE)) 219 220 #define isphys(x) (((ulong)x&KZERO)!=0) 221 222 /* 223 * MPC8xx addresses 224 */ 225 #define INTMEM 0xf0000000 226 #define IOMEM (INTMEM+0x10000) 227 228 #define getpgcolor(a) 0 229