1 /* $NetBSD: tegra_cecreg.h,v 1.1 2015/08/01 21:20:11 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_CECREG_H 30 #define _ARM_TEGRA_CECREG_H 31 32 #define CEC_SW_CONTROL_REG 0x00 33 #define CEC_SW_CONTROL_MODE __BIT(31) 34 #define CEC_SW_CONTROL_FILTERED_RX_DATA_PIN __BIT(4) 35 #define CEC_SW_CONTROL_RAW_INPUT_DATA_PIN __BIT(0) 36 37 #define CEC_HW_CONTROL_REG 0x04 38 #define CEC_HW_CONTROL_TX_RX_MODE __BIT(31) 39 #define CEC_HW_CONTROL_FAST_SIM_MODE __BIT(30) 40 #define CEC_HW_CONTROL_TX_NAK_MODE __BIT(24) 41 #define CEC_HW_CONTROL_RX_NAK_MODE __BIT(16) 42 #define CEC_HW_CONTROL_RX_SNOOP __BIT(15) 43 #define CEC_HW_CONTROL_RX_LOGICAL_ADDRS __BITS(14,0) 44 45 #define CEC_INPUT_FILTER_REG 0x08 46 #define CEC_INPUT_FILTER_MODE __BIT(31) 47 #define CEC_INPUT_FILTER_FIFO_LENGTH __BITS(5,0) 48 49 #define CEC_SPARE_REG 0x0c 50 51 #define CEC_TX_REGISTER_REG 0x10 52 #define CEC_TX_REGISTER_RETRY_FRAME __BIT(17) 53 #define CEC_TX_REGISTER_GENERATE_START_BIT __BIT(16) 54 #define CEC_TX_REGISTER_ADDRESS_MODE __BIT(12) 55 #define CEC_TX_REGISTER_EOM __BIT(8) 56 #define CEC_TX_REGISTER_DATA __BITS(7,0) 57 58 #define CEC_RX_REGISTER_REG 0x14 59 #define CEC_RX_REGISTER_ACK __BIT(9) 60 #define CEC_RX_REGISTER_EOM __BIT(8) 61 #define CEC_RX_REGISTER_DATA __BITS(7,0) 62 63 #define CEC_RX_TIMING_0_REG 0x18 64 #define CEC_RX_TIMING_1_REG 0x1c 65 #define CEC_RX_TIMING_2_REG 0x20 66 #define CEC_TX_TIMING_0_REG 0x24 67 #define CEC_TX_TIMING_1_REG 0x28 68 #define CEC_TX_TIMING_2_REG 0x2c 69 70 #define CEC_INT_STAT_REG 0x30 71 #define CEC_INT_MASK_REG 0x34 72 #define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_L2H __BIT(14) 73 #define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_H2L __BIT(13) 74 #define CEC_INT_RX_BUS_ERROR_DETECTED __BIT(12) 75 #define CEC_INT_RX_BUS_ANOMALY_DETECTED __BIT(11) 76 #define CEC_INT_RX_START_BIT_DETECTED __BIT(10) 77 #define CEC_INT_RX_REGISTER_OVERRUN __BIT(9) 78 #define CEC_INT_RX_REGISTER_FULL __BIT(8) 79 #define CEC_INT_TX_FRAME_TRANSMITTED __BIT(5) 80 #define CEC_INT_TX_BUS_ANOMALY_DETECTED __BIT(4) 81 #define CEC_INT_TX_ARBITRATION_FAILED __BIT(3) 82 #define CEC_INT_TX_FRAME_OR_BLOCK_NAKD __BIT(2) 83 #define CEC_INT_TX_REGISTER_UNDERRUN __BIT(1) 84 #define CEC_INT_TX_REGISTER_EMPTY __BIT(0) 85 86 #define CEC_HW_DEBUG_RX_REG 0x38 87 #define CEC_HW_DEBUG_TX_REG 0x3c 88 #define CEC_HW_SPARE_0_REG 0x40 89 90 #endif /* _ARM_TEGRA_CECREG_H */ 91