1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This defines functionality used to emit comments about X86 instructions to 10 // an output stream for -fverbose-asm. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstComments.h" 15 #include "X86ATTInstPrinter.h" 16 #include "X86BaseInfo.h" 17 #include "X86MCTargetDesc.h" 18 #include "X86ShuffleDecode.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/Support/raw_ostream.h" 22 #include <string_view> 23 24 using namespace llvm; 25 26 #define CASE_SSE_INS_COMMON(Inst, src) \ 27 case X86::Inst##src: 28 29 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 30 case X86::V##Inst##Suffix##src: 31 32 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 33 case X86::V##Inst##Suffix##src##k: 34 35 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \ 36 case X86::V##Inst##Suffix##src##kz: 37 38 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \ 39 CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 40 CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 41 CASE_MASKZ_INS_COMMON(Inst, Suffix, src) 42 43 #define CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \ 44 case X86::V##Inst##Suffix##src##k_Int: 45 46 #define CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src) \ 47 case X86::V##Inst##Suffix##src##kz_Int: 48 49 #define CASE_AVX512_INS_COMMON_INT(Inst, Suffix, src) \ 50 CASE_AVX_INS_COMMON(Inst, Suffix, src##_Int) \ 51 CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \ 52 CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src) 53 54 #define CASE_FPCLASS_PACKED(Inst, src) \ 55 CASE_AVX_INS_COMMON(Inst, Z, src##i) \ 56 CASE_AVX_INS_COMMON(Inst, Z256, src##i) \ 57 CASE_AVX_INS_COMMON(Inst, Z128, src##i) \ 58 CASE_MASK_INS_COMMON(Inst, Z, src##i) 59 60 #define CASE_FPCLASS_PACKED_MEM(Inst) \ 61 CASE_FPCLASS_PACKED(Inst, m) \ 62 CASE_FPCLASS_PACKED(Inst, mb) 63 64 #define CASE_FPCLASS_SCALAR(Inst, src) \ 65 CASE_AVX_INS_COMMON(Inst, Z, src##i) \ 66 CASE_MASK_INS_COMMON(Inst, Z, src##i) 67 68 #define CASE_PTERNLOG(Inst, src) \ 69 CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \ 70 CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \ 71 CASE_AVX512_INS_COMMON(Inst, Z128, r##src##i) 72 73 #define CASE_MOVDUP(Inst, src) \ 74 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 75 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 76 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 77 CASE_AVX_INS_COMMON(Inst, , r##src) \ 78 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 79 CASE_SSE_INS_COMMON(Inst, r##src) 80 81 #define CASE_MASK_MOVDUP(Inst, src) \ 82 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 83 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 84 CASE_MASK_INS_COMMON(Inst, Z128, r##src) 85 86 #define CASE_MASKZ_MOVDUP(Inst, src) \ 87 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ 88 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ 89 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) 90 91 #define CASE_PMOVZX(Inst, src) \ 92 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 93 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 94 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 95 CASE_AVX_INS_COMMON(Inst, , r##src) \ 96 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 97 CASE_SSE_INS_COMMON(Inst, r##src) 98 99 #define CASE_UNPCK(Inst, src) \ 100 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 101 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 102 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 103 CASE_AVX_INS_COMMON(Inst, , r##src) \ 104 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 105 CASE_SSE_INS_COMMON(Inst, r##src) 106 107 #define CASE_MASK_UNPCK(Inst, src) \ 108 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 109 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 110 CASE_MASK_INS_COMMON(Inst, Z128, r##src) 111 112 #define CASE_MASKZ_UNPCK(Inst, src) \ 113 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ 114 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ 115 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) 116 117 #define CASE_SHUF(Inst, suf) \ 118 CASE_AVX512_INS_COMMON(Inst, Z, suf) \ 119 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ 120 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \ 121 CASE_AVX_INS_COMMON(Inst, , suf) \ 122 CASE_AVX_INS_COMMON(Inst, Y, suf) \ 123 CASE_SSE_INS_COMMON(Inst, suf) 124 125 #define CASE_MASK_SHUF(Inst, src) \ 126 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ 127 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ 128 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) 129 130 #define CASE_MASKZ_SHUF(Inst, src) \ 131 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \ 132 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \ 133 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i) 134 135 #define CASE_VPERMILPI(Inst, src) \ 136 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ 137 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ 138 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \ 139 CASE_AVX_INS_COMMON(Inst, , src##i) \ 140 CASE_AVX_INS_COMMON(Inst, Y, src##i) 141 142 #define CASE_MASK_VPERMILPI(Inst, src) \ 143 CASE_MASK_INS_COMMON(Inst, Z, src##i) \ 144 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ 145 CASE_MASK_INS_COMMON(Inst, Z128, src##i) 146 147 #define CASE_MASKZ_VPERMILPI(Inst, src) \ 148 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ 149 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \ 150 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i) 151 152 #define CASE_VPERM(Inst, src) \ 153 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ 154 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ 155 CASE_AVX_INS_COMMON(Inst, Y, src##i) 156 157 #define CASE_MASK_VPERM(Inst, src) \ 158 CASE_MASK_INS_COMMON(Inst, Z, src##i) \ 159 CASE_MASK_INS_COMMON(Inst, Z256, src##i) 160 161 #define CASE_MASKZ_VPERM(Inst, src) \ 162 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ 163 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) 164 165 #define CASE_VSHUF(Inst, src) \ 166 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 167 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 168 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 169 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 170 171 #define CASE_MASK_VSHUF(Inst, src) \ 172 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 173 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 174 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 175 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 176 177 #define CASE_MASKZ_VSHUF(Inst, src) \ 178 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 179 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 180 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 181 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 182 183 #define CASE_AVX512_FMA(Inst, suf) \ 184 CASE_AVX512_INS_COMMON(Inst, Z, suf) \ 185 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ 186 CASE_AVX512_INS_COMMON(Inst, Z128, suf) 187 188 #define CASE_FMA(Inst, suf) \ 189 CASE_AVX512_FMA(Inst, suf) \ 190 CASE_AVX_INS_COMMON(Inst, , suf) \ 191 CASE_AVX_INS_COMMON(Inst, Y, suf) 192 193 #define CASE_FMA_PACKED_REG(Inst) \ 194 CASE_FMA(Inst##PD, r) \ 195 CASE_FMA(Inst##PS, r) 196 197 #define CASE_FMA_PACKED_MEM(Inst) \ 198 CASE_FMA(Inst##PD, m) \ 199 CASE_FMA(Inst##PS, m) \ 200 CASE_AVX512_FMA(Inst##PD, mb) \ 201 CASE_AVX512_FMA(Inst##PS, mb) 202 203 #define CASE_FMA_SCALAR_REG(Inst) \ 204 CASE_AVX_INS_COMMON(Inst##SD, , r) \ 205 CASE_AVX_INS_COMMON(Inst##SS, , r) \ 206 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \ 207 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \ 208 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \ 209 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \ 210 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, r) \ 211 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, r) 212 213 #define CASE_FMA_SCALAR_MEM(Inst) \ 214 CASE_AVX_INS_COMMON(Inst##SD, , m) \ 215 CASE_AVX_INS_COMMON(Inst##SS, , m) \ 216 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \ 217 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \ 218 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \ 219 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \ 220 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, m) \ 221 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, m) 222 223 #define CASE_FMA4(Inst, suf) \ 224 CASE_AVX_INS_COMMON(Inst, 4, suf) \ 225 CASE_AVX_INS_COMMON(Inst, 4Y, suf) 226 227 #define CASE_FMA4_PACKED_RR(Inst) \ 228 CASE_FMA4(Inst##PD, rr) \ 229 CASE_FMA4(Inst##PS, rr) 230 231 #define CASE_FMA4_PACKED_RM(Inst) \ 232 CASE_FMA4(Inst##PD, rm) \ 233 CASE_FMA4(Inst##PS, rm) 234 235 #define CASE_FMA4_PACKED_MR(Inst) \ 236 CASE_FMA4(Inst##PD, mr) \ 237 CASE_FMA4(Inst##PS, mr) 238 239 #define CASE_FMA4_SCALAR_RR(Inst) \ 240 CASE_AVX_INS_COMMON(Inst##SD4, , rr) \ 241 CASE_AVX_INS_COMMON(Inst##SS4, , rr) \ 242 CASE_AVX_INS_COMMON(Inst##SD4, , rr_Int) \ 243 CASE_AVX_INS_COMMON(Inst##SS4, , rr_Int) 244 245 #define CASE_FMA4_SCALAR_RM(Inst) \ 246 CASE_AVX_INS_COMMON(Inst##SD4, , rm) \ 247 CASE_AVX_INS_COMMON(Inst##SS4, , rm) \ 248 CASE_AVX_INS_COMMON(Inst##SD4, , rm_Int) \ 249 CASE_AVX_INS_COMMON(Inst##SS4, , rm_Int) 250 251 #define CASE_FMA4_SCALAR_MR(Inst) \ 252 CASE_AVX_INS_COMMON(Inst##SD4, , mr) \ 253 CASE_AVX_INS_COMMON(Inst##SS4, , mr) \ 254 CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \ 255 CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int) 256 257 static unsigned getVectorRegSize(MCRegister Reg) { 258 if (X86II::isZMMReg(Reg)) 259 return 512; 260 if (X86II::isYMMReg(Reg)) 261 return 256; 262 if (X86II::isXMMReg(Reg)) 263 return 128; 264 if (Reg >= X86::MM0 && Reg <= X86::MM7) 265 return 64; 266 267 llvm_unreachable("Unknown vector reg!"); 268 } 269 270 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, 271 unsigned OperandIndex) { 272 MCRegister OpReg = MI->getOperand(OperandIndex).getReg(); 273 return getVectorRegSize(OpReg) / ScalarSize; 274 } 275 276 static const char *getRegName(MCRegister Reg) { 277 return X86ATTInstPrinter::getRegisterName(Reg); 278 } 279 280 /// Wraps the destination register name with AVX512 mask/maskz filtering. 281 static void printMasking(raw_ostream &OS, const MCInst *MI, 282 const MCInstrInfo &MCII) { 283 const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); 284 uint64_t TSFlags = Desc.TSFlags; 285 286 if (!(TSFlags & X86II::EVEX_K)) 287 return; 288 289 bool MaskWithZero = (TSFlags & X86II::EVEX_Z); 290 unsigned MaskOp = Desc.getNumDefs(); 291 292 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) 293 ++MaskOp; 294 295 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); 296 297 // MASK: zmmX {%kY} 298 OS << " {%" << MaskRegName << "}"; 299 300 // MASKZ: zmmX {%kY} {z} 301 if (MaskWithZero) 302 OS << " {z}"; 303 } 304 305 static bool printFMAComments(const MCInst *MI, raw_ostream &OS, 306 const MCInstrInfo &MCII) { 307 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr; 308 unsigned NumOperands = MI->getNumOperands(); 309 bool RegForm = false; 310 bool Negate = false; 311 StringRef AccStr = "+"; 312 313 // The operands for FMA3 instructions without rounding fall into two forms: 314 // dest, src1, src2, src3 315 // dest, src1, mask, src2, src3 316 // Where src3 is either a register or 5 memory address operands. So to find 317 // dest and src1 we can index from the front. To find src2 and src3 we can 318 // index from the end by taking into account memory vs register form when 319 // finding src2. 320 321 // The operands for FMA4 instructions: 322 // dest, src1, src2, src3 323 // Where src2 OR src3 are either a register or 5 memory address operands. So 324 // to find dest and src1 we can index from the front, src2 (reg/mem) follows 325 // and then src3 (reg) will be at the end. 326 327 switch (MI->getOpcode()) { 328 default: 329 return false; 330 331 CASE_FMA4_PACKED_RR(FMADD) 332 CASE_FMA4_SCALAR_RR(FMADD) 333 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 334 [[fallthrough]]; 335 CASE_FMA4_PACKED_RM(FMADD) 336 CASE_FMA4_SCALAR_RM(FMADD) 337 Mul2Name = getRegName(MI->getOperand(2).getReg()); 338 Mul1Name = getRegName(MI->getOperand(1).getReg()); 339 break; 340 CASE_FMA4_PACKED_MR(FMADD) 341 CASE_FMA4_SCALAR_MR(FMADD) 342 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 343 Mul1Name = getRegName(MI->getOperand(1).getReg()); 344 break; 345 346 CASE_FMA4_PACKED_RR(FMSUB) 347 CASE_FMA4_SCALAR_RR(FMSUB) 348 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 349 [[fallthrough]]; 350 CASE_FMA4_PACKED_RM(FMSUB) 351 CASE_FMA4_SCALAR_RM(FMSUB) 352 Mul2Name = getRegName(MI->getOperand(2).getReg()); 353 Mul1Name = getRegName(MI->getOperand(1).getReg()); 354 AccStr = "-"; 355 break; 356 CASE_FMA4_PACKED_MR(FMSUB) 357 CASE_FMA4_SCALAR_MR(FMSUB) 358 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 359 Mul1Name = getRegName(MI->getOperand(1).getReg()); 360 AccStr = "-"; 361 break; 362 363 CASE_FMA4_PACKED_RR(FNMADD) 364 CASE_FMA4_SCALAR_RR(FNMADD) 365 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 366 [[fallthrough]]; 367 CASE_FMA4_PACKED_RM(FNMADD) 368 CASE_FMA4_SCALAR_RM(FNMADD) 369 Mul2Name = getRegName(MI->getOperand(2).getReg()); 370 Mul1Name = getRegName(MI->getOperand(1).getReg()); 371 Negate = true; 372 break; 373 CASE_FMA4_PACKED_MR(FNMADD) 374 CASE_FMA4_SCALAR_MR(FNMADD) 375 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 376 Mul1Name = getRegName(MI->getOperand(1).getReg()); 377 Negate = true; 378 break; 379 380 CASE_FMA4_PACKED_RR(FNMSUB) 381 CASE_FMA4_SCALAR_RR(FNMSUB) 382 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 383 [[fallthrough]]; 384 CASE_FMA4_PACKED_RM(FNMSUB) 385 CASE_FMA4_SCALAR_RM(FNMSUB) 386 Mul2Name = getRegName(MI->getOperand(2).getReg()); 387 Mul1Name = getRegName(MI->getOperand(1).getReg()); 388 AccStr = "-"; 389 Negate = true; 390 break; 391 CASE_FMA4_PACKED_MR(FNMSUB) 392 CASE_FMA4_SCALAR_MR(FNMSUB) 393 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 394 Mul1Name = getRegName(MI->getOperand(1).getReg()); 395 AccStr = "-"; 396 Negate = true; 397 break; 398 399 CASE_FMA4_PACKED_RR(FMADDSUB) 400 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 401 [[fallthrough]]; 402 CASE_FMA4_PACKED_RM(FMADDSUB) 403 Mul2Name = getRegName(MI->getOperand(2).getReg()); 404 Mul1Name = getRegName(MI->getOperand(1).getReg()); 405 AccStr = "+/-"; 406 break; 407 CASE_FMA4_PACKED_MR(FMADDSUB) 408 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 409 Mul1Name = getRegName(MI->getOperand(1).getReg()); 410 AccStr = "+/-"; 411 break; 412 413 CASE_FMA4_PACKED_RR(FMSUBADD) 414 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 415 [[fallthrough]]; 416 CASE_FMA4_PACKED_RM(FMSUBADD) 417 Mul2Name = getRegName(MI->getOperand(2).getReg()); 418 Mul1Name = getRegName(MI->getOperand(1).getReg()); 419 AccStr = "-/+"; 420 break; 421 CASE_FMA4_PACKED_MR(FMSUBADD) 422 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 423 Mul1Name = getRegName(MI->getOperand(1).getReg()); 424 AccStr = "-/+"; 425 break; 426 427 CASE_FMA_PACKED_REG(FMADD132) 428 CASE_FMA_SCALAR_REG(FMADD132) 429 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 430 RegForm = true; 431 [[fallthrough]]; 432 CASE_FMA_PACKED_MEM(FMADD132) 433 CASE_FMA_SCALAR_MEM(FMADD132) 434 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 435 Mul1Name = getRegName(MI->getOperand(1).getReg()); 436 break; 437 438 CASE_FMA_PACKED_REG(FMADD213) 439 CASE_FMA_SCALAR_REG(FMADD213) 440 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 441 RegForm = true; 442 [[fallthrough]]; 443 CASE_FMA_PACKED_MEM(FMADD213) 444 CASE_FMA_SCALAR_MEM(FMADD213) 445 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 446 Mul2Name = getRegName(MI->getOperand(1).getReg()); 447 break; 448 449 CASE_FMA_PACKED_REG(FMADD231) 450 CASE_FMA_SCALAR_REG(FMADD231) 451 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 452 RegForm = true; 453 [[fallthrough]]; 454 CASE_FMA_PACKED_MEM(FMADD231) 455 CASE_FMA_SCALAR_MEM(FMADD231) 456 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 457 AccName = getRegName(MI->getOperand(1).getReg()); 458 break; 459 460 CASE_FMA_PACKED_REG(FMSUB132) 461 CASE_FMA_SCALAR_REG(FMSUB132) 462 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 463 RegForm = true; 464 [[fallthrough]]; 465 CASE_FMA_PACKED_MEM(FMSUB132) 466 CASE_FMA_SCALAR_MEM(FMSUB132) 467 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 468 Mul1Name = getRegName(MI->getOperand(1).getReg()); 469 AccStr = "-"; 470 break; 471 472 CASE_FMA_PACKED_REG(FMSUB213) 473 CASE_FMA_SCALAR_REG(FMSUB213) 474 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 475 RegForm = true; 476 [[fallthrough]]; 477 CASE_FMA_PACKED_MEM(FMSUB213) 478 CASE_FMA_SCALAR_MEM(FMSUB213) 479 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 480 Mul2Name = getRegName(MI->getOperand(1).getReg()); 481 AccStr = "-"; 482 break; 483 484 CASE_FMA_PACKED_REG(FMSUB231) 485 CASE_FMA_SCALAR_REG(FMSUB231) 486 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 487 RegForm = true; 488 [[fallthrough]]; 489 CASE_FMA_PACKED_MEM(FMSUB231) 490 CASE_FMA_SCALAR_MEM(FMSUB231) 491 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 492 AccName = getRegName(MI->getOperand(1).getReg()); 493 AccStr = "-"; 494 break; 495 496 CASE_FMA_PACKED_REG(FNMADD132) 497 CASE_FMA_SCALAR_REG(FNMADD132) 498 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 499 RegForm = true; 500 [[fallthrough]]; 501 CASE_FMA_PACKED_MEM(FNMADD132) 502 CASE_FMA_SCALAR_MEM(FNMADD132) 503 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 504 Mul1Name = getRegName(MI->getOperand(1).getReg()); 505 Negate = true; 506 break; 507 508 CASE_FMA_PACKED_REG(FNMADD213) 509 CASE_FMA_SCALAR_REG(FNMADD213) 510 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 511 RegForm = true; 512 [[fallthrough]]; 513 CASE_FMA_PACKED_MEM(FNMADD213) 514 CASE_FMA_SCALAR_MEM(FNMADD213) 515 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 516 Mul2Name = getRegName(MI->getOperand(1).getReg()); 517 Negate = true; 518 break; 519 520 CASE_FMA_PACKED_REG(FNMADD231) 521 CASE_FMA_SCALAR_REG(FNMADD231) 522 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 523 RegForm = true; 524 [[fallthrough]]; 525 CASE_FMA_PACKED_MEM(FNMADD231) 526 CASE_FMA_SCALAR_MEM(FNMADD231) 527 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 528 AccName = getRegName(MI->getOperand(1).getReg()); 529 Negate = true; 530 break; 531 532 CASE_FMA_PACKED_REG(FNMSUB132) 533 CASE_FMA_SCALAR_REG(FNMSUB132) 534 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 535 RegForm = true; 536 [[fallthrough]]; 537 CASE_FMA_PACKED_MEM(FNMSUB132) 538 CASE_FMA_SCALAR_MEM(FNMSUB132) 539 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 540 Mul1Name = getRegName(MI->getOperand(1).getReg()); 541 AccStr = "-"; 542 Negate = true; 543 break; 544 545 CASE_FMA_PACKED_REG(FNMSUB213) 546 CASE_FMA_SCALAR_REG(FNMSUB213) 547 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 548 RegForm = true; 549 [[fallthrough]]; 550 CASE_FMA_PACKED_MEM(FNMSUB213) 551 CASE_FMA_SCALAR_MEM(FNMSUB213) 552 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 553 Mul2Name = getRegName(MI->getOperand(1).getReg()); 554 AccStr = "-"; 555 Negate = true; 556 break; 557 558 CASE_FMA_PACKED_REG(FNMSUB231) 559 CASE_FMA_SCALAR_REG(FNMSUB231) 560 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 561 RegForm = true; 562 [[fallthrough]]; 563 CASE_FMA_PACKED_MEM(FNMSUB231) 564 CASE_FMA_SCALAR_MEM(FNMSUB231) 565 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 566 AccName = getRegName(MI->getOperand(1).getReg()); 567 AccStr = "-"; 568 Negate = true; 569 break; 570 571 CASE_FMA_PACKED_REG(FMADDSUB132) 572 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 573 RegForm = true; 574 [[fallthrough]]; 575 CASE_FMA_PACKED_MEM(FMADDSUB132) 576 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 577 Mul1Name = getRegName(MI->getOperand(1).getReg()); 578 AccStr = "+/-"; 579 break; 580 581 CASE_FMA_PACKED_REG(FMADDSUB213) 582 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 583 RegForm = true; 584 [[fallthrough]]; 585 CASE_FMA_PACKED_MEM(FMADDSUB213) 586 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 587 Mul2Name = getRegName(MI->getOperand(1).getReg()); 588 AccStr = "+/-"; 589 break; 590 591 CASE_FMA_PACKED_REG(FMADDSUB231) 592 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 593 RegForm = true; 594 [[fallthrough]]; 595 CASE_FMA_PACKED_MEM(FMADDSUB231) 596 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 597 AccName = getRegName(MI->getOperand(1).getReg()); 598 AccStr = "+/-"; 599 break; 600 601 CASE_FMA_PACKED_REG(FMSUBADD132) 602 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 603 RegForm = true; 604 [[fallthrough]]; 605 CASE_FMA_PACKED_MEM(FMSUBADD132) 606 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 607 Mul1Name = getRegName(MI->getOperand(1).getReg()); 608 AccStr = "-/+"; 609 break; 610 611 CASE_FMA_PACKED_REG(FMSUBADD213) 612 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 613 RegForm = true; 614 [[fallthrough]]; 615 CASE_FMA_PACKED_MEM(FMSUBADD213) 616 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 617 Mul2Name = getRegName(MI->getOperand(1).getReg()); 618 AccStr = "-/+"; 619 break; 620 621 CASE_FMA_PACKED_REG(FMSUBADD231) 622 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 623 RegForm = true; 624 [[fallthrough]]; 625 CASE_FMA_PACKED_MEM(FMSUBADD231) 626 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 627 AccName = getRegName(MI->getOperand(1).getReg()); 628 AccStr = "-/+"; 629 break; 630 } 631 632 const char *DestName = getRegName(MI->getOperand(0).getReg()); 633 634 if (!Mul1Name) Mul1Name = "mem"; 635 if (!Mul2Name) Mul2Name = "mem"; 636 if (!AccName) AccName = "mem"; 637 638 OS << DestName; 639 printMasking(OS, MI, MCII); 640 OS << " = "; 641 642 if (Negate) 643 OS << '-'; 644 645 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' ' 646 << AccName << '\n'; 647 648 return true; 649 } 650 651 // This table is indexed by the imm8 binary function specified in a 652 // vpternlog{d,q} instruction. The symbols {a,b,c} correspond to the three 653 // inputs to the binary function. This table was taken from 654 // https://gist.github.com/dougallj/81a80cd381988466c4e1c4889ecac95b#file-2-x86-base-txt 655 // with slight massaging. 656 constexpr StringLiteral TernlogFunctions[] = { 657 "0", 658 "~(a | b | c)", 659 "c & ~(a | b)", 660 "~(a | b)", 661 "b & ~(a | c)", 662 "~(a | c)", 663 "~a & (b ^ c)", 664 "~(a | (b & c))", 665 "b & c & ~a", 666 "~(a | (b ^ c))", 667 "c & ~a", 668 "~a & (c | ~b)", 669 "b & ~a", 670 "~a & (b | ~c)", 671 "~a & (b | c)", 672 "~a", 673 "a & ~(b | c)", 674 "~(b | c)", 675 "~b & (a ^ c)", 676 "~((a & c) | b)", 677 "~c & (a ^ b)", 678 "~((a & b) | c)", 679 "a ^ ((a & b) | (b ^ c))", 680 "(a & (b ^ c)) ^ ~(b & c)", 681 "(a ^ b) & (a ^ c)", 682 "~((a & b) | (b ^ c))", 683 "a ^ ((a & b) | c)", 684 "(a & c) ^ (c | ~b)", 685 "a ^ ((a & c) | b)", 686 "(a & b) ^ (b | ~c)", 687 "a ^ (b | c)", 688 "~(a & (b | c))", 689 "a & c & ~b", 690 "~(b | (a ^ c))", 691 "c & ~b", 692 "~b & (c | ~a)", 693 "(a ^ b) & (b ^ c)", 694 "~((a & b) | (a ^ c))", 695 "b ^ ((a & b) | c)", 696 "(b & c) ^ (c | ~a)", 697 "c & (a ^ b)", 698 "(a | b) ^ ((a & b) | ~c)", 699 "c & ~(a & b)", 700 "(c & (a ^ b)) | ~(a | b)", 701 "(b | c) & (a ^ b)", 702 "a ^ (b | ~c)", 703 "(a & b) ^ (b | c)", 704 "(c & ~b) | ~a", 705 "a & ~b", 706 "~b & (a | ~c)", 707 "~b & (a | c)", 708 "~b", 709 "b ^ (a | (b & c))", 710 "(a & b) ^ (a | ~c)", 711 "b ^ (a | c)", 712 "~(b & (a | c))", 713 "(a | c) & (a ^ b)", 714 "b ^ (a | ~c)", 715 "(a & b) ^ (a | c)", 716 "(c & ~a) | ~b", 717 "a ^ b", 718 "~(a | c) | (a ^ b)", 719 "(c & ~a) | (a ^ b)", 720 "~(a & b)", 721 "a & b & ~c", 722 "~(c | (a ^ b))", 723 "(a ^ c) & (b ^ c)", 724 "~((a & c) | (a ^ b))", 725 "b & ~c", 726 "~c & (b | ~a)", 727 "c ^ ((a & c) | b)", 728 "(b & c) ^ (b | ~a)", 729 "b & (a ^ c)", 730 "(a | c) ^ ((a & c) | ~b)", 731 "(b | c) & (a ^ c)", 732 "a ^ (c | ~b)", 733 "b & ~(a & c)", 734 "(b & (a ^ c)) | ~(a | c)", 735 "(a & c) ^ (b | c)", 736 "(b & ~c) | ~a", 737 "a & ~c", 738 "~c & (a | ~b)", 739 "c ^ (a | (b & c))", 740 "(a & c) ^ (a | ~b)", 741 "~c & (a | b)", 742 "~c", 743 "c ^ (a | b)", 744 "~(c & (a | b))", 745 "(a | b) & (a ^ c)", 746 "c ^ (a | ~b)", 747 "a ^ c", 748 "~(a | b) | (a ^ c)", 749 "(a & c) ^ (a | b)", 750 "(b & ~a) | ~c", 751 "(b & ~a) | (a ^ c)", 752 "~(a & c)", 753 "a & (b ^ c)", 754 "~(b ^ c) ^ (a | (b & c))", 755 "(a | c) & (b ^ c)", 756 "b ^ (c | ~a)", 757 "(a | b) & (b ^ c)", 758 "c ^ (b | ~a)", 759 "b ^ c", 760 "~(a | b) | (b ^ c)", 761 "(a | b) & (c ^ (a & b))", 762 "b ^ c ^ ~a", 763 "c ^ (a & b)", 764 "~(a | b) | (c ^ (a & b))", 765 "b ^ (a & c)", 766 "~(a | c) | (b ^ (a & c))", 767 "(b & ~a) | (b ^ c)", 768 "~a | (b ^ c)", 769 "a & ~(b & c)", 770 "(a & (b ^ c)) | ~(b | c)", 771 "(b & c) ^ (a | c)", 772 "(a & ~c) | ~b", 773 "(b & c) ^ (a | b)", 774 "(a & ~b) | ~c", 775 "(a & ~b) | (b ^ c)", 776 "~(b & c)", 777 "a ^ (b & c)", 778 "~(b | c) | (a ^ (b & c))", 779 "(a & ~b) | (a ^ c)", 780 "~b | (a ^ c)", 781 "(a & ~c) | (a ^ b)", 782 "~c | (a ^ b)", 783 "(a ^ b) | (a ^ c)", 784 "~(a & b & c)", 785 "a & b & c", 786 "~((a ^ b) | (a ^ c))", 787 "c & ~(a ^ b)", 788 "~(a ^ b) & (c | ~a)", 789 "b & ~(a ^ c)", 790 "~(a ^ c) & (b | ~a)", 791 "(b | c) & (a ^ b ^ c)", 792 "(b & c) ^ ~a", 793 "b & c", 794 "~(b ^ c) & (b | ~a)", 795 "c & (b | ~a)", 796 "~((b & c) ^ (a | b))", 797 "b & (c | ~a)", 798 "~((b & c) ^ (a | c))", 799 "a ^ ((a ^ b) | (a ^ c))", 800 "(b & c) | ~a", 801 "a & ~(b ^ c)", 802 "~(b ^ c) & (a | ~b)", 803 "(a | c) & (a ^ b ^ c)", 804 "(a & c) ^ ~b", 805 "(a | b) & (a ^ b ^ c)", 806 "(a & b) ^ ~c", 807 "a ^ b ^ c", 808 "~(a | b) | (a ^ b ^ c)", 809 "~(b ^ c) & (a | b)", 810 "~(b ^ c)", 811 "c ^ (a & ~b)", 812 "~((a | b) & (b ^ c))", 813 "b ^ (a & ~c)", 814 "~((a | c) & (b ^ c))", 815 "(b & c) | (a ^ (b | c))", 816 "~(a & (b ^ c))", 817 "a & c", 818 "~(a ^ c) & (a | ~b)", 819 "c & (a | ~b)", 820 "~((a & c) ^ (a | b))", 821 "~(a ^ c) & (a | b)", 822 "~(a ^ c)", 823 "c ^ (b & ~a)", 824 "~((a | b) & (a ^ c))", 825 "c & (a | b)", 826 "~c ^ (a | b)", 827 "c", 828 "c | ~(a | b)", 829 "b ^ (a & (b ^ c))", 830 "(b & c) | ~(a ^ c)", 831 "(b & ~a) | c", 832 "c | ~a", 833 "a & (c | ~b)", 834 "~((a & c) ^ (b | c))", 835 "a ^ ((a ^ c) & (b ^ c))", 836 "(a & c) | ~b", 837 "a ^ (b & ~c)", 838 "~((b | c) & (a ^ c))", 839 "(a & c) | (a ^ b ^ c)", 840 "~(b & (a ^ c))", 841 "a ^ (b & (a ^ c))", 842 "(a & c) | ~(b ^ c)", 843 "(a & ~b) | c", 844 "c | ~b", 845 "(a & c) | (a ^ b)", 846 "~((a ^ c) & (b ^ c))", 847 "c | (a ^ b)", 848 "c | ~(a & b)", 849 "a & b", 850 "~(a ^ b) & (a | ~c)", 851 "~(a ^ b) & (a | c)", 852 "~(a ^ b)", 853 "b & (a | ~c)", 854 "~((a & b) ^ (a | c))", 855 "b ^ (c & ~a)", 856 "~((a | c) & (a ^ b))", 857 "b & (a | c)", 858 "~b ^ (a | c)", 859 "c ^ (a & (b ^ c))", 860 "(b & c) | ~(a ^ b)", 861 "b", 862 "b | ~(a | c)", 863 "(c & ~a) | b", 864 "b | ~a", 865 "a & (b | ~c)", 866 "~((a & b) ^ (b | c))", 867 "a ^ (c & ~b)", 868 "~((b | c) & (a ^ b))", 869 "a ^ ((a ^ b) & (b ^ c))", 870 "(a & b) | ~c", 871 "(a & b) | (a ^ b ^ c)", 872 "~(c & (a ^ b))", 873 "a ^ (c & (a ^ b))", 874 "(a & b) | ~(b ^ c)", 875 "(a & b) | (a ^ c)", 876 "~((a ^ b) & (b ^ c))", 877 "(a & ~c) | b", 878 "b | ~c", 879 "b | (a ^ c)", 880 "b | ~(a & c)", 881 "a & (b | c)", 882 "~a ^ (b | c)", 883 "c ^ (b & (a ^ c))", 884 "(a & c) | ~(a ^ b)", 885 "b ^ (c & (a ^ b))", 886 "(a & b) | ~(a ^ c)", 887 "(a & b) | (b ^ c)", 888 "~((a ^ b) & (a ^ c))", 889 "(a | b) & ((a & b) | c)", 890 "(a & b) | (b ^ c ^ ~a)", 891 "(a & b) | c", 892 "c | ~(a ^ b)", 893 "(a & c) | b", 894 "b | ~(a ^ c)", 895 "b | c", 896 "~a | b | c", 897 "a", 898 "a | ~(b | c)", 899 "a | (c & ~b)", 900 "a | ~b", 901 "a | (b & ~c)", 902 "a | ~c", 903 "a | (b ^ c)", 904 "a | ~(b & c)", 905 "a | (b & c)", 906 "a | ~(b ^ c)", 907 "a | c", 908 "~b | a | c", 909 "a | b", 910 "~c | a | b", 911 "a | b | c", 912 "-1", 913 }; 914 915 static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS, 916 const MCInstrInfo &MCII) { 917 unsigned NumOperands = MI->getNumOperands(); 918 919 int Src2Idx; 920 int Src3Idx; 921 switch (MI->getOpcode()) { 922 // dest, src1, src2, src3, tbl 923 // dest, src1, mask, src2, src3, tbl 924 CASE_PTERNLOG(PTERNLOGD, r) 925 CASE_PTERNLOG(PTERNLOGQ, r) 926 Src2Idx = NumOperands - 3; 927 Src3Idx = NumOperands - 2; 928 break; 929 930 // dest, src1, src2, memory, tbl 931 // dest, src1, mask, src2, memory, tbl 932 CASE_PTERNLOG(PTERNLOGD, m) 933 CASE_PTERNLOG(PTERNLOGQ, m) 934 CASE_PTERNLOG(PTERNLOGD, mb) 935 CASE_PTERNLOG(PTERNLOGQ, mb) 936 Src2Idx = NumOperands - 7; 937 Src3Idx = -1; 938 break; 939 940 default: 941 return false; 942 } 943 StringRef DestName = getRegName(MI->getOperand(0).getReg()); 944 StringRef Src1Name = getRegName(MI->getOperand(1).getReg()); 945 StringRef Src2Name = getRegName(MI->getOperand(Src2Idx).getReg()); 946 StringRef Src3Name = 947 Src3Idx != -1 ? getRegName(MI->getOperand(Src3Idx).getReg()) : "mem"; 948 uint8_t TruthTable = MI->getOperand(NumOperands - 1).getImm(); 949 950 StringRef SrcNames[] = {Src1Name, Src2Name, Src3Name}; 951 952 OS << DestName; 953 printMasking(OS, MI, MCII); 954 OS << " = "; 955 956 static_assert(std::size(TernlogFunctions) == 256); 957 std::string_view BooleanFunction = TernlogFunctions[TruthTable]; 958 959 while (!BooleanFunction.empty()) { 960 // Print the expression up to the next symbol. 961 size_t SymbolOffset = BooleanFunction.find_first_of("abc"); 962 OS << BooleanFunction.substr(0, SymbolOffset); 963 if (SymbolOffset == std::string_view::npos) { 964 // No more symbols, that means we just printed everything. 965 break; 966 } 967 // Let's replace {a,b,c} with Src{1,2,3}Name. 968 char Symbol = BooleanFunction[SymbolOffset]; 969 OS << SrcNames[Symbol - 'a']; 970 // Consume the part of the expression we handled. 971 BooleanFunction.remove_prefix(SymbolOffset + 1); 972 } 973 OS << '\n'; 974 return true; 975 } 976 977 static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS, 978 const MCInstrInfo &MCII) { 979 unsigned NumOperands = MI->getNumOperands(); 980 int SrcIdx; 981 switch (MI->getOpcode()) { 982 CASE_FPCLASS_PACKED(FPCLASSBF16, r) 983 CASE_FPCLASS_PACKED(FPCLASSPH, r) 984 CASE_FPCLASS_PACKED(FPCLASSPS, r) 985 CASE_FPCLASS_PACKED(FPCLASSPD, r) 986 CASE_FPCLASS_SCALAR(FPCLASSSH, r) 987 CASE_FPCLASS_SCALAR(FPCLASSSS, r) 988 CASE_FPCLASS_SCALAR(FPCLASSSD, r) { 989 SrcIdx = NumOperands - 2; 990 break; 991 } 992 CASE_FPCLASS_PACKED_MEM(FPCLASSBF16) 993 CASE_FPCLASS_PACKED_MEM(FPCLASSPH) 994 CASE_FPCLASS_PACKED_MEM(FPCLASSPS) 995 CASE_FPCLASS_PACKED_MEM(FPCLASSPD) 996 CASE_FPCLASS_SCALAR(FPCLASSSH, m) 997 CASE_FPCLASS_SCALAR(FPCLASSSS, m) 998 CASE_FPCLASS_SCALAR(FPCLASSSD, m) { 999 SrcIdx = -1; 1000 break; 1001 } 1002 default: 1003 return false; 1004 } 1005 StringRef DestName = getRegName(MI->getOperand(0).getReg()); 1006 StringRef SrcName = 1007 SrcIdx != -1 ? getRegName(MI->getOperand(SrcIdx).getReg()) : "mem"; 1008 1009 OS << DestName; 1010 printMasking(OS, MI, MCII); 1011 OS << " = "; 1012 1013 uint8_t Categories = MI->getOperand(NumOperands - 1).getImm(); 1014 if (Categories == 0) { 1015 OS << "false"; 1016 } else { 1017 static constexpr StringLiteral CategoryNames[] = { 1018 "QuietNaN", 1019 "PositiveZero", 1020 "NegativeZero", 1021 "PositiveInfinity", 1022 "NegativeInfinity", 1023 "Subnormal", 1024 "Negative", 1025 "SignalingNaN", 1026 }; 1027 bool Conjoin = false; 1028 for (size_t I = 0, E = std::size(CategoryNames); I != E; ++I) { 1029 if (Categories & (1 << I)) { 1030 if (Conjoin) 1031 OS << " | "; 1032 Conjoin = true; 1033 OS << "is" << CategoryNames[I] << '(' << SrcName << ')'; 1034 } 1035 } 1036 } 1037 OS << '\n'; 1038 return true; 1039 } 1040 1041 //===----------------------------------------------------------------------===// 1042 // Top Level Entrypoint 1043 //===----------------------------------------------------------------------===// 1044 1045 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints 1046 /// newline terminated strings to the specified string if desired. This 1047 /// information is shown in disassembly dumps when verbose assembly is enabled. 1048 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, 1049 const MCInstrInfo &MCII) { 1050 // If this is a shuffle operation, the switch should fill in this state. 1051 SmallVector<int, 8> ShuffleMask; 1052 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr; 1053 unsigned NumOperands = MI->getNumOperands(); 1054 bool RegForm = false; 1055 1056 if (printFMAComments(MI, OS, MCII)) 1057 return true; 1058 1059 if (printPTERNLOGComments(MI, OS, MCII)) 1060 return true; 1061 1062 if (printFPCLASSComments(MI, OS, MCII)) 1063 return true; 1064 1065 switch (MI->getOpcode()) { 1066 default: 1067 // Not an instruction for which we can decode comments. 1068 return false; 1069 1070 case X86::BLENDPDrri: 1071 case X86::VBLENDPDrri: 1072 case X86::VBLENDPDYrri: 1073 Src2Name = getRegName(MI->getOperand(2).getReg()); 1074 [[fallthrough]]; 1075 case X86::BLENDPDrmi: 1076 case X86::VBLENDPDrmi: 1077 case X86::VBLENDPDYrmi: 1078 if (MI->getOperand(NumOperands - 1).isImm()) 1079 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0), 1080 MI->getOperand(NumOperands - 1).getImm(), 1081 ShuffleMask); 1082 Src1Name = getRegName(MI->getOperand(1).getReg()); 1083 DestName = getRegName(MI->getOperand(0).getReg()); 1084 break; 1085 1086 case X86::BLENDPSrri: 1087 case X86::VBLENDPSrri: 1088 case X86::VBLENDPSYrri: 1089 Src2Name = getRegName(MI->getOperand(2).getReg()); 1090 [[fallthrough]]; 1091 case X86::BLENDPSrmi: 1092 case X86::VBLENDPSrmi: 1093 case X86::VBLENDPSYrmi: 1094 if (MI->getOperand(NumOperands - 1).isImm()) 1095 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0), 1096 MI->getOperand(NumOperands - 1).getImm(), 1097 ShuffleMask); 1098 Src1Name = getRegName(MI->getOperand(1).getReg()); 1099 DestName = getRegName(MI->getOperand(0).getReg()); 1100 break; 1101 1102 case X86::PBLENDWrri: 1103 case X86::VPBLENDWrri: 1104 case X86::VPBLENDWYrri: 1105 Src2Name = getRegName(MI->getOperand(2).getReg()); 1106 [[fallthrough]]; 1107 case X86::PBLENDWrmi: 1108 case X86::VPBLENDWrmi: 1109 case X86::VPBLENDWYrmi: 1110 if (MI->getOperand(NumOperands - 1).isImm()) 1111 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0), 1112 MI->getOperand(NumOperands - 1).getImm(), 1113 ShuffleMask); 1114 Src1Name = getRegName(MI->getOperand(1).getReg()); 1115 DestName = getRegName(MI->getOperand(0).getReg()); 1116 break; 1117 1118 case X86::VPBLENDDrri: 1119 case X86::VPBLENDDYrri: 1120 Src2Name = getRegName(MI->getOperand(2).getReg()); 1121 [[fallthrough]]; 1122 case X86::VPBLENDDrmi: 1123 case X86::VPBLENDDYrmi: 1124 if (MI->getOperand(NumOperands - 1).isImm()) 1125 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0), 1126 MI->getOperand(NumOperands - 1).getImm(), 1127 ShuffleMask); 1128 Src1Name = getRegName(MI->getOperand(1).getReg()); 1129 DestName = getRegName(MI->getOperand(0).getReg()); 1130 break; 1131 1132 case X86::INSERTPSrri: 1133 case X86::VINSERTPSrri: 1134 case X86::VINSERTPSZrri: 1135 Src2Name = getRegName(MI->getOperand(2).getReg()); 1136 DestName = getRegName(MI->getOperand(0).getReg()); 1137 Src1Name = getRegName(MI->getOperand(1).getReg()); 1138 if (MI->getOperand(NumOperands - 1).isImm()) 1139 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask, 1140 /*SrcIsMem=*/false); 1141 break; 1142 1143 case X86::INSERTPSrmi: 1144 case X86::VINSERTPSrmi: 1145 case X86::VINSERTPSZrmi: 1146 DestName = getRegName(MI->getOperand(0).getReg()); 1147 Src1Name = getRegName(MI->getOperand(1).getReg()); 1148 if (MI->getOperand(NumOperands - 1).isImm()) 1149 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask, 1150 /*SrcIsMem=*/true); 1151 break; 1152 1153 case X86::MOVLHPSrr: 1154 case X86::VMOVLHPSrr: 1155 case X86::VMOVLHPSZrr: 1156 Src2Name = getRegName(MI->getOperand(2).getReg()); 1157 Src1Name = getRegName(MI->getOperand(1).getReg()); 1158 DestName = getRegName(MI->getOperand(0).getReg()); 1159 DecodeMOVLHPSMask(2, ShuffleMask); 1160 break; 1161 1162 case X86::MOVHLPSrr: 1163 case X86::VMOVHLPSrr: 1164 case X86::VMOVHLPSZrr: 1165 Src2Name = getRegName(MI->getOperand(2).getReg()); 1166 Src1Name = getRegName(MI->getOperand(1).getReg()); 1167 DestName = getRegName(MI->getOperand(0).getReg()); 1168 DecodeMOVHLPSMask(2, ShuffleMask); 1169 break; 1170 1171 case X86::MOVHPDrm: 1172 case X86::VMOVHPDrm: 1173 case X86::VMOVHPDZ128rm: 1174 Src1Name = getRegName(MI->getOperand(1).getReg()); 1175 DestName = getRegName(MI->getOperand(0).getReg()); 1176 DecodeInsertElementMask(2, 1, 1, ShuffleMask); 1177 break; 1178 1179 case X86::MOVHPSrm: 1180 case X86::VMOVHPSrm: 1181 case X86::VMOVHPSZ128rm: 1182 Src1Name = getRegName(MI->getOperand(1).getReg()); 1183 DestName = getRegName(MI->getOperand(0).getReg()); 1184 DecodeInsertElementMask(4, 2, 2, ShuffleMask); 1185 break; 1186 1187 case X86::MOVLPDrm: 1188 case X86::VMOVLPDrm: 1189 case X86::VMOVLPDZ128rm: 1190 Src1Name = getRegName(MI->getOperand(1).getReg()); 1191 DestName = getRegName(MI->getOperand(0).getReg()); 1192 DecodeInsertElementMask(2, 0, 1, ShuffleMask); 1193 break; 1194 1195 case X86::MOVLPSrm: 1196 case X86::VMOVLPSrm: 1197 case X86::VMOVLPSZ128rm: 1198 Src1Name = getRegName(MI->getOperand(1).getReg()); 1199 DestName = getRegName(MI->getOperand(0).getReg()); 1200 DecodeInsertElementMask(4, 0, 2, ShuffleMask); 1201 break; 1202 1203 CASE_MOVDUP(MOVSLDUP, r) 1204 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1205 [[fallthrough]]; 1206 1207 CASE_MOVDUP(MOVSLDUP, m) 1208 DestName = getRegName(MI->getOperand(0).getReg()); 1209 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask); 1210 break; 1211 1212 CASE_MOVDUP(MOVSHDUP, r) 1213 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1214 [[fallthrough]]; 1215 1216 CASE_MOVDUP(MOVSHDUP, m) 1217 DestName = getRegName(MI->getOperand(0).getReg()); 1218 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask); 1219 break; 1220 1221 CASE_MOVDUP(MOVDDUP, r) 1222 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1223 [[fallthrough]]; 1224 1225 CASE_MOVDUP(MOVDDUP, m) 1226 DestName = getRegName(MI->getOperand(0).getReg()); 1227 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask); 1228 break; 1229 1230 case X86::PSLLDQri: 1231 case X86::VPSLLDQri: 1232 case X86::VPSLLDQYri: 1233 case X86::VPSLLDQZ128ri: 1234 case X86::VPSLLDQZ256ri: 1235 case X86::VPSLLDQZri: 1236 Src1Name = getRegName(MI->getOperand(1).getReg()); 1237 [[fallthrough]]; 1238 case X86::VPSLLDQZ128mi: 1239 case X86::VPSLLDQZ256mi: 1240 case X86::VPSLLDQZmi: 1241 DestName = getRegName(MI->getOperand(0).getReg()); 1242 if (MI->getOperand(NumOperands - 1).isImm()) 1243 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0), 1244 MI->getOperand(NumOperands - 1).getImm(), 1245 ShuffleMask); 1246 break; 1247 1248 case X86::PSRLDQri: 1249 case X86::VPSRLDQri: 1250 case X86::VPSRLDQYri: 1251 case X86::VPSRLDQZ128ri: 1252 case X86::VPSRLDQZ256ri: 1253 case X86::VPSRLDQZri: 1254 Src1Name = getRegName(MI->getOperand(1).getReg()); 1255 [[fallthrough]]; 1256 case X86::VPSRLDQZ128mi: 1257 case X86::VPSRLDQZ256mi: 1258 case X86::VPSRLDQZmi: 1259 DestName = getRegName(MI->getOperand(0).getReg()); 1260 if (MI->getOperand(NumOperands - 1).isImm()) 1261 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0), 1262 MI->getOperand(NumOperands - 1).getImm(), 1263 ShuffleMask); 1264 break; 1265 1266 CASE_SHUF(PALIGNR, rri) 1267 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1268 RegForm = true; 1269 [[fallthrough]]; 1270 1271 CASE_SHUF(PALIGNR, rmi) 1272 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1273 DestName = getRegName(MI->getOperand(0).getReg()); 1274 if (MI->getOperand(NumOperands - 1).isImm()) 1275 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0), 1276 MI->getOperand(NumOperands - 1).getImm(), 1277 ShuffleMask); 1278 break; 1279 1280 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri) 1281 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri) 1282 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri) 1283 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1284 RegForm = true; 1285 [[fallthrough]]; 1286 1287 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi) 1288 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi) 1289 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi) 1290 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1291 DestName = getRegName(MI->getOperand(0).getReg()); 1292 if (MI->getOperand(NumOperands - 1).isImm()) 1293 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0), 1294 MI->getOperand(NumOperands - 1).getImm(), 1295 ShuffleMask); 1296 break; 1297 1298 CASE_AVX512_INS_COMMON(ALIGND, Z, rri) 1299 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri) 1300 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri) 1301 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1302 RegForm = true; 1303 [[fallthrough]]; 1304 1305 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi) 1306 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi) 1307 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi) 1308 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1309 DestName = getRegName(MI->getOperand(0).getReg()); 1310 if (MI->getOperand(NumOperands - 1).isImm()) 1311 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0), 1312 MI->getOperand(NumOperands - 1).getImm(), 1313 ShuffleMask); 1314 break; 1315 1316 CASE_SHUF(PSHUFD, ri) 1317 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1318 [[fallthrough]]; 1319 1320 CASE_SHUF(PSHUFD, mi) 1321 DestName = getRegName(MI->getOperand(0).getReg()); 1322 if (MI->getOperand(NumOperands - 1).isImm()) 1323 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32, 1324 MI->getOperand(NumOperands - 1).getImm(), 1325 ShuffleMask); 1326 break; 1327 1328 CASE_SHUF(PSHUFHW, ri) 1329 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1330 [[fallthrough]]; 1331 1332 CASE_SHUF(PSHUFHW, mi) 1333 DestName = getRegName(MI->getOperand(0).getReg()); 1334 if (MI->getOperand(NumOperands - 1).isImm()) 1335 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0), 1336 MI->getOperand(NumOperands - 1).getImm(), 1337 ShuffleMask); 1338 break; 1339 1340 CASE_SHUF(PSHUFLW, ri) 1341 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1342 [[fallthrough]]; 1343 1344 CASE_SHUF(PSHUFLW, mi) 1345 DestName = getRegName(MI->getOperand(0).getReg()); 1346 if (MI->getOperand(NumOperands - 1).isImm()) 1347 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0), 1348 MI->getOperand(NumOperands - 1).getImm(), 1349 ShuffleMask); 1350 break; 1351 1352 case X86::MMX_PSHUFWri: 1353 Src1Name = getRegName(MI->getOperand(1).getReg()); 1354 [[fallthrough]]; 1355 1356 case X86::MMX_PSHUFWmi: 1357 DestName = getRegName(MI->getOperand(0).getReg()); 1358 if (MI->getOperand(NumOperands - 1).isImm()) 1359 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(), 1360 ShuffleMask); 1361 break; 1362 1363 case X86::PSWAPDrr: 1364 Src1Name = getRegName(MI->getOperand(1).getReg()); 1365 [[fallthrough]]; 1366 1367 case X86::PSWAPDrm: 1368 DestName = getRegName(MI->getOperand(0).getReg()); 1369 DecodePSWAPMask(2, ShuffleMask); 1370 break; 1371 1372 CASE_UNPCK(PUNPCKHBW, r) 1373 case X86::MMX_PUNPCKHBWrr: 1374 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1375 RegForm = true; 1376 [[fallthrough]]; 1377 1378 CASE_UNPCK(PUNPCKHBW, m) 1379 case X86::MMX_PUNPCKHBWrm: 1380 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1381 DestName = getRegName(MI->getOperand(0).getReg()); 1382 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask); 1383 break; 1384 1385 CASE_UNPCK(PUNPCKHWD, r) 1386 case X86::MMX_PUNPCKHWDrr: 1387 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1388 RegForm = true; 1389 [[fallthrough]]; 1390 1391 CASE_UNPCK(PUNPCKHWD, m) 1392 case X86::MMX_PUNPCKHWDrm: 1393 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1394 DestName = getRegName(MI->getOperand(0).getReg()); 1395 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask); 1396 break; 1397 1398 CASE_UNPCK(PUNPCKHDQ, r) 1399 case X86::MMX_PUNPCKHDQrr: 1400 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1401 RegForm = true; 1402 [[fallthrough]]; 1403 1404 CASE_UNPCK(PUNPCKHDQ, m) 1405 case X86::MMX_PUNPCKHDQrm: 1406 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1407 DestName = getRegName(MI->getOperand(0).getReg()); 1408 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); 1409 break; 1410 1411 CASE_UNPCK(PUNPCKHQDQ, r) 1412 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1413 RegForm = true; 1414 [[fallthrough]]; 1415 1416 CASE_UNPCK(PUNPCKHQDQ, m) 1417 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1418 DestName = getRegName(MI->getOperand(0).getReg()); 1419 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); 1420 break; 1421 1422 CASE_UNPCK(PUNPCKLBW, r) 1423 case X86::MMX_PUNPCKLBWrr: 1424 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1425 RegForm = true; 1426 [[fallthrough]]; 1427 1428 CASE_UNPCK(PUNPCKLBW, m) 1429 case X86::MMX_PUNPCKLBWrm: 1430 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1431 DestName = getRegName(MI->getOperand(0).getReg()); 1432 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask); 1433 break; 1434 1435 CASE_UNPCK(PUNPCKLWD, r) 1436 case X86::MMX_PUNPCKLWDrr: 1437 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1438 RegForm = true; 1439 [[fallthrough]]; 1440 1441 CASE_UNPCK(PUNPCKLWD, m) 1442 case X86::MMX_PUNPCKLWDrm: 1443 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1444 DestName = getRegName(MI->getOperand(0).getReg()); 1445 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask); 1446 break; 1447 1448 CASE_UNPCK(PUNPCKLDQ, r) 1449 case X86::MMX_PUNPCKLDQrr: 1450 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1451 RegForm = true; 1452 [[fallthrough]]; 1453 1454 CASE_UNPCK(PUNPCKLDQ, m) 1455 case X86::MMX_PUNPCKLDQrm: 1456 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1457 DestName = getRegName(MI->getOperand(0).getReg()); 1458 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); 1459 break; 1460 1461 CASE_UNPCK(PUNPCKLQDQ, r) 1462 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1463 RegForm = true; 1464 [[fallthrough]]; 1465 1466 CASE_UNPCK(PUNPCKLQDQ, m) 1467 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1468 DestName = getRegName(MI->getOperand(0).getReg()); 1469 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); 1470 break; 1471 1472 CASE_SHUF(SHUFPD, rri) 1473 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1474 RegForm = true; 1475 [[fallthrough]]; 1476 1477 CASE_SHUF(SHUFPD, rmi) 1478 if (MI->getOperand(NumOperands - 1).isImm()) 1479 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64, 1480 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); 1481 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1482 DestName = getRegName(MI->getOperand(0).getReg()); 1483 break; 1484 1485 CASE_SHUF(SHUFPS, rri) 1486 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1487 RegForm = true; 1488 [[fallthrough]]; 1489 1490 CASE_SHUF(SHUFPS, rmi) 1491 if (MI->getOperand(NumOperands - 1).isImm()) 1492 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32, 1493 MI->getOperand(NumOperands - 1).getImm(), 1494 ShuffleMask); 1495 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1496 DestName = getRegName(MI->getOperand(0).getReg()); 1497 break; 1498 1499 CASE_VSHUF(64X2, r) 1500 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1501 RegForm = true; 1502 [[fallthrough]]; 1503 1504 CASE_VSHUF(64X2, m) 1505 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64, 1506 MI->getOperand(NumOperands - 1).getImm(), 1507 ShuffleMask); 1508 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1509 DestName = getRegName(MI->getOperand(0).getReg()); 1510 break; 1511 1512 CASE_VSHUF(32X4, r) 1513 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1514 RegForm = true; 1515 [[fallthrough]]; 1516 1517 CASE_VSHUF(32X4, m) 1518 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32, 1519 MI->getOperand(NumOperands - 1).getImm(), 1520 ShuffleMask); 1521 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 1522 DestName = getRegName(MI->getOperand(0).getReg()); 1523 break; 1524 1525 CASE_UNPCK(UNPCKLPD, r) 1526 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1527 RegForm = true; 1528 [[fallthrough]]; 1529 1530 CASE_UNPCK(UNPCKLPD, m) 1531 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); 1532 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1533 DestName = getRegName(MI->getOperand(0).getReg()); 1534 break; 1535 1536 CASE_UNPCK(UNPCKLPS, r) 1537 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1538 RegForm = true; 1539 [[fallthrough]]; 1540 1541 CASE_UNPCK(UNPCKLPS, m) 1542 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); 1543 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1544 DestName = getRegName(MI->getOperand(0).getReg()); 1545 break; 1546 1547 CASE_UNPCK(UNPCKHPD, r) 1548 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1549 RegForm = true; 1550 [[fallthrough]]; 1551 1552 CASE_UNPCK(UNPCKHPD, m) 1553 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); 1554 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1555 DestName = getRegName(MI->getOperand(0).getReg()); 1556 break; 1557 1558 CASE_UNPCK(UNPCKHPS, r) 1559 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1560 RegForm = true; 1561 [[fallthrough]]; 1562 1563 CASE_UNPCK(UNPCKHPS, m) 1564 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); 1565 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 1566 DestName = getRegName(MI->getOperand(0).getReg()); 1567 break; 1568 1569 CASE_VPERMILPI(PERMILPS, r) 1570 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1571 [[fallthrough]]; 1572 1573 CASE_VPERMILPI(PERMILPS, m) 1574 if (MI->getOperand(NumOperands - 1).isImm()) 1575 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32, 1576 MI->getOperand(NumOperands - 1).getImm(), 1577 ShuffleMask); 1578 DestName = getRegName(MI->getOperand(0).getReg()); 1579 break; 1580 1581 CASE_VPERMILPI(PERMILPD, r) 1582 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1583 [[fallthrough]]; 1584 1585 CASE_VPERMILPI(PERMILPD, m) 1586 if (MI->getOperand(NumOperands - 1).isImm()) 1587 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64, 1588 MI->getOperand(NumOperands - 1).getImm(), 1589 ShuffleMask); 1590 DestName = getRegName(MI->getOperand(0).getReg()); 1591 break; 1592 1593 case X86::VPERM2F128rri: 1594 case X86::VPERM2I128rri: 1595 Src2Name = getRegName(MI->getOperand(2).getReg()); 1596 [[fallthrough]]; 1597 1598 case X86::VPERM2F128rmi: 1599 case X86::VPERM2I128rmi: 1600 // For instruction comments purpose, assume the 256-bit vector is v4i64. 1601 if (MI->getOperand(NumOperands - 1).isImm()) 1602 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(), 1603 ShuffleMask); 1604 Src1Name = getRegName(MI->getOperand(1).getReg()); 1605 DestName = getRegName(MI->getOperand(0).getReg()); 1606 break; 1607 1608 CASE_VPERM(PERMPD, r) 1609 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1610 [[fallthrough]]; 1611 1612 CASE_VPERM(PERMPD, m) 1613 if (MI->getOperand(NumOperands - 1).isImm()) 1614 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0), 1615 MI->getOperand(NumOperands - 1).getImm(), 1616 ShuffleMask); 1617 DestName = getRegName(MI->getOperand(0).getReg()); 1618 break; 1619 1620 CASE_VPERM(PERMQ, r) 1621 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 1622 [[fallthrough]]; 1623 1624 CASE_VPERM(PERMQ, m) 1625 if (MI->getOperand(NumOperands - 1).isImm()) 1626 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0), 1627 MI->getOperand(NumOperands - 1).getImm(), 1628 ShuffleMask); 1629 DestName = getRegName(MI->getOperand(0).getReg()); 1630 break; 1631 1632 case X86::MOVSDrr: 1633 case X86::VMOVSDrr: 1634 case X86::VMOVSDZrr: 1635 Src2Name = getRegName(MI->getOperand(2).getReg()); 1636 Src1Name = getRegName(MI->getOperand(1).getReg()); 1637 DecodeScalarMoveMask(2, false, ShuffleMask); 1638 DestName = getRegName(MI->getOperand(0).getReg()); 1639 break; 1640 1641 case X86::MOVSSrr: 1642 case X86::VMOVSSrr: 1643 case X86::VMOVSSZrr: 1644 Src2Name = getRegName(MI->getOperand(2).getReg()); 1645 Src1Name = getRegName(MI->getOperand(1).getReg()); 1646 DecodeScalarMoveMask(4, false, ShuffleMask); 1647 DestName = getRegName(MI->getOperand(0).getReg()); 1648 break; 1649 1650 case X86::MOVPQI2QIrr: 1651 case X86::MOVZPQILo2PQIrr: 1652 case X86::VMOVPQI2QIrr: 1653 case X86::VMOVPQI2QIZrr: 1654 case X86::VMOVZPQILo2PQIrr: 1655 case X86::VMOVZPQILo2PQIZrr: 1656 Src1Name = getRegName(MI->getOperand(1).getReg()); 1657 DecodeZeroMoveLowMask(2, ShuffleMask); 1658 DestName = getRegName(MI->getOperand(0).getReg()); 1659 break; 1660 1661 case X86::EXTRQI: 1662 if (MI->getOperand(2).isImm() && 1663 MI->getOperand(3).isImm()) 1664 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(), 1665 MI->getOperand(3).getImm(), ShuffleMask); 1666 1667 DestName = getRegName(MI->getOperand(0).getReg()); 1668 Src1Name = getRegName(MI->getOperand(1).getReg()); 1669 break; 1670 1671 case X86::INSERTQI: 1672 if (MI->getOperand(3).isImm() && 1673 MI->getOperand(4).isImm()) 1674 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(), 1675 MI->getOperand(4).getImm(), ShuffleMask); 1676 1677 DestName = getRegName(MI->getOperand(0).getReg()); 1678 Src1Name = getRegName(MI->getOperand(1).getReg()); 1679 Src2Name = getRegName(MI->getOperand(2).getReg()); 1680 break; 1681 1682 case X86::VBROADCASTF128rm: 1683 case X86::VBROADCASTI128rm: 1684 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z256, rm) 1685 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z256, rm) 1686 DecodeSubVectorBroadcast(4, 2, ShuffleMask); 1687 DestName = getRegName(MI->getOperand(0).getReg()); 1688 break; 1689 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z, rm) 1690 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z, rm) 1691 DecodeSubVectorBroadcast(8, 2, ShuffleMask); 1692 DestName = getRegName(MI->getOperand(0).getReg()); 1693 break; 1694 CASE_AVX512_INS_COMMON(BROADCASTF64X4, Z, rm) 1695 CASE_AVX512_INS_COMMON(BROADCASTI64X4, Z, rm) 1696 DecodeSubVectorBroadcast(8, 4, ShuffleMask); 1697 DestName = getRegName(MI->getOperand(0).getReg()); 1698 break; 1699 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm) 1700 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm) 1701 DecodeSubVectorBroadcast(8, 4, ShuffleMask); 1702 DestName = getRegName(MI->getOperand(0).getReg()); 1703 break; 1704 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z, rm) 1705 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z, rm) 1706 DecodeSubVectorBroadcast(16, 4, ShuffleMask); 1707 DestName = getRegName(MI->getOperand(0).getReg()); 1708 break; 1709 CASE_AVX512_INS_COMMON(BROADCASTF32X8, Z, rm) 1710 CASE_AVX512_INS_COMMON(BROADCASTI32X8, Z, rm) 1711 DecodeSubVectorBroadcast(16, 8, ShuffleMask); 1712 DestName = getRegName(MI->getOperand(0).getReg()); 1713 break; 1714 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rr) 1715 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1716 [[fallthrough]]; 1717 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rm) 1718 DecodeSubVectorBroadcast(4, 2, ShuffleMask); 1719 DestName = getRegName(MI->getOperand(0).getReg()); 1720 break; 1721 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rr) 1722 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rr) 1723 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1724 [[fallthrough]]; 1725 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rm) 1726 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rm) 1727 DecodeSubVectorBroadcast(8, 2, ShuffleMask); 1728 DestName = getRegName(MI->getOperand(0).getReg()); 1729 break; 1730 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rr) 1731 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rr) 1732 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1733 [[fallthrough]]; 1734 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rm) 1735 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rm) 1736 DecodeSubVectorBroadcast(16, 2, ShuffleMask); 1737 DestName = getRegName(MI->getOperand(0).getReg()); 1738 break; 1739 1740 CASE_PMOVZX(PMOVZXBW, r) 1741 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1742 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false, 1743 ShuffleMask); 1744 DestName = getRegName(MI->getOperand(0).getReg()); 1745 break; 1746 1747 CASE_PMOVZX(PMOVZXBD, r) 1748 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1749 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false, 1750 ShuffleMask); 1751 DestName = getRegName(MI->getOperand(0).getReg()); 1752 break; 1753 1754 CASE_PMOVZX(PMOVZXBQ, r) 1755 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1756 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false, 1757 ShuffleMask); 1758 DestName = getRegName(MI->getOperand(0).getReg()); 1759 break; 1760 1761 CASE_PMOVZX(PMOVZXWD, r) 1762 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1763 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false, 1764 ShuffleMask); 1765 DestName = getRegName(MI->getOperand(0).getReg()); 1766 break; 1767 1768 CASE_PMOVZX(PMOVZXWQ, r) 1769 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1770 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false, 1771 ShuffleMask); 1772 DestName = getRegName(MI->getOperand(0).getReg()); 1773 break; 1774 1775 CASE_PMOVZX(PMOVZXDQ, r) 1776 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 1777 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false, 1778 ShuffleMask); 1779 DestName = getRegName(MI->getOperand(0).getReg()); 1780 break; 1781 } 1782 1783 // The only comments we decode are shuffles, so give up if we were unable to 1784 // decode a shuffle mask. 1785 if (ShuffleMask.empty()) 1786 return false; 1787 1788 if (!DestName) DestName = Src1Name; 1789 if (DestName) { 1790 OS << DestName; 1791 printMasking(OS, MI, MCII); 1792 } else 1793 OS << "mem"; 1794 1795 OS << " = "; 1796 1797 // If the two sources are the same, canonicalize the input elements to be 1798 // from the first src so that we get larger element spans. 1799 if (Src1Name == Src2Name) { 1800 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 1801 if ((int)ShuffleMask[i] >= 0 && // Not sentinel. 1802 ShuffleMask[i] >= (int)e) // From second mask. 1803 ShuffleMask[i] -= e; 1804 } 1805 } 1806 1807 // The shuffle mask specifies which elements of the src1/src2 fill in the 1808 // destination, with a few sentinel values. Loop through and print them 1809 // out. 1810 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 1811 if (i != 0) 1812 OS << ','; 1813 if (ShuffleMask[i] == SM_SentinelZero) { 1814 OS << "zero"; 1815 continue; 1816 } 1817 1818 // Otherwise, it must come from src1 or src2. Print the span of elements 1819 // that comes from this src. 1820 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size(); 1821 const char *SrcName = isSrc1 ? Src1Name : Src2Name; 1822 OS << (SrcName ? SrcName : "mem") << '['; 1823 bool IsFirst = true; 1824 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero && 1825 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) { 1826 if (!IsFirst) 1827 OS << ','; 1828 else 1829 IsFirst = false; 1830 if (ShuffleMask[i] == SM_SentinelUndef) 1831 OS << "u"; 1832 else 1833 OS << ShuffleMask[i] % ShuffleMask.size(); 1834 ++i; 1835 } 1836 OS << ']'; 1837 --i; // For loop increments element #. 1838 } 1839 OS << '\n'; 1840 1841 // We successfully added a comment to this instruction. 1842 return true; 1843 } 1844