1/* 2 * mips 24k machine assist 3 */ 4#undef MASK 5#define MASK(w) ((1<<(w))-1) 6 7#define SP R29 8 9#define NOP NOR R0, R0, R0 10 11#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r 12 13/* a mips 24k erratum requires a NOP after; experience dictates EHB before */ 14#define ERET EHB; WORD $0x42000018; NOP 15 16#define RETURN RET; NOP 17 18/* 19 * R4000 instructions 20 */ 21#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16)) 22#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16)) 23 24/* new instructions in mips 24k (mips32r2) */ 25#define DI(rt) WORD $(0x41606000|((rt)<<16)) /* interrupts off */ 26#define EI(rt) WORD $(0x41606020|((rt)<<16)) /* interrupts on */ 27#define EHB WORD $0xc0 28/* jalr with hazard barrier, link in R22 */ 29#define JALRHB(r) WORD $(((r)<<21)|(22<<11)|(1<<10)|9); NOP 30/* jump register with hazard barrier */ 31#define JRHB(r) WORD $(((r)<<21)|(1<<10)|8); NOP 32#define MFC0(src,sel,dst) WORD $(0x40000000|((src)<<11)|((dst)<<16)|(sel)) 33#define MTC0(src,dst,sel) WORD $(0x40800000|((dst)<<11)|((src)<<16)|(sel)) 34#define MIPS24KNOP NOP /* for erratum #48 */ 35#define RDHWR(hwr, r) WORD $(0x7c00003b|((hwr)<<11)|((r)<<16)) 36#define SYNC WORD $0xf /* all sync barriers */ 37#define WAIT WORD $0x42000020 /* wait for interrupt */ 38 39/* all barriers, clears all hazards; clobbers r/Reg and R22 */ 40#define BARRIERS(r, Reg, label) \ 41 SYNC; EHB; MOVW $ret(SB), Reg; JALRHB(r) 42/* same but return to KSEG1 */ 43#define UBARRIERS(r, Reg, label) \ 44 SYNC; EHB; MOVW $ret(SB), Reg; OR $KSEG1, Reg; JALRHB(r) 45 46/* alternative definitions using labels */ 47#ifdef notdef 48/* all barriers, clears all hazards; clobbers r/Reg */ 49#define BARRIERS(r, Reg, label) \ 50 SYNC; EHB; \ 51 MOVW $label(SB), Reg; \ 52 JRHB(r); \ 53TEXT label(SB), $-4; \ 54 NOP 55#define UBARRIERS(r, Reg, label) \ 56 SYNC; EHB; \ 57 MOVW $label(SB), Reg; \ 58 OR $KSEG1, Reg; \ 59 JRHB(r); \ 60TEXT label(SB), $-4; \ 61 NOP 62#endif 63 64#define PUTC(c, r1, r2) CONST(PHYSCONS, r1); MOVW $(c), r2; MOVW r2, (r1); NOP 65 66/* 67 * cache manipulation 68 */ 69 70#define CACHE BREAK /* overloaded op-code */ 71 72#define PI R((0 /* primary I cache */ 73#define PD R((1 /* primary D cache */ 74#define TD R((2 /* tertiary I/D cache */ 75#define SD R((3 /* secondary combined I/D cache */ 76 77#define IWBI (0<<2))) /* index write-back invalidate */ 78#define ILT (1<<2))) /* index load tag */ 79#define IST (2<<2))) /* index store tag */ 80/* #define CDE (3<<2))) /* create dirty exclusive */ 81#define HINV (4<<2))) /* hit invalidate */ 82#define HWBI (5<<2))) /* hit write back invalidate */ 83#define HWB (6<<2))) /* hit write back */ 84/* #define HSV (7<<2))) /* hit set virtual */ 85