| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
429 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | Thumb2SizeReduction.cpp | 499 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
529 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
537 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
550 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| H A D | ARMBaseRegisterInfo.cpp | 660 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
672 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
701 Register BaseReg, in isFrameOffsetLegal()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 536 Register BaseReg, in isFrameOffsetLegal()
558 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
570 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| H A D | AArch64StorePairSuppress.cpp | 156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| H A D | AArch64LoadStoreOptimizer.cpp | 1238 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1533 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1835 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1891 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1968 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 51 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 270 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
335 BitVector &CandidateDestRegs) { in generateCodeTemplates()
395 BitVector &CandidateDestRegs) { in generateCodeTemplates()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86AsmPrinter.cpp | 288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| H A D | X86FixupLEAs.cpp | 384 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
569 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| H A D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 166 unsigned BaseReg = Base.getReg(); in is16BitMemOperand() local
183 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand() local
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand() local
389 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
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| H A D | X86IntelInstPrinter.cpp | 355 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| H A D | X86ATTInstPrinter.cpp | 398 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 374 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1463 Register BaseReg = MRI.createVirtualRegister(RC); in materializeFrameBaseRegister() local
1472 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
1497 Register BaseReg, in isFrameOffsetLegal()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 593 for (const SCEV *BaseReg : BaseRegs) in hasRegsUsedByUsesOtherThan() local
610 for (const SCEV *BaseReg : BaseRegs) { in print() local
1343 for (const SCEV *BaseReg : F.BaseRegs) { in RateFormula() local
1553 for (const SCEV *BaseReg : F.BaseRegs) in InsertFormula() local
3379 for (const SCEV *BaseReg : F.BaseRegs) in CountRegisters() local
3587 const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; in GenerateReassociationsImpl() local
3707 for (const SCEV *BaseReg : Base.BaseRegs) { in GenerateCombinations() local
3896 for (const SCEV *BaseReg : Base.BaseRegs) in GenerateICmpZeroScales() local
4064 for (const SCEV *&BaseReg : F.BaseRegs) { in GenerateTruncates() local
4248 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
[all …]
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 295 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( in evalDerivedToBase() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 439 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg() local
684 Register BaseReg = MRI.createVirtualRegister( in materializeFrameBaseRegister() local
720 void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
770 Register BaseReg, in isFrameOffsetLegal()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 964 virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
971 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, in isFrameOffsetLegal()
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