| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInsertHardClauses.cpp | 174 SmallVector<const MachineOperand *, 4> BaseOps; member
212 SmallVector<const MachineOperand *, 4> BaseOps; in runOnMachineFunction() local
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| H A D | SIInstrInfo.cpp | 360 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
[all...] |
| /llvm-project/llvm/unittests/Target/RISCV/ |
| H A D | RISCVInstrInfoTest.cpp | 166 SmallVector<const MachineOperand *> BaseOps; in TEST_P() local
[all...] |
| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 796 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 1738 SmallVector<const MachineOperand *, 4> BaseOps; global() member
1949 SmallVector<const MachineOperand *, 4> BaseOps; collectMemOpRecords() local
[all...] |
| H A D | TargetInstrInfo.cpp | 1427 SmallVector<const MachineOperand *, 4> BaseOps; getMemOperandWithOffset() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1484 getMemOperandsWithOffsetWidth(const MachineInstr & MI,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2608 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3073 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2838 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4615 getMemOperandsWithOffsetWidth(const MachineInstr & MemOp,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2700 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3699 SmallVector<SDValue, 1> BaseOps(1, Cond); visitSelect() local
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