| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 150 const MachineOperand *BaseOp; in runOnMachineFunction() local
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| H A D | AArch64InstrInfo.cpp | 2520 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2547 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
814 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 1621 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local
1767 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
2730 unsigned BaseOp = getBaseOperandIndex(*MI); in AdjustBaseAndOffset() local
2863 int BaseOp = getBaseOperandIndex(Use); in DistributeIncrements() local
2919 int BaseOp = getBaseOperandIndex(*PrePostInc); in DistributeIncrements() local
2940 unsigned BaseOp = getBaseOperandIndex(*Use); in DistributeIncrements() local
2990 int BaseOp = getBaseOperandIndex(MI); in DistributeIncrements() local
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| H A D | ARMHazardRecognizer.cpp | 107 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 96 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) in processAddUses() local
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) in updateAddUses() local
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| H A D | HexagonInstrInfo.cpp | 1086 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1101 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo() local
1124 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo() local
1140 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo() local
2978 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); in getMemOperandsWithOffsetWidth() local
3217 const MachineOperand &BaseOp = MI.getOperand(BasePos); in getBaseAndOffset() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1072 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset()
1224 const MachineOperand *BaseOp; in describeLoadedValue() local
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| H A D | MachineSink.cpp | 1007 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
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| H A D | ModuloSchedule.cpp | 913 const MachineOperand *BaseOp; in computeDelta() local
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| H A D | MachinePipeliner.cpp | 2127 const MachineOperand *BaseOp; in computeDelta() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3678 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
3746 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
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| H A D | X86ISelLowering.cpp | 23536 unsigned BaseOp = 0; in getX86XALUOOp() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1375 unsigned BaseOp = 0; in LowerXALUO() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3669 unsigned BaseOp = 0; in lowerXALUO() local
3734 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2740 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 5738 const MCOperand &BaseOp = Inst.getOperand(2); in expandSaaAddr() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 253 const MachineOperand *BaseOp, *OffsetOp; in getMemOperandsWithOffsetWidth() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6507 unsigned BaseOp; in lowerAddSubSatToMinMax() local
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