| /llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 139 for (const auto &Bank : Banks) emitHeader() local
223 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
246 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
260 for (const auto &Bank : Banks) emitBaseClassImplementation() local
273 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
303 RegisterBank Bank(*V, CGH.getNumModeIds()); run() local
323 for (const auto &Bank : Banks) { run() local
[all...] |
| H A D | RegisterInfoEmitter.cpp | 105 runEnums(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & Bank) runEnums() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 221 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank() argument
668 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping() local
707 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane() local
1019 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane() local
2008 constrainRegToBank(MachineRegisterInfo & MRI,MachineIRBuilder & B,Register & Reg,const RegisterBank & Bank) constrainRegToBank() argument
3496 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { getMappingType() local
3513 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { isSALUMapping() local
3692 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); getRegBankID() local
3702 unsigned Bank = getRegBankID(Reg, MRI, AMDGPU::SGPRRegBankID); getSGPROpMapping() local
3801 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); getInstrMapping() local
4023 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { getInstrMapping() local
4129 unsigned Bank = getMappingType(MRI, MI); getInstrMapping() local
4174 unsigned Bank = getRegBankID(Src, MRI); getInstrMapping() local
4315 unsigned Bank = getMappingType(MRI, MI); getInstrMapping() local
4945 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
4952 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
4959 unsigned Bank = getInstrMapping() local
5059 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
5068 unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, getInstrMapping() local
5167 unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SGPRRegBankID ? getInstrMapping() local
5239 unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, getInstrMapping() local
[all...] |
| H A D | SIRegisterInfo.h | 337 getRegClassForTypeOnBank(LLT Ty,const RegisterBank & Bank) getRegClassForTypeOnBank() argument
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 352 const RegisterBank *Bank = setTypesAccordingToPhysicalRegister() local
530 const RegisterBankInfo::ValueMapping *Bank = getFprbMapping(Op0Size); getInstrMapping() local
539 const RegisterBankInfo::ValueMapping *Bank = getInstrMapping() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 67 const RegisterBank *Bank; global() member
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| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 185 selectIndexedProgMemLoad(const LoadSDNode * LD,MVT VT,int Bank) selectIndexedProgMemLoad() argument
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| H A D | AVRExpandPseudoInsts.cpp | 851 Register Bank = MI.getOperand(2).getReg(); in expandLPMWELPMW() local
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