| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 137 for (const auto &Bank : Banks) emitHeader() local
222 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
244 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
258 for (const auto &Bank : Banks) emitBaseClassImplementation() local
271 for (const auto &Bank : Banks) { emitBaseClassImplementation() local
301 RegisterBank Bank(*V, CGH.getNumModeIds()); run() local
321 for (const auto &Bank : Banks) { run() local
[all...] |
| H A D | RegisterInfoEmitter.cpp | 105 CodeGenRegBank &Bank) { in runEnums() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 221 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank() argument
668 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping() local
707 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane() local
1019 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane() local
2008 constrainRegToBank(MachineRegisterInfo & MRI,MachineIRBuilder & B,Register & Reg,const RegisterBank & Bank) constrainRegToBank() argument
3490 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { getMappingType() local
3507 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { isSALUMapping() local
3686 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); getRegBankID() local
3696 unsigned Bank = getRegBankID(Reg, MRI, AMDGPU::SGPRRegBankID); getSGPROpMapping() local
3795 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); getInstrMapping() local
4017 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { getInstrMapping() local
4122 unsigned Bank = getMappingType(MRI, MI); getInstrMapping() local
4167 unsigned Bank = getRegBankID(Src, MRI); getInstrMapping() local
4308 unsigned Bank = getMappingType(MRI, MI); getInstrMapping() local
4924 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
4931 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
4938 unsigned Bank = getInstrMapping() local
5038 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, getInstrMapping() local
5047 unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, getInstrMapping() local
5144 unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SGPRRegBankID ? getInstrMapping() local
5216 unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, getInstrMapping() local
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| H A D | SIRegisterInfo.h | 337 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { in getRegClassForTypeOnBank()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 371 const RegisterBank *Bank = setTypesAccordingToPhysicalRegister() local
549 const RegisterBankInfo::ValueMapping *Bank = getFprbMapping(Op0Size); getInstrMapping() local
558 const RegisterBankInfo::ValueMapping *Bank = getInstrMapping() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 67 const RegisterBank *Bank; member
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 179 selectIndexedProgMemLoad(const LoadSDNode * LD,MVT VT,int Bank) selectIndexedProgMemLoad() argument
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| H A D | AVRExpandPseudoInsts.cpp | 851 Register Bank = MI.getOperand(2).getReg(); in expandLPMWELPMW() local
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| /freebsd-src/sys/dev/acpica/ |
| H A D | acpi_apei.c | 104 uint16_t Bank; member
|