xref: /netbsd-src/sys/external/bsd/sljit/dist/sljit_src/sljitNativeTILEGX-encoder.c (revision e35f55c6f088a9d849ac9e2c68755800c96229c2) 
1 /*	$NetBSD: sljitNativeTILEGX-encoder.c,v 1.3 2019/01/20 23:14:16 alnsn Exp $	*/
2 
3 /*
4  *    Stack-less Just-In-Time compiler
5  *
6  *    Copyright 2013-2013 Tilera Corporation(jiwang@tilera.com). All rights reserved.
7  *    Copyright Zoltan Herczeg (hzmester@freemail.hu). All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without modification, are
10  * permitted provided that the following conditions are met:
11  *
12  *   1. Redistributions of source code must retain the above copyright notice, this list of
13  *      conditions and the following disclaimer.
14  *
15  *   2. Redistributions in binary form must reproduce the above copyright notice, this list
16  *      of conditions and the following disclaimer in the documentation and/or other materials
17  *      provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY
20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
22  * SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
25  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 /* This code is owned by Tilera Corporation, and distributed as part
31    of multiple projects. In sljit, the code is under BSD licence.  */
32 
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #define BFD_RELOC(x) R_##x
37 
38 /* Special registers. */
39 #define TREG_LR 55
40 #define TREG_SN 56
41 #define TREG_ZERO 63
42 
43 /* Canonical name of each register. */
44 const char *const tilegx_register_names[] =
45 {
46   "r0",   "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
47   "r8",   "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
48   "r16",  "r17", "r18", "r19", "r20", "r21", "r22", "r23",
49   "r24",  "r25", "r26", "r27", "r28", "r29", "r30", "r31",
50   "r32",  "r33", "r34", "r35", "r36", "r37", "r38", "r39",
51   "r40",  "r41", "r42", "r43", "r44", "r45", "r46", "r47",
52   "r48",  "r49", "r50", "r51", "r52", "tp",  "sp",  "lr",
53   "sn",  "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
54 };
55 
56 enum
57 {
58   R_NONE = 0,
59   R_TILEGX_NONE = 0,
60   R_TILEGX_64 = 1,
61   R_TILEGX_32 = 2,
62   R_TILEGX_16 = 3,
63   R_TILEGX_8 = 4,
64   R_TILEGX_64_PCREL = 5,
65   R_TILEGX_32_PCREL = 6,
66   R_TILEGX_16_PCREL = 7,
67   R_TILEGX_8_PCREL = 8,
68   R_TILEGX_HW0 = 9,
69   R_TILEGX_HW1 = 10,
70   R_TILEGX_HW2 = 11,
71   R_TILEGX_HW3 = 12,
72   R_TILEGX_HW0_LAST = 13,
73   R_TILEGX_HW1_LAST = 14,
74   R_TILEGX_HW2_LAST = 15,
75   R_TILEGX_COPY = 16,
76   R_TILEGX_GLOB_DAT = 17,
77   R_TILEGX_JMP_SLOT = 18,
78   R_TILEGX_RELATIVE = 19,
79   R_TILEGX_BROFF_X1 = 20,
80   R_TILEGX_JUMPOFF_X1 = 21,
81   R_TILEGX_JUMPOFF_X1_PLT = 22,
82   R_TILEGX_IMM8_X0 = 23,
83   R_TILEGX_IMM8_Y0 = 24,
84   R_TILEGX_IMM8_X1 = 25,
85   R_TILEGX_IMM8_Y1 = 26,
86   R_TILEGX_DEST_IMM8_X1 = 27,
87   R_TILEGX_MT_IMM14_X1 = 28,
88   R_TILEGX_MF_IMM14_X1 = 29,
89   R_TILEGX_MMSTART_X0 = 30,
90   R_TILEGX_MMEND_X0 = 31,
91   R_TILEGX_SHAMT_X0 = 32,
92   R_TILEGX_SHAMT_X1 = 33,
93   R_TILEGX_SHAMT_Y0 = 34,
94   R_TILEGX_SHAMT_Y1 = 35,
95   R_TILEGX_IMM16_X0_HW0 = 36,
96   R_TILEGX_IMM16_X1_HW0 = 37,
97   R_TILEGX_IMM16_X0_HW1 = 38,
98   R_TILEGX_IMM16_X1_HW1 = 39,
99   R_TILEGX_IMM16_X0_HW2 = 40,
100   R_TILEGX_IMM16_X1_HW2 = 41,
101   R_TILEGX_IMM16_X0_HW3 = 42,
102   R_TILEGX_IMM16_X1_HW3 = 43,
103   R_TILEGX_IMM16_X0_HW0_LAST = 44,
104   R_TILEGX_IMM16_X1_HW0_LAST = 45,
105   R_TILEGX_IMM16_X0_HW1_LAST = 46,
106   R_TILEGX_IMM16_X1_HW1_LAST = 47,
107   R_TILEGX_IMM16_X0_HW2_LAST = 48,
108   R_TILEGX_IMM16_X1_HW2_LAST = 49,
109   R_TILEGX_IMM16_X0_HW0_PCREL = 50,
110   R_TILEGX_IMM16_X1_HW0_PCREL = 51,
111   R_TILEGX_IMM16_X0_HW1_PCREL = 52,
112   R_TILEGX_IMM16_X1_HW1_PCREL = 53,
113   R_TILEGX_IMM16_X0_HW2_PCREL = 54,
114   R_TILEGX_IMM16_X1_HW2_PCREL = 55,
115   R_TILEGX_IMM16_X0_HW3_PCREL = 56,
116   R_TILEGX_IMM16_X1_HW3_PCREL = 57,
117   R_TILEGX_IMM16_X0_HW0_LAST_PCREL = 58,
118   R_TILEGX_IMM16_X1_HW0_LAST_PCREL = 59,
119   R_TILEGX_IMM16_X0_HW1_LAST_PCREL = 60,
120   R_TILEGX_IMM16_X1_HW1_LAST_PCREL = 61,
121   R_TILEGX_IMM16_X0_HW2_LAST_PCREL = 62,
122   R_TILEGX_IMM16_X1_HW2_LAST_PCREL = 63,
123   R_TILEGX_IMM16_X0_HW0_GOT = 64,
124   R_TILEGX_IMM16_X1_HW0_GOT = 65,
125 
126   R_TILEGX_IMM16_X0_HW0_PLT_PCREL = 66,
127   R_TILEGX_IMM16_X1_HW0_PLT_PCREL = 67,
128   R_TILEGX_IMM16_X0_HW1_PLT_PCREL = 68,
129   R_TILEGX_IMM16_X1_HW1_PLT_PCREL = 69,
130   R_TILEGX_IMM16_X0_HW2_PLT_PCREL = 70,
131   R_TILEGX_IMM16_X1_HW2_PLT_PCREL = 71,
132 
133   R_TILEGX_IMM16_X0_HW0_LAST_GOT = 72,
134   R_TILEGX_IMM16_X1_HW0_LAST_GOT = 73,
135   R_TILEGX_IMM16_X0_HW1_LAST_GOT = 74,
136   R_TILEGX_IMM16_X1_HW1_LAST_GOT = 75,
137   R_TILEGX_IMM16_X0_HW0_TLS_GD = 78,
138   R_TILEGX_IMM16_X1_HW0_TLS_GD = 79,
139   R_TILEGX_IMM16_X0_HW0_TLS_LE = 80,
140   R_TILEGX_IMM16_X1_HW0_TLS_LE = 81,
141   R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE = 82,
142   R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE = 83,
143   R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE = 84,
144   R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE = 85,
145   R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD = 86,
146   R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD = 87,
147   R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD = 88,
148   R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD = 89,
149   R_TILEGX_IMM16_X0_HW0_TLS_IE = 92,
150   R_TILEGX_IMM16_X1_HW0_TLS_IE = 93,
151 
152   R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL = 94,
153   R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL = 95,
154   R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL = 96,
155   R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL = 97,
156   R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL = 98,
157   R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL = 99,
158 
159   R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE = 100,
160   R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE = 101,
161   R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE = 102,
162   R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE = 103,
163   R_TILEGX_TLS_DTPMOD64 = 106,
164   R_TILEGX_TLS_DTPOFF64 = 107,
165   R_TILEGX_TLS_TPOFF64 = 108,
166   R_TILEGX_TLS_DTPMOD32 = 109,
167   R_TILEGX_TLS_DTPOFF32 = 110,
168   R_TILEGX_TLS_TPOFF32 = 111,
169   R_TILEGX_TLS_GD_CALL = 112,
170   R_TILEGX_IMM8_X0_TLS_GD_ADD = 113,
171   R_TILEGX_IMM8_X1_TLS_GD_ADD = 114,
172   R_TILEGX_IMM8_Y0_TLS_GD_ADD = 115,
173   R_TILEGX_IMM8_Y1_TLS_GD_ADD = 116,
174   R_TILEGX_TLS_IE_LOAD = 117,
175   R_TILEGX_IMM8_X0_TLS_ADD = 118,
176   R_TILEGX_IMM8_X1_TLS_ADD = 119,
177   R_TILEGX_IMM8_Y0_TLS_ADD = 120,
178   R_TILEGX_IMM8_Y1_TLS_ADD = 121,
179   R_TILEGX_GNU_VTINHERIT = 128,
180   R_TILEGX_GNU_VTENTRY = 129,
181   R_TILEGX_IRELATIVE = 130,
182   R_TILEGX_NUM = 131
183 };
184 
185 typedef enum
186 {
187   TILEGX_PIPELINE_X0,
188   TILEGX_PIPELINE_X1,
189   TILEGX_PIPELINE_Y0,
190   TILEGX_PIPELINE_Y1,
191   TILEGX_PIPELINE_Y2,
192 } tilegx_pipeline;
193 
194 typedef unsigned long long tilegx_bundle_bits;
195 
196 /* These are the bits that determine if a bundle is in the X encoding. */
197 #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
198 
199 enum
200 {
201   /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
202   TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
203 
204   /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
205   TILEGX_NUM_PIPELINE_ENCODINGS = 5,
206 
207   /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
208   TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
209 
210   /* Instructions take this many bytes. */
211   TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
212 
213   /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
214   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
215 
216   /* Bundles should be aligned modulo this number of bytes. */
217   TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
218     (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
219 
220   /* Number of registers (some are magic, such as network I/O). */
221   TILEGX_NUM_REGISTERS = 64,
222 };
223 
224 /* Make a few "tile_" variables to simplify common code between
225    architectures.  */
226 
227 typedef tilegx_bundle_bits tile_bundle_bits;
228 #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
229 #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
230 #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
231   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
232 
233 /* 64-bit pattern for a { bpt ; nop } bundle. */
234 #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
235 
236 typedef enum
237 {
238   TILEGX_OP_TYPE_REGISTER,
239   TILEGX_OP_TYPE_IMMEDIATE,
240   TILEGX_OP_TYPE_ADDRESS,
241   TILEGX_OP_TYPE_SPR
242 } tilegx_operand_type;
243 
244 struct tilegx_operand
245 {
246   /* Is this operand a register, immediate or address? */
247   tilegx_operand_type type;
248 
249   /* The default relocation type for this operand.  */
250   signed int default_reloc : 16;
251 
252   /* How many bits is this value? (used for range checking) */
253   unsigned int num_bits : 5;
254 
255   /* Is the value signed? (used for range checking) */
256   unsigned int is_signed : 1;
257 
258   /* Is this operand a source register? */
259   unsigned int is_src_reg : 1;
260 
261   /* Is this operand written? (i.e. is it a destination register) */
262   unsigned int is_dest_reg : 1;
263 
264   /* Is this operand PC-relative? */
265   unsigned int is_pc_relative : 1;
266 
267   /* By how many bits do we right shift the value before inserting? */
268   unsigned int rightshift : 2;
269 
270   /* Return the bits for this operand to be ORed into an existing bundle. */
271   tilegx_bundle_bits (*insert) (int op);
272 
273   /* Extract this operand and return it. */
274   unsigned int (*extract) (tilegx_bundle_bits bundle);
275 };
276 
277 typedef enum
278 {
279   TILEGX_OPC_BPT,
280   TILEGX_OPC_INFO,
281   TILEGX_OPC_INFOL,
282   TILEGX_OPC_LD4S_TLS,
283   TILEGX_OPC_LD_TLS,
284   TILEGX_OPC_MOVE,
285   TILEGX_OPC_MOVEI,
286   TILEGX_OPC_MOVELI,
287   TILEGX_OPC_PREFETCH,
288   TILEGX_OPC_PREFETCH_ADD_L1,
289   TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
290   TILEGX_OPC_PREFETCH_ADD_L2,
291   TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
292   TILEGX_OPC_PREFETCH_ADD_L3,
293   TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
294   TILEGX_OPC_PREFETCH_L1,
295   TILEGX_OPC_PREFETCH_L1_FAULT,
296   TILEGX_OPC_PREFETCH_L2,
297   TILEGX_OPC_PREFETCH_L2_FAULT,
298   TILEGX_OPC_PREFETCH_L3,
299   TILEGX_OPC_PREFETCH_L3_FAULT,
300   TILEGX_OPC_RAISE,
301   TILEGX_OPC_ADD,
302   TILEGX_OPC_ADDI,
303   TILEGX_OPC_ADDLI,
304   TILEGX_OPC_ADDX,
305   TILEGX_OPC_ADDXI,
306   TILEGX_OPC_ADDXLI,
307   TILEGX_OPC_ADDXSC,
308   TILEGX_OPC_AND,
309   TILEGX_OPC_ANDI,
310   TILEGX_OPC_BEQZ,
311   TILEGX_OPC_BEQZT,
312   TILEGX_OPC_BFEXTS,
313   TILEGX_OPC_BFEXTU,
314   TILEGX_OPC_BFINS,
315   TILEGX_OPC_BGEZ,
316   TILEGX_OPC_BGEZT,
317   TILEGX_OPC_BGTZ,
318   TILEGX_OPC_BGTZT,
319   TILEGX_OPC_BLBC,
320   TILEGX_OPC_BLBCT,
321   TILEGX_OPC_BLBS,
322   TILEGX_OPC_BLBST,
323   TILEGX_OPC_BLEZ,
324   TILEGX_OPC_BLEZT,
325   TILEGX_OPC_BLTZ,
326   TILEGX_OPC_BLTZT,
327   TILEGX_OPC_BNEZ,
328   TILEGX_OPC_BNEZT,
329   TILEGX_OPC_CLZ,
330   TILEGX_OPC_CMOVEQZ,
331   TILEGX_OPC_CMOVNEZ,
332   TILEGX_OPC_CMPEQ,
333   TILEGX_OPC_CMPEQI,
334   TILEGX_OPC_CMPEXCH,
335   TILEGX_OPC_CMPEXCH4,
336   TILEGX_OPC_CMPLES,
337   TILEGX_OPC_CMPLEU,
338   TILEGX_OPC_CMPLTS,
339   TILEGX_OPC_CMPLTSI,
340   TILEGX_OPC_CMPLTU,
341   TILEGX_OPC_CMPLTUI,
342   TILEGX_OPC_CMPNE,
343   TILEGX_OPC_CMUL,
344   TILEGX_OPC_CMULA,
345   TILEGX_OPC_CMULAF,
346   TILEGX_OPC_CMULF,
347   TILEGX_OPC_CMULFR,
348   TILEGX_OPC_CMULH,
349   TILEGX_OPC_CMULHR,
350   TILEGX_OPC_CRC32_32,
351   TILEGX_OPC_CRC32_8,
352   TILEGX_OPC_CTZ,
353   TILEGX_OPC_DBLALIGN,
354   TILEGX_OPC_DBLALIGN2,
355   TILEGX_OPC_DBLALIGN4,
356   TILEGX_OPC_DBLALIGN6,
357   TILEGX_OPC_DRAIN,
358   TILEGX_OPC_DTLBPR,
359   TILEGX_OPC_EXCH,
360   TILEGX_OPC_EXCH4,
361   TILEGX_OPC_FDOUBLE_ADD_FLAGS,
362   TILEGX_OPC_FDOUBLE_ADDSUB,
363   TILEGX_OPC_FDOUBLE_MUL_FLAGS,
364   TILEGX_OPC_FDOUBLE_PACK1,
365   TILEGX_OPC_FDOUBLE_PACK2,
366   TILEGX_OPC_FDOUBLE_SUB_FLAGS,
367   TILEGX_OPC_FDOUBLE_UNPACK_MAX,
368   TILEGX_OPC_FDOUBLE_UNPACK_MIN,
369   TILEGX_OPC_FETCHADD,
370   TILEGX_OPC_FETCHADD4,
371   TILEGX_OPC_FETCHADDGEZ,
372   TILEGX_OPC_FETCHADDGEZ4,
373   TILEGX_OPC_FETCHAND,
374   TILEGX_OPC_FETCHAND4,
375   TILEGX_OPC_FETCHOR,
376   TILEGX_OPC_FETCHOR4,
377   TILEGX_OPC_FINV,
378   TILEGX_OPC_FLUSH,
379   TILEGX_OPC_FLUSHWB,
380   TILEGX_OPC_FNOP,
381   TILEGX_OPC_FSINGLE_ADD1,
382   TILEGX_OPC_FSINGLE_ADDSUB2,
383   TILEGX_OPC_FSINGLE_MUL1,
384   TILEGX_OPC_FSINGLE_MUL2,
385   TILEGX_OPC_FSINGLE_PACK1,
386   TILEGX_OPC_FSINGLE_PACK2,
387   TILEGX_OPC_FSINGLE_SUB1,
388   TILEGX_OPC_ICOH,
389   TILEGX_OPC_ILL,
390   TILEGX_OPC_INV,
391   TILEGX_OPC_IRET,
392   TILEGX_OPC_J,
393   TILEGX_OPC_JAL,
394   TILEGX_OPC_JALR,
395   TILEGX_OPC_JALRP,
396   TILEGX_OPC_JR,
397   TILEGX_OPC_JRP,
398   TILEGX_OPC_LD,
399   TILEGX_OPC_LD1S,
400   TILEGX_OPC_LD1S_ADD,
401   TILEGX_OPC_LD1U,
402   TILEGX_OPC_LD1U_ADD,
403   TILEGX_OPC_LD2S,
404   TILEGX_OPC_LD2S_ADD,
405   TILEGX_OPC_LD2U,
406   TILEGX_OPC_LD2U_ADD,
407   TILEGX_OPC_LD4S,
408   TILEGX_OPC_LD4S_ADD,
409   TILEGX_OPC_LD4U,
410   TILEGX_OPC_LD4U_ADD,
411   TILEGX_OPC_LD_ADD,
412   TILEGX_OPC_LDNA,
413   TILEGX_OPC_LDNA_ADD,
414   TILEGX_OPC_LDNT,
415   TILEGX_OPC_LDNT1S,
416   TILEGX_OPC_LDNT1S_ADD,
417   TILEGX_OPC_LDNT1U,
418   TILEGX_OPC_LDNT1U_ADD,
419   TILEGX_OPC_LDNT2S,
420   TILEGX_OPC_LDNT2S_ADD,
421   TILEGX_OPC_LDNT2U,
422   TILEGX_OPC_LDNT2U_ADD,
423   TILEGX_OPC_LDNT4S,
424   TILEGX_OPC_LDNT4S_ADD,
425   TILEGX_OPC_LDNT4U,
426   TILEGX_OPC_LDNT4U_ADD,
427   TILEGX_OPC_LDNT_ADD,
428   TILEGX_OPC_LNK,
429   TILEGX_OPC_MF,
430   TILEGX_OPC_MFSPR,
431   TILEGX_OPC_MM,
432   TILEGX_OPC_MNZ,
433   TILEGX_OPC_MTSPR,
434   TILEGX_OPC_MUL_HS_HS,
435   TILEGX_OPC_MUL_HS_HU,
436   TILEGX_OPC_MUL_HS_LS,
437   TILEGX_OPC_MUL_HS_LU,
438   TILEGX_OPC_MUL_HU_HU,
439   TILEGX_OPC_MUL_HU_LS,
440   TILEGX_OPC_MUL_HU_LU,
441   TILEGX_OPC_MUL_LS_LS,
442   TILEGX_OPC_MUL_LS_LU,
443   TILEGX_OPC_MUL_LU_LU,
444   TILEGX_OPC_MULA_HS_HS,
445   TILEGX_OPC_MULA_HS_HU,
446   TILEGX_OPC_MULA_HS_LS,
447   TILEGX_OPC_MULA_HS_LU,
448   TILEGX_OPC_MULA_HU_HU,
449   TILEGX_OPC_MULA_HU_LS,
450   TILEGX_OPC_MULA_HU_LU,
451   TILEGX_OPC_MULA_LS_LS,
452   TILEGX_OPC_MULA_LS_LU,
453   TILEGX_OPC_MULA_LU_LU,
454   TILEGX_OPC_MULAX,
455   TILEGX_OPC_MULX,
456   TILEGX_OPC_MZ,
457   TILEGX_OPC_NAP,
458   TILEGX_OPC_NOP,
459   TILEGX_OPC_NOR,
460   TILEGX_OPC_OR,
461   TILEGX_OPC_ORI,
462   TILEGX_OPC_PCNT,
463   TILEGX_OPC_REVBITS,
464   TILEGX_OPC_REVBYTES,
465   TILEGX_OPC_ROTL,
466   TILEGX_OPC_ROTLI,
467   TILEGX_OPC_SHL,
468   TILEGX_OPC_SHL16INSLI,
469   TILEGX_OPC_SHL1ADD,
470   TILEGX_OPC_SHL1ADDX,
471   TILEGX_OPC_SHL2ADD,
472   TILEGX_OPC_SHL2ADDX,
473   TILEGX_OPC_SHL3ADD,
474   TILEGX_OPC_SHL3ADDX,
475   TILEGX_OPC_SHLI,
476   TILEGX_OPC_SHLX,
477   TILEGX_OPC_SHLXI,
478   TILEGX_OPC_SHRS,
479   TILEGX_OPC_SHRSI,
480   TILEGX_OPC_SHRU,
481   TILEGX_OPC_SHRUI,
482   TILEGX_OPC_SHRUX,
483   TILEGX_OPC_SHRUXI,
484   TILEGX_OPC_SHUFFLEBYTES,
485   TILEGX_OPC_ST,
486   TILEGX_OPC_ST1,
487   TILEGX_OPC_ST1_ADD,
488   TILEGX_OPC_ST2,
489   TILEGX_OPC_ST2_ADD,
490   TILEGX_OPC_ST4,
491   TILEGX_OPC_ST4_ADD,
492   TILEGX_OPC_ST_ADD,
493   TILEGX_OPC_STNT,
494   TILEGX_OPC_STNT1,
495   TILEGX_OPC_STNT1_ADD,
496   TILEGX_OPC_STNT2,
497   TILEGX_OPC_STNT2_ADD,
498   TILEGX_OPC_STNT4,
499   TILEGX_OPC_STNT4_ADD,
500   TILEGX_OPC_STNT_ADD,
501   TILEGX_OPC_SUB,
502   TILEGX_OPC_SUBX,
503   TILEGX_OPC_SUBXSC,
504   TILEGX_OPC_SWINT0,
505   TILEGX_OPC_SWINT1,
506   TILEGX_OPC_SWINT2,
507   TILEGX_OPC_SWINT3,
508   TILEGX_OPC_TBLIDXB0,
509   TILEGX_OPC_TBLIDXB1,
510   TILEGX_OPC_TBLIDXB2,
511   TILEGX_OPC_TBLIDXB3,
512   TILEGX_OPC_V1ADD,
513   TILEGX_OPC_V1ADDI,
514   TILEGX_OPC_V1ADDUC,
515   TILEGX_OPC_V1ADIFFU,
516   TILEGX_OPC_V1AVGU,
517   TILEGX_OPC_V1CMPEQ,
518   TILEGX_OPC_V1CMPEQI,
519   TILEGX_OPC_V1CMPLES,
520   TILEGX_OPC_V1CMPLEU,
521   TILEGX_OPC_V1CMPLTS,
522   TILEGX_OPC_V1CMPLTSI,
523   TILEGX_OPC_V1CMPLTU,
524   TILEGX_OPC_V1CMPLTUI,
525   TILEGX_OPC_V1CMPNE,
526   TILEGX_OPC_V1DDOTPU,
527   TILEGX_OPC_V1DDOTPUA,
528   TILEGX_OPC_V1DDOTPUS,
529   TILEGX_OPC_V1DDOTPUSA,
530   TILEGX_OPC_V1DOTP,
531   TILEGX_OPC_V1DOTPA,
532   TILEGX_OPC_V1DOTPU,
533   TILEGX_OPC_V1DOTPUA,
534   TILEGX_OPC_V1DOTPUS,
535   TILEGX_OPC_V1DOTPUSA,
536   TILEGX_OPC_V1INT_H,
537   TILEGX_OPC_V1INT_L,
538   TILEGX_OPC_V1MAXU,
539   TILEGX_OPC_V1MAXUI,
540   TILEGX_OPC_V1MINU,
541   TILEGX_OPC_V1MINUI,
542   TILEGX_OPC_V1MNZ,
543   TILEGX_OPC_V1MULTU,
544   TILEGX_OPC_V1MULU,
545   TILEGX_OPC_V1MULUS,
546   TILEGX_OPC_V1MZ,
547   TILEGX_OPC_V1SADAU,
548   TILEGX_OPC_V1SADU,
549   TILEGX_OPC_V1SHL,
550   TILEGX_OPC_V1SHLI,
551   TILEGX_OPC_V1SHRS,
552   TILEGX_OPC_V1SHRSI,
553   TILEGX_OPC_V1SHRU,
554   TILEGX_OPC_V1SHRUI,
555   TILEGX_OPC_V1SUB,
556   TILEGX_OPC_V1SUBUC,
557   TILEGX_OPC_V2ADD,
558   TILEGX_OPC_V2ADDI,
559   TILEGX_OPC_V2ADDSC,
560   TILEGX_OPC_V2ADIFFS,
561   TILEGX_OPC_V2AVGS,
562   TILEGX_OPC_V2CMPEQ,
563   TILEGX_OPC_V2CMPEQI,
564   TILEGX_OPC_V2CMPLES,
565   TILEGX_OPC_V2CMPLEU,
566   TILEGX_OPC_V2CMPLTS,
567   TILEGX_OPC_V2CMPLTSI,
568   TILEGX_OPC_V2CMPLTU,
569   TILEGX_OPC_V2CMPLTUI,
570   TILEGX_OPC_V2CMPNE,
571   TILEGX_OPC_V2DOTP,
572   TILEGX_OPC_V2DOTPA,
573   TILEGX_OPC_V2INT_H,
574   TILEGX_OPC_V2INT_L,
575   TILEGX_OPC_V2MAXS,
576   TILEGX_OPC_V2MAXSI,
577   TILEGX_OPC_V2MINS,
578   TILEGX_OPC_V2MINSI,
579   TILEGX_OPC_V2MNZ,
580   TILEGX_OPC_V2MULFSC,
581   TILEGX_OPC_V2MULS,
582   TILEGX_OPC_V2MULTS,
583   TILEGX_OPC_V2MZ,
584   TILEGX_OPC_V2PACKH,
585   TILEGX_OPC_V2PACKL,
586   TILEGX_OPC_V2PACKUC,
587   TILEGX_OPC_V2SADAS,
588   TILEGX_OPC_V2SADAU,
589   TILEGX_OPC_V2SADS,
590   TILEGX_OPC_V2SADU,
591   TILEGX_OPC_V2SHL,
592   TILEGX_OPC_V2SHLI,
593   TILEGX_OPC_V2SHLSC,
594   TILEGX_OPC_V2SHRS,
595   TILEGX_OPC_V2SHRSI,
596   TILEGX_OPC_V2SHRU,
597   TILEGX_OPC_V2SHRUI,
598   TILEGX_OPC_V2SUB,
599   TILEGX_OPC_V2SUBSC,
600   TILEGX_OPC_V4ADD,
601   TILEGX_OPC_V4ADDSC,
602   TILEGX_OPC_V4INT_H,
603   TILEGX_OPC_V4INT_L,
604   TILEGX_OPC_V4PACKSC,
605   TILEGX_OPC_V4SHL,
606   TILEGX_OPC_V4SHLSC,
607   TILEGX_OPC_V4SHRS,
608   TILEGX_OPC_V4SHRU,
609   TILEGX_OPC_V4SUB,
610   TILEGX_OPC_V4SUBSC,
611   TILEGX_OPC_WH64,
612   TILEGX_OPC_XOR,
613   TILEGX_OPC_XORI,
614   TILEGX_OPC_NONE
615 } tilegx_mnemonic;
616 
617 enum
618 {
619   TILEGX_MAX_OPERANDS = 4 /* bfexts */
620 };
621 
622 struct tilegx_opcode
623 {
624   /* The opcode mnemonic, e.g. "add" */
625   const char *name;
626 
627   /* The enum value for this mnemonic. */
628   tilegx_mnemonic mnemonic;
629 
630   /* A bit mask of which of the five pipes this instruction
631      is compatible with:
632      X0  0x01
633      X1  0x02
634      Y0  0x04
635      Y1  0x08
636      Y2  0x10 */
637   unsigned char pipes;
638 
639   /* How many operands are there? */
640   unsigned char num_operands;
641 
642   /* Which register does this write implicitly, or TREG_ZERO if none? */
643   unsigned char implicitly_written_register;
644 
645   /* Can this be bundled with other instructions (almost always true). */
646   unsigned char can_bundle;
647 
648   /* The description of the operands. Each of these is an
649    * index into the tilegx_operands[] table. */
650   unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
651 
652   /* A mask of which bits have predefined values for each pipeline.
653    * This is useful for disassembly. */
654   tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS];
655 
656   /* For each bit set in fixed_bit_masks, what the value is for this
657    * instruction. */
658   tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS];
659 };
660 
661 /* Used for non-textual disassembly into structs. */
662 struct tilegx_decoded_instruction
663 {
664   const struct tilegx_opcode *opcode;
665   const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
666   long long operand_values[TILEGX_MAX_OPERANDS];
667 };
668 
669 enum
670 {
671   ADDI_IMM8_OPCODE_X0 = 1,
672   ADDI_IMM8_OPCODE_X1 = 1,
673   ADDI_OPCODE_Y0 = 0,
674   ADDI_OPCODE_Y1 = 1,
675   ADDLI_OPCODE_X0 = 1,
676   ADDLI_OPCODE_X1 = 0,
677   ADDXI_IMM8_OPCODE_X0 = 2,
678   ADDXI_IMM8_OPCODE_X1 = 2,
679   ADDXI_OPCODE_Y0 = 1,
680   ADDXI_OPCODE_Y1 = 2,
681   ADDXLI_OPCODE_X0 = 2,
682   ADDXLI_OPCODE_X1 = 1,
683   ADDXSC_RRR_0_OPCODE_X0 = 1,
684   ADDXSC_RRR_0_OPCODE_X1 = 1,
685   ADDX_RRR_0_OPCODE_X0 = 2,
686   ADDX_RRR_0_OPCODE_X1 = 2,
687   ADDX_RRR_0_OPCODE_Y0 = 0,
688   ADDX_SPECIAL_0_OPCODE_Y1 = 0,
689   ADD_RRR_0_OPCODE_X0 = 3,
690   ADD_RRR_0_OPCODE_X1 = 3,
691   ADD_RRR_0_OPCODE_Y0 = 1,
692   ADD_SPECIAL_0_OPCODE_Y1 = 1,
693   ANDI_IMM8_OPCODE_X0 = 3,
694   ANDI_IMM8_OPCODE_X1 = 3,
695   ANDI_OPCODE_Y0 = 2,
696   ANDI_OPCODE_Y1 = 3,
697   AND_RRR_0_OPCODE_X0 = 4,
698   AND_RRR_0_OPCODE_X1 = 4,
699   AND_RRR_5_OPCODE_Y0 = 0,
700   AND_RRR_5_OPCODE_Y1 = 0,
701   BEQZT_BRANCH_OPCODE_X1 = 16,
702   BEQZ_BRANCH_OPCODE_X1 = 17,
703   BFEXTS_BF_OPCODE_X0 = 4,
704   BFEXTU_BF_OPCODE_X0 = 5,
705   BFINS_BF_OPCODE_X0 = 6,
706   BF_OPCODE_X0 = 3,
707   BGEZT_BRANCH_OPCODE_X1 = 18,
708   BGEZ_BRANCH_OPCODE_X1 = 19,
709   BGTZT_BRANCH_OPCODE_X1 = 20,
710   BGTZ_BRANCH_OPCODE_X1 = 21,
711   BLBCT_BRANCH_OPCODE_X1 = 22,
712   BLBC_BRANCH_OPCODE_X1 = 23,
713   BLBST_BRANCH_OPCODE_X1 = 24,
714   BLBS_BRANCH_OPCODE_X1 = 25,
715   BLEZT_BRANCH_OPCODE_X1 = 26,
716   BLEZ_BRANCH_OPCODE_X1 = 27,
717   BLTZT_BRANCH_OPCODE_X1 = 28,
718   BLTZ_BRANCH_OPCODE_X1 = 29,
719   BNEZT_BRANCH_OPCODE_X1 = 30,
720   BNEZ_BRANCH_OPCODE_X1 = 31,
721   BRANCH_OPCODE_X1 = 2,
722   CMOVEQZ_RRR_0_OPCODE_X0 = 5,
723   CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
724   CMOVNEZ_RRR_0_OPCODE_X0 = 6,
725   CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
726   CMPEQI_IMM8_OPCODE_X0 = 4,
727   CMPEQI_IMM8_OPCODE_X1 = 4,
728   CMPEQI_OPCODE_Y0 = 3,
729   CMPEQI_OPCODE_Y1 = 4,
730   CMPEQ_RRR_0_OPCODE_X0 = 7,
731   CMPEQ_RRR_0_OPCODE_X1 = 5,
732   CMPEQ_RRR_3_OPCODE_Y0 = 0,
733   CMPEQ_RRR_3_OPCODE_Y1 = 2,
734   CMPEXCH4_RRR_0_OPCODE_X1 = 6,
735   CMPEXCH_RRR_0_OPCODE_X1 = 7,
736   CMPLES_RRR_0_OPCODE_X0 = 8,
737   CMPLES_RRR_0_OPCODE_X1 = 8,
738   CMPLES_RRR_2_OPCODE_Y0 = 0,
739   CMPLES_RRR_2_OPCODE_Y1 = 0,
740   CMPLEU_RRR_0_OPCODE_X0 = 9,
741   CMPLEU_RRR_0_OPCODE_X1 = 9,
742   CMPLEU_RRR_2_OPCODE_Y0 = 1,
743   CMPLEU_RRR_2_OPCODE_Y1 = 1,
744   CMPLTSI_IMM8_OPCODE_X0 = 5,
745   CMPLTSI_IMM8_OPCODE_X1 = 5,
746   CMPLTSI_OPCODE_Y0 = 4,
747   CMPLTSI_OPCODE_Y1 = 5,
748   CMPLTS_RRR_0_OPCODE_X0 = 10,
749   CMPLTS_RRR_0_OPCODE_X1 = 10,
750   CMPLTS_RRR_2_OPCODE_Y0 = 2,
751   CMPLTS_RRR_2_OPCODE_Y1 = 2,
752   CMPLTUI_IMM8_OPCODE_X0 = 6,
753   CMPLTUI_IMM8_OPCODE_X1 = 6,
754   CMPLTU_RRR_0_OPCODE_X0 = 11,
755   CMPLTU_RRR_0_OPCODE_X1 = 11,
756   CMPLTU_RRR_2_OPCODE_Y0 = 3,
757   CMPLTU_RRR_2_OPCODE_Y1 = 3,
758   CMPNE_RRR_0_OPCODE_X0 = 12,
759   CMPNE_RRR_0_OPCODE_X1 = 12,
760   CMPNE_RRR_3_OPCODE_Y0 = 1,
761   CMPNE_RRR_3_OPCODE_Y1 = 3,
762   CMULAF_RRR_0_OPCODE_X0 = 13,
763   CMULA_RRR_0_OPCODE_X0 = 14,
764   CMULFR_RRR_0_OPCODE_X0 = 15,
765   CMULF_RRR_0_OPCODE_X0 = 16,
766   CMULHR_RRR_0_OPCODE_X0 = 17,
767   CMULH_RRR_0_OPCODE_X0 = 18,
768   CMUL_RRR_0_OPCODE_X0 = 19,
769   CNTLZ_UNARY_OPCODE_X0 = 1,
770   CNTLZ_UNARY_OPCODE_Y0 = 1,
771   CNTTZ_UNARY_OPCODE_X0 = 2,
772   CNTTZ_UNARY_OPCODE_Y0 = 2,
773   CRC32_32_RRR_0_OPCODE_X0 = 20,
774   CRC32_8_RRR_0_OPCODE_X0 = 21,
775   DBLALIGN2_RRR_0_OPCODE_X0 = 22,
776   DBLALIGN2_RRR_0_OPCODE_X1 = 13,
777   DBLALIGN4_RRR_0_OPCODE_X0 = 23,
778   DBLALIGN4_RRR_0_OPCODE_X1 = 14,
779   DBLALIGN6_RRR_0_OPCODE_X0 = 24,
780   DBLALIGN6_RRR_0_OPCODE_X1 = 15,
781   DBLALIGN_RRR_0_OPCODE_X0 = 25,
782   DRAIN_UNARY_OPCODE_X1 = 1,
783   DTLBPR_UNARY_OPCODE_X1 = 2,
784   EXCH4_RRR_0_OPCODE_X1 = 16,
785   EXCH_RRR_0_OPCODE_X1 = 17,
786   FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
787   FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
788   FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
789   FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
790   FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
791   FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
792   FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
793   FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
794   FETCHADD4_RRR_0_OPCODE_X1 = 18,
795   FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
796   FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
797   FETCHADD_RRR_0_OPCODE_X1 = 21,
798   FETCHAND4_RRR_0_OPCODE_X1 = 22,
799   FETCHAND_RRR_0_OPCODE_X1 = 23,
800   FETCHOR4_RRR_0_OPCODE_X1 = 24,
801   FETCHOR_RRR_0_OPCODE_X1 = 25,
802   FINV_UNARY_OPCODE_X1 = 3,
803   FLUSHWB_UNARY_OPCODE_X1 = 4,
804   FLUSH_UNARY_OPCODE_X1 = 5,
805   FNOP_UNARY_OPCODE_X0 = 3,
806   FNOP_UNARY_OPCODE_X1 = 6,
807   FNOP_UNARY_OPCODE_Y0 = 3,
808   FNOP_UNARY_OPCODE_Y1 = 8,
809   FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
810   FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
811   FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
812   FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
813   FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
814   FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
815   FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
816   FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
817   ICOH_UNARY_OPCODE_X1 = 7,
818   ILL_UNARY_OPCODE_X1 = 8,
819   ILL_UNARY_OPCODE_Y1 = 9,
820   IMM8_OPCODE_X0 = 4,
821   IMM8_OPCODE_X1 = 3,
822   INV_UNARY_OPCODE_X1 = 9,
823   IRET_UNARY_OPCODE_X1 = 10,
824   JALRP_UNARY_OPCODE_X1 = 11,
825   JALRP_UNARY_OPCODE_Y1 = 10,
826   JALR_UNARY_OPCODE_X1 = 12,
827   JALR_UNARY_OPCODE_Y1 = 11,
828   JAL_JUMP_OPCODE_X1 = 0,
829   JRP_UNARY_OPCODE_X1 = 13,
830   JRP_UNARY_OPCODE_Y1 = 12,
831   JR_UNARY_OPCODE_X1 = 14,
832   JR_UNARY_OPCODE_Y1 = 13,
833   JUMP_OPCODE_X1 = 4,
834   J_JUMP_OPCODE_X1 = 1,
835   LD1S_ADD_IMM8_OPCODE_X1 = 7,
836   LD1S_OPCODE_Y2 = 0,
837   LD1S_UNARY_OPCODE_X1 = 15,
838   LD1U_ADD_IMM8_OPCODE_X1 = 8,
839   LD1U_OPCODE_Y2 = 1,
840   LD1U_UNARY_OPCODE_X1 = 16,
841   LD2S_ADD_IMM8_OPCODE_X1 = 9,
842   LD2S_OPCODE_Y2 = 2,
843   LD2S_UNARY_OPCODE_X1 = 17,
844   LD2U_ADD_IMM8_OPCODE_X1 = 10,
845   LD2U_OPCODE_Y2 = 3,
846   LD2U_UNARY_OPCODE_X1 = 18,
847   LD4S_ADD_IMM8_OPCODE_X1 = 11,
848   LD4S_OPCODE_Y2 = 1,
849   LD4S_UNARY_OPCODE_X1 = 19,
850   LD4U_ADD_IMM8_OPCODE_X1 = 12,
851   LD4U_OPCODE_Y2 = 2,
852   LD4U_UNARY_OPCODE_X1 = 20,
853   LDNA_UNARY_OPCODE_X1 = 21,
854   LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
855   LDNT1S_UNARY_OPCODE_X1 = 22,
856   LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
857   LDNT1U_UNARY_OPCODE_X1 = 23,
858   LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
859   LDNT2S_UNARY_OPCODE_X1 = 24,
860   LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
861   LDNT2U_UNARY_OPCODE_X1 = 25,
862   LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
863   LDNT4S_UNARY_OPCODE_X1 = 26,
864   LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
865   LDNT4U_UNARY_OPCODE_X1 = 27,
866   LDNT_ADD_IMM8_OPCODE_X1 = 19,
867   LDNT_UNARY_OPCODE_X1 = 28,
868   LD_ADD_IMM8_OPCODE_X1 = 20,
869   LD_OPCODE_Y2 = 3,
870   LD_UNARY_OPCODE_X1 = 29,
871   LNK_UNARY_OPCODE_X1 = 30,
872   LNK_UNARY_OPCODE_Y1 = 14,
873   LWNA_ADD_IMM8_OPCODE_X1 = 21,
874   MFSPR_IMM8_OPCODE_X1 = 22,
875   MF_UNARY_OPCODE_X1 = 31,
876   MM_BF_OPCODE_X0 = 7,
877   MNZ_RRR_0_OPCODE_X0 = 40,
878   MNZ_RRR_0_OPCODE_X1 = 26,
879   MNZ_RRR_4_OPCODE_Y0 = 2,
880   MNZ_RRR_4_OPCODE_Y1 = 2,
881   MODE_OPCODE_YA2 = 1,
882   MODE_OPCODE_YB2 = 2,
883   MODE_OPCODE_YC2 = 3,
884   MTSPR_IMM8_OPCODE_X1 = 23,
885   MULAX_RRR_0_OPCODE_X0 = 41,
886   MULAX_RRR_3_OPCODE_Y0 = 2,
887   MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
888   MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
889   MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
890   MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
891   MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
892   MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
893   MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
894   MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
895   MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
896   MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
897   MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
898   MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
899   MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
900   MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
901   MULX_RRR_0_OPCODE_X0 = 52,
902   MULX_RRR_3_OPCODE_Y0 = 3,
903   MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
904   MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
905   MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
906   MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
907   MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
908   MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
909   MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
910   MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
911   MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
912   MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
913   MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
914   MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
915   MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
916   MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
917   MZ_RRR_0_OPCODE_X0 = 63,
918   MZ_RRR_0_OPCODE_X1 = 27,
919   MZ_RRR_4_OPCODE_Y0 = 3,
920   MZ_RRR_4_OPCODE_Y1 = 3,
921   NAP_UNARY_OPCODE_X1 = 32,
922   NOP_UNARY_OPCODE_X0 = 5,
923   NOP_UNARY_OPCODE_X1 = 33,
924   NOP_UNARY_OPCODE_Y0 = 5,
925   NOP_UNARY_OPCODE_Y1 = 15,
926   NOR_RRR_0_OPCODE_X0 = 64,
927   NOR_RRR_0_OPCODE_X1 = 28,
928   NOR_RRR_5_OPCODE_Y0 = 1,
929   NOR_RRR_5_OPCODE_Y1 = 1,
930   ORI_IMM8_OPCODE_X0 = 7,
931   ORI_IMM8_OPCODE_X1 = 24,
932   OR_RRR_0_OPCODE_X0 = 65,
933   OR_RRR_0_OPCODE_X1 = 29,
934   OR_RRR_5_OPCODE_Y0 = 2,
935   OR_RRR_5_OPCODE_Y1 = 2,
936   PCNT_UNARY_OPCODE_X0 = 6,
937   PCNT_UNARY_OPCODE_Y0 = 6,
938   REVBITS_UNARY_OPCODE_X0 = 7,
939   REVBITS_UNARY_OPCODE_Y0 = 7,
940   REVBYTES_UNARY_OPCODE_X0 = 8,
941   REVBYTES_UNARY_OPCODE_Y0 = 8,
942   ROTLI_SHIFT_OPCODE_X0 = 1,
943   ROTLI_SHIFT_OPCODE_X1 = 1,
944   ROTLI_SHIFT_OPCODE_Y0 = 0,
945   ROTLI_SHIFT_OPCODE_Y1 = 0,
946   ROTL_RRR_0_OPCODE_X0 = 66,
947   ROTL_RRR_0_OPCODE_X1 = 30,
948   ROTL_RRR_6_OPCODE_Y0 = 0,
949   ROTL_RRR_6_OPCODE_Y1 = 0,
950   RRR_0_OPCODE_X0 = 5,
951   RRR_0_OPCODE_X1 = 5,
952   RRR_0_OPCODE_Y0 = 5,
953   RRR_0_OPCODE_Y1 = 6,
954   RRR_1_OPCODE_Y0 = 6,
955   RRR_1_OPCODE_Y1 = 7,
956   RRR_2_OPCODE_Y0 = 7,
957   RRR_2_OPCODE_Y1 = 8,
958   RRR_3_OPCODE_Y0 = 8,
959   RRR_3_OPCODE_Y1 = 9,
960   RRR_4_OPCODE_Y0 = 9,
961   RRR_4_OPCODE_Y1 = 10,
962   RRR_5_OPCODE_Y0 = 10,
963   RRR_5_OPCODE_Y1 = 11,
964   RRR_6_OPCODE_Y0 = 11,
965   RRR_6_OPCODE_Y1 = 12,
966   RRR_7_OPCODE_Y0 = 12,
967   RRR_7_OPCODE_Y1 = 13,
968   RRR_8_OPCODE_Y0 = 13,
969   RRR_9_OPCODE_Y0 = 14,
970   SHIFT_OPCODE_X0 = 6,
971   SHIFT_OPCODE_X1 = 6,
972   SHIFT_OPCODE_Y0 = 15,
973   SHIFT_OPCODE_Y1 = 14,
974   SHL16INSLI_OPCODE_X0 = 7,
975   SHL16INSLI_OPCODE_X1 = 7,
976   SHL1ADDX_RRR_0_OPCODE_X0 = 67,
977   SHL1ADDX_RRR_0_OPCODE_X1 = 31,
978   SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
979   SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
980   SHL1ADD_RRR_0_OPCODE_X0 = 68,
981   SHL1ADD_RRR_0_OPCODE_X1 = 32,
982   SHL1ADD_RRR_1_OPCODE_Y0 = 0,
983   SHL1ADD_RRR_1_OPCODE_Y1 = 0,
984   SHL2ADDX_RRR_0_OPCODE_X0 = 69,
985   SHL2ADDX_RRR_0_OPCODE_X1 = 33,
986   SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
987   SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
988   SHL2ADD_RRR_0_OPCODE_X0 = 70,
989   SHL2ADD_RRR_0_OPCODE_X1 = 34,
990   SHL2ADD_RRR_1_OPCODE_Y0 = 1,
991   SHL2ADD_RRR_1_OPCODE_Y1 = 1,
992   SHL3ADDX_RRR_0_OPCODE_X0 = 71,
993   SHL3ADDX_RRR_0_OPCODE_X1 = 35,
994   SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
995   SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
996   SHL3ADD_RRR_0_OPCODE_X0 = 72,
997   SHL3ADD_RRR_0_OPCODE_X1 = 36,
998   SHL3ADD_RRR_1_OPCODE_Y0 = 2,
999   SHL3ADD_RRR_1_OPCODE_Y1 = 2,
1000   SHLI_SHIFT_OPCODE_X0 = 2,
1001   SHLI_SHIFT_OPCODE_X1 = 2,
1002   SHLI_SHIFT_OPCODE_Y0 = 1,
1003   SHLI_SHIFT_OPCODE_Y1 = 1,
1004   SHLXI_SHIFT_OPCODE_X0 = 3,
1005   SHLXI_SHIFT_OPCODE_X1 = 3,
1006   SHLX_RRR_0_OPCODE_X0 = 73,
1007   SHLX_RRR_0_OPCODE_X1 = 37,
1008   SHL_RRR_0_OPCODE_X0 = 74,
1009   SHL_RRR_0_OPCODE_X1 = 38,
1010   SHL_RRR_6_OPCODE_Y0 = 1,
1011   SHL_RRR_6_OPCODE_Y1 = 1,
1012   SHRSI_SHIFT_OPCODE_X0 = 4,
1013   SHRSI_SHIFT_OPCODE_X1 = 4,
1014   SHRSI_SHIFT_OPCODE_Y0 = 2,
1015   SHRSI_SHIFT_OPCODE_Y1 = 2,
1016   SHRS_RRR_0_OPCODE_X0 = 75,
1017   SHRS_RRR_0_OPCODE_X1 = 39,
1018   SHRS_RRR_6_OPCODE_Y0 = 2,
1019   SHRS_RRR_6_OPCODE_Y1 = 2,
1020   SHRUI_SHIFT_OPCODE_X0 = 5,
1021   SHRUI_SHIFT_OPCODE_X1 = 5,
1022   SHRUI_SHIFT_OPCODE_Y0 = 3,
1023   SHRUI_SHIFT_OPCODE_Y1 = 3,
1024   SHRUXI_SHIFT_OPCODE_X0 = 6,
1025   SHRUXI_SHIFT_OPCODE_X1 = 6,
1026   SHRUX_RRR_0_OPCODE_X0 = 76,
1027   SHRUX_RRR_0_OPCODE_X1 = 40,
1028   SHRU_RRR_0_OPCODE_X0 = 77,
1029   SHRU_RRR_0_OPCODE_X1 = 41,
1030   SHRU_RRR_6_OPCODE_Y0 = 3,
1031   SHRU_RRR_6_OPCODE_Y1 = 3,
1032   SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
1033   ST1_ADD_IMM8_OPCODE_X1 = 25,
1034   ST1_OPCODE_Y2 = 0,
1035   ST1_RRR_0_OPCODE_X1 = 42,
1036   ST2_ADD_IMM8_OPCODE_X1 = 26,
1037   ST2_OPCODE_Y2 = 1,
1038   ST2_RRR_0_OPCODE_X1 = 43,
1039   ST4_ADD_IMM8_OPCODE_X1 = 27,
1040   ST4_OPCODE_Y2 = 2,
1041   ST4_RRR_0_OPCODE_X1 = 44,
1042   STNT1_ADD_IMM8_OPCODE_X1 = 28,
1043   STNT1_RRR_0_OPCODE_X1 = 45,
1044   STNT2_ADD_IMM8_OPCODE_X1 = 29,
1045   STNT2_RRR_0_OPCODE_X1 = 46,
1046   STNT4_ADD_IMM8_OPCODE_X1 = 30,
1047   STNT4_RRR_0_OPCODE_X1 = 47,
1048   STNT_ADD_IMM8_OPCODE_X1 = 31,
1049   STNT_RRR_0_OPCODE_X1 = 48,
1050   ST_ADD_IMM8_OPCODE_X1 = 32,
1051   ST_OPCODE_Y2 = 3,
1052   ST_RRR_0_OPCODE_X1 = 49,
1053   SUBXSC_RRR_0_OPCODE_X0 = 79,
1054   SUBXSC_RRR_0_OPCODE_X1 = 50,
1055   SUBX_RRR_0_OPCODE_X0 = 80,
1056   SUBX_RRR_0_OPCODE_X1 = 51,
1057   SUBX_RRR_0_OPCODE_Y0 = 2,
1058   SUBX_RRR_0_OPCODE_Y1 = 2,
1059   SUB_RRR_0_OPCODE_X0 = 81,
1060   SUB_RRR_0_OPCODE_X1 = 52,
1061   SUB_RRR_0_OPCODE_Y0 = 3,
1062   SUB_RRR_0_OPCODE_Y1 = 3,
1063   SWINT0_UNARY_OPCODE_X1 = 34,
1064   SWINT1_UNARY_OPCODE_X1 = 35,
1065   SWINT2_UNARY_OPCODE_X1 = 36,
1066   SWINT3_UNARY_OPCODE_X1 = 37,
1067   TBLIDXB0_UNARY_OPCODE_X0 = 9,
1068   TBLIDXB0_UNARY_OPCODE_Y0 = 9,
1069   TBLIDXB1_UNARY_OPCODE_X0 = 10,
1070   TBLIDXB1_UNARY_OPCODE_Y0 = 10,
1071   TBLIDXB2_UNARY_OPCODE_X0 = 11,
1072   TBLIDXB2_UNARY_OPCODE_Y0 = 11,
1073   TBLIDXB3_UNARY_OPCODE_X0 = 12,
1074   TBLIDXB3_UNARY_OPCODE_Y0 = 12,
1075   UNARY_RRR_0_OPCODE_X0 = 82,
1076   UNARY_RRR_0_OPCODE_X1 = 53,
1077   UNARY_RRR_1_OPCODE_Y0 = 3,
1078   UNARY_RRR_1_OPCODE_Y1 = 3,
1079   V1ADDI_IMM8_OPCODE_X0 = 8,
1080   V1ADDI_IMM8_OPCODE_X1 = 33,
1081   V1ADDUC_RRR_0_OPCODE_X0 = 83,
1082   V1ADDUC_RRR_0_OPCODE_X1 = 54,
1083   V1ADD_RRR_0_OPCODE_X0 = 84,
1084   V1ADD_RRR_0_OPCODE_X1 = 55,
1085   V1ADIFFU_RRR_0_OPCODE_X0 = 85,
1086   V1AVGU_RRR_0_OPCODE_X0 = 86,
1087   V1CMPEQI_IMM8_OPCODE_X0 = 9,
1088   V1CMPEQI_IMM8_OPCODE_X1 = 34,
1089   V1CMPEQ_RRR_0_OPCODE_X0 = 87,
1090   V1CMPEQ_RRR_0_OPCODE_X1 = 56,
1091   V1CMPLES_RRR_0_OPCODE_X0 = 88,
1092   V1CMPLES_RRR_0_OPCODE_X1 = 57,
1093   V1CMPLEU_RRR_0_OPCODE_X0 = 89,
1094   V1CMPLEU_RRR_0_OPCODE_X1 = 58,
1095   V1CMPLTSI_IMM8_OPCODE_X0 = 10,
1096   V1CMPLTSI_IMM8_OPCODE_X1 = 35,
1097   V1CMPLTS_RRR_0_OPCODE_X0 = 90,
1098   V1CMPLTS_RRR_0_OPCODE_X1 = 59,
1099   V1CMPLTUI_IMM8_OPCODE_X0 = 11,
1100   V1CMPLTUI_IMM8_OPCODE_X1 = 36,
1101   V1CMPLTU_RRR_0_OPCODE_X0 = 91,
1102   V1CMPLTU_RRR_0_OPCODE_X1 = 60,
1103   V1CMPNE_RRR_0_OPCODE_X0 = 92,
1104   V1CMPNE_RRR_0_OPCODE_X1 = 61,
1105   V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
1106   V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
1107   V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
1108   V1DDOTPU_RRR_0_OPCODE_X0 = 162,
1109   V1DOTPA_RRR_0_OPCODE_X0 = 95,
1110   V1DOTPUA_RRR_0_OPCODE_X0 = 163,
1111   V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
1112   V1DOTPUS_RRR_0_OPCODE_X0 = 97,
1113   V1DOTPU_RRR_0_OPCODE_X0 = 164,
1114   V1DOTP_RRR_0_OPCODE_X0 = 98,
1115   V1INT_H_RRR_0_OPCODE_X0 = 99,
1116   V1INT_H_RRR_0_OPCODE_X1 = 62,
1117   V1INT_L_RRR_0_OPCODE_X0 = 100,
1118   V1INT_L_RRR_0_OPCODE_X1 = 63,
1119   V1MAXUI_IMM8_OPCODE_X0 = 12,
1120   V1MAXUI_IMM8_OPCODE_X1 = 37,
1121   V1MAXU_RRR_0_OPCODE_X0 = 101,
1122   V1MAXU_RRR_0_OPCODE_X1 = 64,
1123   V1MINUI_IMM8_OPCODE_X0 = 13,
1124   V1MINUI_IMM8_OPCODE_X1 = 38,
1125   V1MINU_RRR_0_OPCODE_X0 = 102,
1126   V1MINU_RRR_0_OPCODE_X1 = 65,
1127   V1MNZ_RRR_0_OPCODE_X0 = 103,
1128   V1MNZ_RRR_0_OPCODE_X1 = 66,
1129   V1MULTU_RRR_0_OPCODE_X0 = 104,
1130   V1MULUS_RRR_0_OPCODE_X0 = 105,
1131   V1MULU_RRR_0_OPCODE_X0 = 106,
1132   V1MZ_RRR_0_OPCODE_X0 = 107,
1133   V1MZ_RRR_0_OPCODE_X1 = 67,
1134   V1SADAU_RRR_0_OPCODE_X0 = 108,
1135   V1SADU_RRR_0_OPCODE_X0 = 109,
1136   V1SHLI_SHIFT_OPCODE_X0 = 7,
1137   V1SHLI_SHIFT_OPCODE_X1 = 7,
1138   V1SHL_RRR_0_OPCODE_X0 = 110,
1139   V1SHL_RRR_0_OPCODE_X1 = 68,
1140   V1SHRSI_SHIFT_OPCODE_X0 = 8,
1141   V1SHRSI_SHIFT_OPCODE_X1 = 8,
1142   V1SHRS_RRR_0_OPCODE_X0 = 111,
1143   V1SHRS_RRR_0_OPCODE_X1 = 69,
1144   V1SHRUI_SHIFT_OPCODE_X0 = 9,
1145   V1SHRUI_SHIFT_OPCODE_X1 = 9,
1146   V1SHRU_RRR_0_OPCODE_X0 = 112,
1147   V1SHRU_RRR_0_OPCODE_X1 = 70,
1148   V1SUBUC_RRR_0_OPCODE_X0 = 113,
1149   V1SUBUC_RRR_0_OPCODE_X1 = 71,
1150   V1SUB_RRR_0_OPCODE_X0 = 114,
1151   V1SUB_RRR_0_OPCODE_X1 = 72,
1152   V2ADDI_IMM8_OPCODE_X0 = 14,
1153   V2ADDI_IMM8_OPCODE_X1 = 39,
1154   V2ADDSC_RRR_0_OPCODE_X0 = 115,
1155   V2ADDSC_RRR_0_OPCODE_X1 = 73,
1156   V2ADD_RRR_0_OPCODE_X0 = 116,
1157   V2ADD_RRR_0_OPCODE_X1 = 74,
1158   V2ADIFFS_RRR_0_OPCODE_X0 = 117,
1159   V2AVGS_RRR_0_OPCODE_X0 = 118,
1160   V2CMPEQI_IMM8_OPCODE_X0 = 15,
1161   V2CMPEQI_IMM8_OPCODE_X1 = 40,
1162   V2CMPEQ_RRR_0_OPCODE_X0 = 119,
1163   V2CMPEQ_RRR_0_OPCODE_X1 = 75,
1164   V2CMPLES_RRR_0_OPCODE_X0 = 120,
1165   V2CMPLES_RRR_0_OPCODE_X1 = 76,
1166   V2CMPLEU_RRR_0_OPCODE_X0 = 121,
1167   V2CMPLEU_RRR_0_OPCODE_X1 = 77,
1168   V2CMPLTSI_IMM8_OPCODE_X0 = 16,
1169   V2CMPLTSI_IMM8_OPCODE_X1 = 41,
1170   V2CMPLTS_RRR_0_OPCODE_X0 = 122,
1171   V2CMPLTS_RRR_0_OPCODE_X1 = 78,
1172   V2CMPLTUI_IMM8_OPCODE_X0 = 17,
1173   V2CMPLTUI_IMM8_OPCODE_X1 = 42,
1174   V2CMPLTU_RRR_0_OPCODE_X0 = 123,
1175   V2CMPLTU_RRR_0_OPCODE_X1 = 79,
1176   V2CMPNE_RRR_0_OPCODE_X0 = 124,
1177   V2CMPNE_RRR_0_OPCODE_X1 = 80,
1178   V2DOTPA_RRR_0_OPCODE_X0 = 125,
1179   V2DOTP_RRR_0_OPCODE_X0 = 126,
1180   V2INT_H_RRR_0_OPCODE_X0 = 127,
1181   V2INT_H_RRR_0_OPCODE_X1 = 81,
1182   V2INT_L_RRR_0_OPCODE_X0 = 128,
1183   V2INT_L_RRR_0_OPCODE_X1 = 82,
1184   V2MAXSI_IMM8_OPCODE_X0 = 18,
1185   V2MAXSI_IMM8_OPCODE_X1 = 43,
1186   V2MAXS_RRR_0_OPCODE_X0 = 129,
1187   V2MAXS_RRR_0_OPCODE_X1 = 83,
1188   V2MINSI_IMM8_OPCODE_X0 = 19,
1189   V2MINSI_IMM8_OPCODE_X1 = 44,
1190   V2MINS_RRR_0_OPCODE_X0 = 130,
1191   V2MINS_RRR_0_OPCODE_X1 = 84,
1192   V2MNZ_RRR_0_OPCODE_X0 = 131,
1193   V2MNZ_RRR_0_OPCODE_X1 = 85,
1194   V2MULFSC_RRR_0_OPCODE_X0 = 132,
1195   V2MULS_RRR_0_OPCODE_X0 = 133,
1196   V2MULTS_RRR_0_OPCODE_X0 = 134,
1197   V2MZ_RRR_0_OPCODE_X0 = 135,
1198   V2MZ_RRR_0_OPCODE_X1 = 86,
1199   V2PACKH_RRR_0_OPCODE_X0 = 136,
1200   V2PACKH_RRR_0_OPCODE_X1 = 87,
1201   V2PACKL_RRR_0_OPCODE_X0 = 137,
1202   V2PACKL_RRR_0_OPCODE_X1 = 88,
1203   V2PACKUC_RRR_0_OPCODE_X0 = 138,
1204   V2PACKUC_RRR_0_OPCODE_X1 = 89,
1205   V2SADAS_RRR_0_OPCODE_X0 = 139,
1206   V2SADAU_RRR_0_OPCODE_X0 = 140,
1207   V2SADS_RRR_0_OPCODE_X0 = 141,
1208   V2SADU_RRR_0_OPCODE_X0 = 142,
1209   V2SHLI_SHIFT_OPCODE_X0 = 10,
1210   V2SHLI_SHIFT_OPCODE_X1 = 10,
1211   V2SHLSC_RRR_0_OPCODE_X0 = 143,
1212   V2SHLSC_RRR_0_OPCODE_X1 = 90,
1213   V2SHL_RRR_0_OPCODE_X0 = 144,
1214   V2SHL_RRR_0_OPCODE_X1 = 91,
1215   V2SHRSI_SHIFT_OPCODE_X0 = 11,
1216   V2SHRSI_SHIFT_OPCODE_X1 = 11,
1217   V2SHRS_RRR_0_OPCODE_X0 = 145,
1218   V2SHRS_RRR_0_OPCODE_X1 = 92,
1219   V2SHRUI_SHIFT_OPCODE_X0 = 12,
1220   V2SHRUI_SHIFT_OPCODE_X1 = 12,
1221   V2SHRU_RRR_0_OPCODE_X0 = 146,
1222   V2SHRU_RRR_0_OPCODE_X1 = 93,
1223   V2SUBSC_RRR_0_OPCODE_X0 = 147,
1224   V2SUBSC_RRR_0_OPCODE_X1 = 94,
1225   V2SUB_RRR_0_OPCODE_X0 = 148,
1226   V2SUB_RRR_0_OPCODE_X1 = 95,
1227   V4ADDSC_RRR_0_OPCODE_X0 = 149,
1228   V4ADDSC_RRR_0_OPCODE_X1 = 96,
1229   V4ADD_RRR_0_OPCODE_X0 = 150,
1230   V4ADD_RRR_0_OPCODE_X1 = 97,
1231   V4INT_H_RRR_0_OPCODE_X0 = 151,
1232   V4INT_H_RRR_0_OPCODE_X1 = 98,
1233   V4INT_L_RRR_0_OPCODE_X0 = 152,
1234   V4INT_L_RRR_0_OPCODE_X1 = 99,
1235   V4PACKSC_RRR_0_OPCODE_X0 = 153,
1236   V4PACKSC_RRR_0_OPCODE_X1 = 100,
1237   V4SHLSC_RRR_0_OPCODE_X0 = 154,
1238   V4SHLSC_RRR_0_OPCODE_X1 = 101,
1239   V4SHL_RRR_0_OPCODE_X0 = 155,
1240   V4SHL_RRR_0_OPCODE_X1 = 102,
1241   V4SHRS_RRR_0_OPCODE_X0 = 156,
1242   V4SHRS_RRR_0_OPCODE_X1 = 103,
1243   V4SHRU_RRR_0_OPCODE_X0 = 157,
1244   V4SHRU_RRR_0_OPCODE_X1 = 104,
1245   V4SUBSC_RRR_0_OPCODE_X0 = 158,
1246   V4SUBSC_RRR_0_OPCODE_X1 = 105,
1247   V4SUB_RRR_0_OPCODE_X0 = 159,
1248   V4SUB_RRR_0_OPCODE_X1 = 106,
1249   WH64_UNARY_OPCODE_X1 = 38,
1250   XORI_IMM8_OPCODE_X0 = 20,
1251   XORI_IMM8_OPCODE_X1 = 45,
1252   XOR_RRR_0_OPCODE_X0 = 160,
1253   XOR_RRR_0_OPCODE_X1 = 107,
1254   XOR_RRR_5_OPCODE_Y0 = 3,
1255   XOR_RRR_5_OPCODE_Y1 = 3
1256 };
1257 
1258 static __inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)1259 get_BFEnd_X0(tilegx_bundle_bits num)
1260 {
1261   const unsigned int n = (unsigned int)num;
1262   return (((n >> 12)) & 0x3f);
1263 }
1264 
1265 static __inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)1266 get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
1267 {
1268   const unsigned int n = (unsigned int)num;
1269   return (((n >> 24)) & 0xf);
1270 }
1271 
1272 static __inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)1273 get_BFStart_X0(tilegx_bundle_bits num)
1274 {
1275   const unsigned int n = (unsigned int)num;
1276   return (((n >> 18)) & 0x3f);
1277 }
1278 
1279 static __inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)1280 get_BrOff_X1(tilegx_bundle_bits n)
1281 {
1282   return (((unsigned int)(n >> 31)) & 0x0000003f) |
1283          (((unsigned int)(n >> 37)) & 0x0001ffc0);
1284 }
1285 
1286 static __inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)1287 get_BrType_X1(tilegx_bundle_bits n)
1288 {
1289   return (((unsigned int)(n >> 54)) & 0x1f);
1290 }
1291 
1292 static __inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)1293 get_Dest_Imm8_X1(tilegx_bundle_bits n)
1294 {
1295   return (((unsigned int)(n >> 31)) & 0x0000003f) |
1296          (((unsigned int)(n >> 43)) & 0x000000c0);
1297 }
1298 
1299 static __inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)1300 get_Dest_X0(tilegx_bundle_bits num)
1301 {
1302   const unsigned int n = (unsigned int)num;
1303   return (((n >> 0)) & 0x3f);
1304 }
1305 
1306 static __inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)1307 get_Dest_X1(tilegx_bundle_bits n)
1308 {
1309   return (((unsigned int)(n >> 31)) & 0x3f);
1310 }
1311 
1312 static __inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)1313 get_Dest_Y0(tilegx_bundle_bits num)
1314 {
1315   const unsigned int n = (unsigned int)num;
1316   return (((n >> 0)) & 0x3f);
1317 }
1318 
1319 static __inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)1320 get_Dest_Y1(tilegx_bundle_bits n)
1321 {
1322   return (((unsigned int)(n >> 31)) & 0x3f);
1323 }
1324 
1325 static __inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)1326 get_Imm16_X0(tilegx_bundle_bits num)
1327 {
1328   const unsigned int n = (unsigned int)num;
1329   return (((n >> 12)) & 0xffff);
1330 }
1331 
1332 static __inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)1333 get_Imm16_X1(tilegx_bundle_bits n)
1334 {
1335   return (((unsigned int)(n >> 43)) & 0xffff);
1336 }
1337 
1338 static __inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)1339 get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
1340 {
1341   const unsigned int n = (unsigned int)num;
1342   return (((n >> 20)) & 0xff);
1343 }
1344 
1345 static __inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)1346 get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
1347 {
1348   return (((unsigned int)(n >> 51)) & 0xff);
1349 }
1350 
1351 static __inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)1352 get_Imm8_X0(tilegx_bundle_bits num)
1353 {
1354   const unsigned int n = (unsigned int)num;
1355   return (((n >> 12)) & 0xff);
1356 }
1357 
1358 static __inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)1359 get_Imm8_X1(tilegx_bundle_bits n)
1360 {
1361   return (((unsigned int)(n >> 43)) & 0xff);
1362 }
1363 
1364 static __inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)1365 get_Imm8_Y0(tilegx_bundle_bits num)
1366 {
1367   const unsigned int n = (unsigned int)num;
1368   return (((n >> 12)) & 0xff);
1369 }
1370 
1371 static __inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)1372 get_Imm8_Y1(tilegx_bundle_bits n)
1373 {
1374   return (((unsigned int)(n >> 43)) & 0xff);
1375 }
1376 
1377 static __inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)1378 get_JumpOff_X1(tilegx_bundle_bits n)
1379 {
1380   return (((unsigned int)(n >> 31)) & 0x7ffffff);
1381 }
1382 
1383 static __inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)1384 get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
1385 {
1386   return (((unsigned int)(n >> 58)) & 0x1);
1387 }
1388 
1389 static __inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)1390 get_MF_Imm14_X1(tilegx_bundle_bits n)
1391 {
1392   return (((unsigned int)(n >> 37)) & 0x3fff);
1393 }
1394 
1395 static __inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)1396 get_MT_Imm14_X1(tilegx_bundle_bits n)
1397 {
1398   return (((unsigned int)(n >> 31)) & 0x0000003f) |
1399          (((unsigned int)(n >> 37)) & 0x00003fc0);
1400 }
1401 
1402 static __inline unsigned int
get_Mode(tilegx_bundle_bits n)1403 get_Mode(tilegx_bundle_bits n)
1404 {
1405   return (((unsigned int)(n >> 62)) & 0x3);
1406 }
1407 
1408 static __inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)1409 get_Opcode_X0(tilegx_bundle_bits num)
1410 {
1411   const unsigned int n = (unsigned int)num;
1412   return (((n >> 28)) & 0x7);
1413 }
1414 
1415 static __inline unsigned int
get_Opcode_X1(tilegx_bundle_bits n)1416 get_Opcode_X1(tilegx_bundle_bits n)
1417 {
1418   return (((unsigned int)(n >> 59)) & 0x7);
1419 }
1420 
1421 static __inline unsigned int
get_Opcode_Y0(tilegx_bundle_bits num)1422 get_Opcode_Y0(tilegx_bundle_bits num)
1423 {
1424   const unsigned int n = (unsigned int)num;
1425   return (((n >> 27)) & 0xf);
1426 }
1427 
1428 static __inline unsigned int
get_Opcode_Y1(tilegx_bundle_bits n)1429 get_Opcode_Y1(tilegx_bundle_bits n)
1430 {
1431   return (((unsigned int)(n >> 58)) & 0xf);
1432 }
1433 
1434 static __inline unsigned int
get_Opcode_Y2(tilegx_bundle_bits n)1435 get_Opcode_Y2(tilegx_bundle_bits n)
1436 {
1437   return (((n >> 26)) & 0x00000001) |
1438          (((unsigned int)(n >> 56)) & 0x00000002);
1439 }
1440 
1441 static __inline unsigned int
get_RRROpcodeExtension_X0(tilegx_bundle_bits num)1442 get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
1443 {
1444   const unsigned int n = (unsigned int)num;
1445   return (((n >> 18)) & 0x3ff);
1446 }
1447 
1448 static __inline unsigned int
get_RRROpcodeExtension_X1(tilegx_bundle_bits n)1449 get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
1450 {
1451   return (((unsigned int)(n >> 49)) & 0x3ff);
1452 }
1453 
1454 static __inline unsigned int
get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)1455 get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
1456 {
1457   const unsigned int n = (unsigned int)num;
1458   return (((n >> 18)) & 0x3);
1459 }
1460 
1461 static __inline unsigned int
get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)1462 get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
1463 {
1464   return (((unsigned int)(n >> 49)) & 0x3);
1465 }
1466 
1467 static __inline unsigned int
get_ShAmt_X0(tilegx_bundle_bits num)1468 get_ShAmt_X0(tilegx_bundle_bits num)
1469 {
1470   const unsigned int n = (unsigned int)num;
1471   return (((n >> 12)) & 0x3f);
1472 }
1473 
1474 static __inline unsigned int
get_ShAmt_X1(tilegx_bundle_bits n)1475 get_ShAmt_X1(tilegx_bundle_bits n)
1476 {
1477   return (((unsigned int)(n >> 43)) & 0x3f);
1478 }
1479 
1480 static __inline unsigned int
get_ShAmt_Y0(tilegx_bundle_bits num)1481 get_ShAmt_Y0(tilegx_bundle_bits num)
1482 {
1483   const unsigned int n = (unsigned int)num;
1484   return (((n >> 12)) & 0x3f);
1485 }
1486 
1487 static __inline unsigned int
get_ShAmt_Y1(tilegx_bundle_bits n)1488 get_ShAmt_Y1(tilegx_bundle_bits n)
1489 {
1490   return (((unsigned int)(n >> 43)) & 0x3f);
1491 }
1492 
1493 static __inline unsigned int
get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)1494 get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
1495 {
1496   const unsigned int n = (unsigned int)num;
1497   return (((n >> 18)) & 0x3ff);
1498 }
1499 
1500 static __inline unsigned int
get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)1501 get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
1502 {
1503   return (((unsigned int)(n >> 49)) & 0x3ff);
1504 }
1505 
1506 static __inline unsigned int
get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)1507 get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
1508 {
1509   const unsigned int n = (unsigned int)num;
1510   return (((n >> 18)) & 0x3);
1511 }
1512 
1513 static __inline unsigned int
get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)1514 get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
1515 {
1516   return (((unsigned int)(n >> 49)) & 0x3);
1517 }
1518 
1519 static __inline unsigned int
get_SrcA_X0(tilegx_bundle_bits num)1520 get_SrcA_X0(tilegx_bundle_bits num)
1521 {
1522   const unsigned int n = (unsigned int)num;
1523   return (((n >> 6)) & 0x3f);
1524 }
1525 
1526 static __inline unsigned int
get_SrcA_X1(tilegx_bundle_bits n)1527 get_SrcA_X1(tilegx_bundle_bits n)
1528 {
1529   return (((unsigned int)(n >> 37)) & 0x3f);
1530 }
1531 
1532 static __inline unsigned int
get_SrcA_Y0(tilegx_bundle_bits num)1533 get_SrcA_Y0(tilegx_bundle_bits num)
1534 {
1535   const unsigned int n = (unsigned int)num;
1536   return (((n >> 6)) & 0x3f);
1537 }
1538 
1539 static __inline unsigned int
get_SrcA_Y1(tilegx_bundle_bits n)1540 get_SrcA_Y1(tilegx_bundle_bits n)
1541 {
1542   return (((unsigned int)(n >> 37)) & 0x3f);
1543 }
1544 
1545 static __inline unsigned int
get_SrcA_Y2(tilegx_bundle_bits num)1546 get_SrcA_Y2(tilegx_bundle_bits num)
1547 {
1548   const unsigned int n = (unsigned int)num;
1549   return (((n >> 20)) & 0x3f);
1550 }
1551 
1552 static __inline unsigned int
get_SrcBDest_Y2(tilegx_bundle_bits n)1553 get_SrcBDest_Y2(tilegx_bundle_bits n)
1554 {
1555   return (((unsigned int)(n >> 51)) & 0x3f);
1556 }
1557 
1558 static __inline unsigned int
get_SrcB_X0(tilegx_bundle_bits num)1559 get_SrcB_X0(tilegx_bundle_bits num)
1560 {
1561   const unsigned int n = (unsigned int)num;
1562   return (((n >> 12)) & 0x3f);
1563 }
1564 
1565 static __inline unsigned int
get_SrcB_X1(tilegx_bundle_bits n)1566 get_SrcB_X1(tilegx_bundle_bits n)
1567 {
1568   return (((unsigned int)(n >> 43)) & 0x3f);
1569 }
1570 
1571 static __inline unsigned int
get_SrcB_Y0(tilegx_bundle_bits num)1572 get_SrcB_Y0(tilegx_bundle_bits num)
1573 {
1574   const unsigned int n = (unsigned int)num;
1575   return (((n >> 12)) & 0x3f);
1576 }
1577 
1578 static __inline unsigned int
get_SrcB_Y1(tilegx_bundle_bits n)1579 get_SrcB_Y1(tilegx_bundle_bits n)
1580 {
1581   return (((unsigned int)(n >> 43)) & 0x3f);
1582 }
1583 
1584 static __inline unsigned int
get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)1585 get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
1586 {
1587   const unsigned int n = (unsigned int)num;
1588   return (((n >> 12)) & 0x3f);
1589 }
1590 
1591 static __inline unsigned int
get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)1592 get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
1593 {
1594   return (((unsigned int)(n >> 43)) & 0x3f);
1595 }
1596 
1597 static __inline unsigned int
get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)1598 get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
1599 {
1600   const unsigned int n = (unsigned int)num;
1601   return (((n >> 12)) & 0x3f);
1602 }
1603 
1604 static __inline unsigned int
get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)1605 get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
1606 {
1607   return (((unsigned int)(n >> 43)) & 0x3f);
1608 }
1609 
1610 static __inline int
sign_extend(int n,int num_bits)1611 sign_extend(int n, int num_bits)
1612 {
1613   int shift = (int)(sizeof(int) * 8 - num_bits);
1614   return (n << shift) >> shift;
1615 }
1616 
1617 static __inline tilegx_bundle_bits
create_BFEnd_X0(int num)1618 create_BFEnd_X0(int num)
1619 {
1620   const unsigned int n = (unsigned int)num;
1621   return ((n & 0x3f) << 12);
1622 }
1623 
1624 static __inline tilegx_bundle_bits
create_BFOpcodeExtension_X0(int num)1625 create_BFOpcodeExtension_X0(int num)
1626 {
1627   const unsigned int n = (unsigned int)num;
1628   return ((n & 0xf) << 24);
1629 }
1630 
1631 static __inline tilegx_bundle_bits
create_BFStart_X0(int num)1632 create_BFStart_X0(int num)
1633 {
1634   const unsigned int n = (unsigned int)num;
1635   return ((n & 0x3f) << 18);
1636 }
1637 
1638 static __inline tilegx_bundle_bits
create_BrOff_X1(int num)1639 create_BrOff_X1(int num)
1640 {
1641   const unsigned int n = (unsigned int)num;
1642   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
1643          (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
1644 }
1645 
1646 static __inline tilegx_bundle_bits
create_BrType_X1(int num)1647 create_BrType_X1(int num)
1648 {
1649   const unsigned int n = (unsigned int)num;
1650   return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
1651 }
1652 
1653 static __inline tilegx_bundle_bits
create_Dest_Imm8_X1(int num)1654 create_Dest_Imm8_X1(int num)
1655 {
1656   const unsigned int n = (unsigned int)num;
1657   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
1658          (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
1659 }
1660 
1661 static __inline tilegx_bundle_bits
create_Dest_X0(int num)1662 create_Dest_X0(int num)
1663 {
1664   const unsigned int n = (unsigned int)num;
1665   return ((n & 0x3f) << 0);
1666 }
1667 
1668 static __inline tilegx_bundle_bits
create_Dest_X1(int num)1669 create_Dest_X1(int num)
1670 {
1671   const unsigned int n = (unsigned int)num;
1672   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
1673 }
1674 
1675 static __inline tilegx_bundle_bits
create_Dest_Y0(int num)1676 create_Dest_Y0(int num)
1677 {
1678   const unsigned int n = (unsigned int)num;
1679   return ((n & 0x3f) << 0);
1680 }
1681 
1682 static __inline tilegx_bundle_bits
create_Dest_Y1(int num)1683 create_Dest_Y1(int num)
1684 {
1685   const unsigned int n = (unsigned int)num;
1686   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
1687 }
1688 
1689 static __inline tilegx_bundle_bits
create_Imm16_X0(int num)1690 create_Imm16_X0(int num)
1691 {
1692   const unsigned int n = (unsigned int)num;
1693   return ((n & 0xffff) << 12);
1694 }
1695 
1696 static __inline tilegx_bundle_bits
create_Imm16_X1(int num)1697 create_Imm16_X1(int num)
1698 {
1699   const unsigned int n = (unsigned int)num;
1700   return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
1701 }
1702 
1703 static __inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X0(int num)1704 create_Imm8OpcodeExtension_X0(int num)
1705 {
1706   const unsigned int n = (unsigned int)num;
1707   return ((n & 0xff) << 20);
1708 }
1709 
1710 static __inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X1(int num)1711 create_Imm8OpcodeExtension_X1(int num)
1712 {
1713   const unsigned int n = (unsigned int)num;
1714   return (((tilegx_bundle_bits)(n & 0xff)) << 51);
1715 }
1716 
1717 static __inline tilegx_bundle_bits
create_Imm8_X0(int num)1718 create_Imm8_X0(int num)
1719 {
1720   const unsigned int n = (unsigned int)num;
1721   return ((n & 0xff) << 12);
1722 }
1723 
1724 static __inline tilegx_bundle_bits
create_Imm8_X1(int num)1725 create_Imm8_X1(int num)
1726 {
1727   const unsigned int n = (unsigned int)num;
1728   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
1729 }
1730 
1731 static __inline tilegx_bundle_bits
create_Imm8_Y0(int num)1732 create_Imm8_Y0(int num)
1733 {
1734   const unsigned int n = (unsigned int)num;
1735   return ((n & 0xff) << 12);
1736 }
1737 
1738 static __inline tilegx_bundle_bits
create_Imm8_Y1(int num)1739 create_Imm8_Y1(int num)
1740 {
1741   const unsigned int n = (unsigned int)num;
1742   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
1743 }
1744 
1745 static __inline tilegx_bundle_bits
create_JumpOff_X1(int num)1746 create_JumpOff_X1(int num)
1747 {
1748   const unsigned int n = (unsigned int)num;
1749   return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
1750 }
1751 
1752 static __inline tilegx_bundle_bits
create_JumpOpcodeExtension_X1(int num)1753 create_JumpOpcodeExtension_X1(int num)
1754 {
1755   const unsigned int n = (unsigned int)num;
1756   return (((tilegx_bundle_bits)(n & 0x1)) << 58);
1757 }
1758 
1759 static __inline tilegx_bundle_bits
create_MF_Imm14_X1(int num)1760 create_MF_Imm14_X1(int num)
1761 {
1762   const unsigned int n = (unsigned int)num;
1763   return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
1764 }
1765 
1766 static __inline tilegx_bundle_bits
create_MT_Imm14_X1(int num)1767 create_MT_Imm14_X1(int num)
1768 {
1769   const unsigned int n = (unsigned int)num;
1770   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
1771          (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
1772 }
1773 
1774 static __inline tilegx_bundle_bits
create_Mode(int num)1775 create_Mode(int num)
1776 {
1777   const unsigned int n = (unsigned int)num;
1778   return (((tilegx_bundle_bits)(n & 0x3)) << 62);
1779 }
1780 
1781 static __inline tilegx_bundle_bits
create_Opcode_X0(int num)1782 create_Opcode_X0(int num)
1783 {
1784   const unsigned int n = (unsigned int)num;
1785   return ((n & 0x7) << 28);
1786 }
1787 
1788 static __inline tilegx_bundle_bits
create_Opcode_X1(int num)1789 create_Opcode_X1(int num)
1790 {
1791   const unsigned int n = (unsigned int)num;
1792   return (((tilegx_bundle_bits)(n & 0x7)) << 59);
1793 }
1794 
1795 static __inline tilegx_bundle_bits
create_Opcode_Y0(int num)1796 create_Opcode_Y0(int num)
1797 {
1798   const unsigned int n = (unsigned int)num;
1799   return ((n & 0xf) << 27);
1800 }
1801 
1802 static __inline tilegx_bundle_bits
create_Opcode_Y1(int num)1803 create_Opcode_Y1(int num)
1804 {
1805   const unsigned int n = (unsigned int)num;
1806   return (((tilegx_bundle_bits)(n & 0xf)) << 58);
1807 }
1808 
1809 static __inline tilegx_bundle_bits
create_Opcode_Y2(int num)1810 create_Opcode_Y2(int num)
1811 {
1812   const unsigned int n = (unsigned int)num;
1813   return ((n & 0x00000001) << 26) |
1814          (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
1815 }
1816 
1817 static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X0(int num)1818 create_RRROpcodeExtension_X0(int num)
1819 {
1820   const unsigned int n = (unsigned int)num;
1821   return ((n & 0x3ff) << 18);
1822 }
1823 
1824 static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X1(int num)1825 create_RRROpcodeExtension_X1(int num)
1826 {
1827   const unsigned int n = (unsigned int)num;
1828   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1829 }
1830 
1831 static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y0(int num)1832 create_RRROpcodeExtension_Y0(int num)
1833 {
1834   const unsigned int n = (unsigned int)num;
1835   return ((n & 0x3) << 18);
1836 }
1837 
1838 static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y1(int num)1839 create_RRROpcodeExtension_Y1(int num)
1840 {
1841   const unsigned int n = (unsigned int)num;
1842   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1843 }
1844 
1845 static __inline tilegx_bundle_bits
create_ShAmt_X0(int num)1846 create_ShAmt_X0(int num)
1847 {
1848   const unsigned int n = (unsigned int)num;
1849   return ((n & 0x3f) << 12);
1850 }
1851 
1852 static __inline tilegx_bundle_bits
create_ShAmt_X1(int num)1853 create_ShAmt_X1(int num)
1854 {
1855   const unsigned int n = (unsigned int)num;
1856   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1857 }
1858 
1859 static __inline tilegx_bundle_bits
create_ShAmt_Y0(int num)1860 create_ShAmt_Y0(int num)
1861 {
1862   const unsigned int n = (unsigned int)num;
1863   return ((n & 0x3f) << 12);
1864 }
1865 
1866 static __inline tilegx_bundle_bits
create_ShAmt_Y1(int num)1867 create_ShAmt_Y1(int num)
1868 {
1869   const unsigned int n = (unsigned int)num;
1870   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1871 }
1872 
1873 static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X0(int num)1874 create_ShiftOpcodeExtension_X0(int num)
1875 {
1876   const unsigned int n = (unsigned int)num;
1877   return ((n & 0x3ff) << 18);
1878 }
1879 
1880 static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X1(int num)1881 create_ShiftOpcodeExtension_X1(int num)
1882 {
1883   const unsigned int n = (unsigned int)num;
1884   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1885 }
1886 
1887 static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y0(int num)1888 create_ShiftOpcodeExtension_Y0(int num)
1889 {
1890   const unsigned int n = (unsigned int)num;
1891   return ((n & 0x3) << 18);
1892 }
1893 
1894 static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y1(int num)1895 create_ShiftOpcodeExtension_Y1(int num)
1896 {
1897   const unsigned int n = (unsigned int)num;
1898   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1899 }
1900 
1901 static __inline tilegx_bundle_bits
create_SrcA_X0(int num)1902 create_SrcA_X0(int num)
1903 {
1904   const unsigned int n = (unsigned int)num;
1905   return ((n & 0x3f) << 6);
1906 }
1907 
1908 static __inline tilegx_bundle_bits
create_SrcA_X1(int num)1909 create_SrcA_X1(int num)
1910 {
1911   const unsigned int n = (unsigned int)num;
1912   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1913 }
1914 
1915 static __inline tilegx_bundle_bits
create_SrcA_Y0(int num)1916 create_SrcA_Y0(int num)
1917 {
1918   const unsigned int n = (unsigned int)num;
1919   return ((n & 0x3f) << 6);
1920 }
1921 
1922 static __inline tilegx_bundle_bits
create_SrcA_Y1(int num)1923 create_SrcA_Y1(int num)
1924 {
1925   const unsigned int n = (unsigned int)num;
1926   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1927 }
1928 
1929 static __inline tilegx_bundle_bits
create_SrcA_Y2(int num)1930 create_SrcA_Y2(int num)
1931 {
1932   const unsigned int n = (unsigned int)num;
1933   return ((n & 0x3f) << 20);
1934 }
1935 
1936 static __inline tilegx_bundle_bits
create_SrcBDest_Y2(int num)1937 create_SrcBDest_Y2(int num)
1938 {
1939   const unsigned int n = (unsigned int)num;
1940   return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1941 }
1942 
1943 static __inline tilegx_bundle_bits
create_SrcB_X0(int num)1944 create_SrcB_X0(int num)
1945 {
1946   const unsigned int n = (unsigned int)num;
1947   return ((n & 0x3f) << 12);
1948 }
1949 
1950 static __inline tilegx_bundle_bits
create_SrcB_X1(int num)1951 create_SrcB_X1(int num)
1952 {
1953   const unsigned int n = (unsigned int)num;
1954   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1955 }
1956 
1957 static __inline tilegx_bundle_bits
create_SrcB_Y0(int num)1958 create_SrcB_Y0(int num)
1959 {
1960   const unsigned int n = (unsigned int)num;
1961   return ((n & 0x3f) << 12);
1962 }
1963 
1964 static __inline tilegx_bundle_bits
create_SrcB_Y1(int num)1965 create_SrcB_Y1(int num)
1966 {
1967   const unsigned int n = (unsigned int)num;
1968   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1969 }
1970 
1971 static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X0(int num)1972 create_UnaryOpcodeExtension_X0(int num)
1973 {
1974   const unsigned int n = (unsigned int)num;
1975   return ((n & 0x3f) << 12);
1976 }
1977 
1978 static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X1(int num)1979 create_UnaryOpcodeExtension_X1(int num)
1980 {
1981   const unsigned int n = (unsigned int)num;
1982   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1983 }
1984 
1985 static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y0(int num)1986 create_UnaryOpcodeExtension_Y0(int num)
1987 {
1988   const unsigned int n = (unsigned int)num;
1989   return ((n & 0x3f) << 12);
1990 }
1991 
1992 static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y1(int num)1993 create_UnaryOpcodeExtension_Y1(int num)
1994 {
1995   const unsigned int n = (unsigned int)num;
1996   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1997 }
1998 
1999 const struct tilegx_opcode tilegx_opcodes[336] =
2000 {
2001  { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
2002     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
2003 #ifndef DISASM_ONLY
2004     {
2005       0ULL,
2006       0xffffffff80000000ULL,
2007       0ULL,
2008       0ULL,
2009       0ULL
2010     },
2011     {
2012       -1ULL,
2013       0x286a44ae00000000ULL,
2014       -1ULL,
2015       -1ULL,
2016       -1ULL
2017     }
2018 #endif
2019   },
2020   { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
2021     { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
2022 #ifndef DISASM_ONLY
2023     {
2024       0xc00000007ff00fffULL,
2025       0xfff807ff80000000ULL,
2026       0x0000000078000fffULL,
2027       0x3c0007ff80000000ULL,
2028       0ULL
2029     },
2030     {
2031       0x0000000040300fffULL,
2032       0x181807ff80000000ULL,
2033       0x0000000010000fffULL,
2034       0x0c0007ff80000000ULL,
2035       -1ULL
2036     }
2037 #endif
2038   },
2039   { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
2040     { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
2041 #ifndef DISASM_ONLY
2042     {
2043       0xc000000070000fffULL,
2044       0xf80007ff80000000ULL,
2045       0ULL,
2046       0ULL,
2047       0ULL
2048     },
2049     {
2050       0x0000000070000fffULL,
2051       0x380007ff80000000ULL,
2052       -1ULL,
2053       -1ULL,
2054       -1ULL
2055     }
2056 #endif
2057   },
2058   { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
2059     { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
2060 #ifndef DISASM_ONLY
2061     {
2062       0ULL,
2063       0xfffff80000000000ULL,
2064       0ULL,
2065       0ULL,
2066       0ULL
2067     },
2068     {
2069       -1ULL,
2070       0x1858000000000000ULL,
2071       -1ULL,
2072       -1ULL,
2073       -1ULL
2074     }
2075 #endif
2076   },
2077   { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
2078     { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
2079 #ifndef DISASM_ONLY
2080     {
2081       0ULL,
2082       0xfffff80000000000ULL,
2083       0ULL,
2084       0ULL,
2085       0ULL
2086     },
2087     {
2088       -1ULL,
2089       0x18a0000000000000ULL,
2090       -1ULL,
2091       -1ULL,
2092       -1ULL
2093     }
2094 #endif
2095   },
2096   { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
2097     { { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } },
2098 #ifndef DISASM_ONLY
2099     {
2100       0xc00000007ffff000ULL,
2101       0xfffff80000000000ULL,
2102       0x00000000780ff000ULL,
2103       0x3c07f80000000000ULL,
2104       0ULL
2105     },
2106     {
2107       0x000000005107f000ULL,
2108       0x283bf80000000000ULL,
2109       0x00000000500bf000ULL,
2110       0x2c05f80000000000ULL,
2111       -1ULL
2112     }
2113 #endif
2114   },
2115   { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
2116     { { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
2117 #ifndef DISASM_ONLY
2118     {
2119       0xc00000007ff00fc0ULL,
2120       0xfff807e000000000ULL,
2121       0x0000000078000fc0ULL,
2122       0x3c0007e000000000ULL,
2123       0ULL
2124     },
2125     {
2126       0x0000000040100fc0ULL,
2127       0x180807e000000000ULL,
2128       0x0000000000000fc0ULL,
2129       0x040007e000000000ULL,
2130       -1ULL
2131     }
2132 #endif
2133   },
2134   { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
2135     { { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } },
2136 #ifndef DISASM_ONLY
2137     {
2138       0xc000000070000fc0ULL,
2139       0xf80007e000000000ULL,
2140       0ULL,
2141       0ULL,
2142       0ULL
2143     },
2144     {
2145       0x0000000010000fc0ULL,
2146       0x000007e000000000ULL,
2147       -1ULL,
2148       -1ULL,
2149       -1ULL
2150     }
2151 #endif
2152   },
2153   { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
2154     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2155 #ifndef DISASM_ONLY
2156     {
2157       0ULL,
2158       0xfffff81f80000000ULL,
2159       0ULL,
2160       0ULL,
2161       0xc3f8000004000000ULL
2162     },
2163     {
2164       -1ULL,
2165       0x286a801f80000000ULL,
2166       -1ULL,
2167       -1ULL,
2168       0x41f8000004000000ULL
2169     }
2170 #endif
2171   },
2172   { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
2173     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2174 #ifndef DISASM_ONLY
2175     {
2176       0ULL,
2177       0xfff8001f80000000ULL,
2178       0ULL,
2179       0ULL,
2180       0ULL
2181     },
2182     {
2183       -1ULL,
2184       0x1840001f80000000ULL,
2185       -1ULL,
2186       -1ULL,
2187       -1ULL
2188     }
2189 #endif
2190   },
2191   { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
2192     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2193 #ifndef DISASM_ONLY
2194     {
2195       0ULL,
2196       0xfff8001f80000000ULL,
2197       0ULL,
2198       0ULL,
2199       0ULL
2200     },
2201     {
2202       -1ULL,
2203       0x1838001f80000000ULL,
2204       -1ULL,
2205       -1ULL,
2206       -1ULL
2207     }
2208 #endif
2209   },
2210   { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
2211     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2212 #ifndef DISASM_ONLY
2213     {
2214       0ULL,
2215       0xfff8001f80000000ULL,
2216       0ULL,
2217       0ULL,
2218       0ULL
2219     },
2220     {
2221       -1ULL,
2222       0x1850001f80000000ULL,
2223       -1ULL,
2224       -1ULL,
2225       -1ULL
2226     }
2227 #endif
2228   },
2229   { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
2230     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2231 #ifndef DISASM_ONLY
2232     {
2233       0ULL,
2234       0xfff8001f80000000ULL,
2235       0ULL,
2236       0ULL,
2237       0ULL
2238     },
2239     {
2240       -1ULL,
2241       0x1848001f80000000ULL,
2242       -1ULL,
2243       -1ULL,
2244       -1ULL
2245     }
2246 #endif
2247   },
2248   { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
2249     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2250 #ifndef DISASM_ONLY
2251     {
2252       0ULL,
2253       0xfff8001f80000000ULL,
2254       0ULL,
2255       0ULL,
2256       0ULL
2257     },
2258     {
2259       -1ULL,
2260       0x1860001f80000000ULL,
2261       -1ULL,
2262       -1ULL,
2263       -1ULL
2264     }
2265 #endif
2266   },
2267   { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
2268     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
2269 #ifndef DISASM_ONLY
2270     {
2271       0ULL,
2272       0xfff8001f80000000ULL,
2273       0ULL,
2274       0ULL,
2275       0ULL
2276     },
2277     {
2278       -1ULL,
2279       0x1858001f80000000ULL,
2280       -1ULL,
2281       -1ULL,
2282       -1ULL
2283     }
2284 #endif
2285   },
2286   { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
2287     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2288 #ifndef DISASM_ONLY
2289     {
2290       0ULL,
2291       0xfffff81f80000000ULL,
2292       0ULL,
2293       0ULL,
2294       0xc3f8000004000000ULL
2295     },
2296     {
2297       -1ULL,
2298       0x286a801f80000000ULL,
2299       -1ULL,
2300       -1ULL,
2301       0x41f8000004000000ULL
2302     }
2303 #endif
2304   },
2305   { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
2306     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2307 #ifndef DISASM_ONLY
2308     {
2309       0ULL,
2310       0xfffff81f80000000ULL,
2311       0ULL,
2312       0ULL,
2313       0xc3f8000004000000ULL
2314     },
2315     {
2316       -1ULL,
2317       0x286a781f80000000ULL,
2318       -1ULL,
2319       -1ULL,
2320       0x41f8000000000000ULL
2321     }
2322 #endif
2323   },
2324   { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
2325     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2326 #ifndef DISASM_ONLY
2327     {
2328       0ULL,
2329       0xfffff81f80000000ULL,
2330       0ULL,
2331       0ULL,
2332       0xc3f8000004000000ULL
2333     },
2334     {
2335       -1ULL,
2336       0x286a901f80000000ULL,
2337       -1ULL,
2338       -1ULL,
2339       0x43f8000004000000ULL
2340     }
2341 #endif
2342   },
2343   { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
2344     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2345 #ifndef DISASM_ONLY
2346     {
2347       0ULL,
2348       0xfffff81f80000000ULL,
2349       0ULL,
2350       0ULL,
2351       0xc3f8000004000000ULL
2352     },
2353     {
2354       -1ULL,
2355       0x286a881f80000000ULL,
2356       -1ULL,
2357       -1ULL,
2358       0x43f8000000000000ULL
2359     }
2360 #endif
2361   },
2362   { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
2363     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2364 #ifndef DISASM_ONLY
2365     {
2366       0ULL,
2367       0xfffff81f80000000ULL,
2368       0ULL,
2369       0ULL,
2370       0xc3f8000004000000ULL
2371     },
2372     {
2373       -1ULL,
2374       0x286aa01f80000000ULL,
2375       -1ULL,
2376       -1ULL,
2377       0x83f8000000000000ULL
2378     }
2379 #endif
2380   },
2381   { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
2382     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
2383 #ifndef DISASM_ONLY
2384     {
2385       0ULL,
2386       0xfffff81f80000000ULL,
2387       0ULL,
2388       0ULL,
2389       0xc3f8000004000000ULL
2390     },
2391     {
2392       -1ULL,
2393       0x286a981f80000000ULL,
2394       -1ULL,
2395       -1ULL,
2396       0x81f8000004000000ULL
2397     }
2398 #endif
2399   },
2400   { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
2401     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
2402 #ifndef DISASM_ONLY
2403     {
2404       0ULL,
2405       0xffffffff80000000ULL,
2406       0ULL,
2407       0ULL,
2408       0ULL
2409     },
2410     {
2411       -1ULL,
2412       0x286a44ae80000000ULL,
2413       -1ULL,
2414       -1ULL,
2415       -1ULL
2416     }
2417 #endif
2418   },
2419   { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
2420     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
2421 #ifndef DISASM_ONLY
2422     {
2423       0xc00000007ffc0000ULL,
2424       0xfffe000000000000ULL,
2425       0x00000000780c0000ULL,
2426       0x3c06000000000000ULL,
2427       0ULL
2428     },
2429     {
2430       0x00000000500c0000ULL,
2431       0x2806000000000000ULL,
2432       0x0000000028040000ULL,
2433       0x1802000000000000ULL,
2434       -1ULL
2435     }
2436 #endif
2437   },
2438   { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
2439     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
2440 #ifndef DISASM_ONLY
2441     {
2442       0xc00000007ff00000ULL,
2443       0xfff8000000000000ULL,
2444       0x0000000078000000ULL,
2445       0x3c00000000000000ULL,
2446       0ULL
2447     },
2448     {
2449       0x0000000040100000ULL,
2450       0x1808000000000000ULL,
2451       0ULL,
2452       0x0400000000000000ULL,
2453       -1ULL
2454     }
2455 #endif
2456   },
2457   { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
2458     { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
2459 #ifndef DISASM_ONLY
2460     {
2461       0xc000000070000000ULL,
2462       0xf800000000000000ULL,
2463       0ULL,
2464       0ULL,
2465       0ULL
2466     },
2467     {
2468       0x0000000010000000ULL,
2469       0ULL,
2470       -1ULL,
2471       -1ULL,
2472       -1ULL
2473     }
2474 #endif
2475   },
2476   { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
2477     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
2478 #ifndef DISASM_ONLY
2479     {
2480       0xc00000007ffc0000ULL,
2481       0xfffe000000000000ULL,
2482       0x00000000780c0000ULL,
2483       0x3c06000000000000ULL,
2484       0ULL
2485     },
2486     {
2487       0x0000000050080000ULL,
2488       0x2804000000000000ULL,
2489       0x0000000028000000ULL,
2490       0x1800000000000000ULL,
2491       -1ULL
2492     }
2493 #endif
2494   },
2495   { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
2496     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
2497 #ifndef DISASM_ONLY
2498     {
2499       0xc00000007ff00000ULL,
2500       0xfff8000000000000ULL,
2501       0x0000000078000000ULL,
2502       0x3c00000000000000ULL,
2503       0ULL
2504     },
2505     {
2506       0x0000000040200000ULL,
2507       0x1810000000000000ULL,
2508       0x0000000008000000ULL,
2509       0x0800000000000000ULL,
2510       -1ULL
2511     }
2512 #endif
2513   },
2514   { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
2515     { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
2516 #ifndef DISASM_ONLY
2517     {
2518       0xc000000070000000ULL,
2519       0xf800000000000000ULL,
2520       0ULL,
2521       0ULL,
2522       0ULL
2523     },
2524     {
2525       0x0000000020000000ULL,
2526       0x0800000000000000ULL,
2527       -1ULL,
2528       -1ULL,
2529       -1ULL
2530     }
2531 #endif
2532   },
2533   { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
2534     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
2535 #ifndef DISASM_ONLY
2536     {
2537       0xc00000007ffc0000ULL,
2538       0xfffe000000000000ULL,
2539       0ULL,
2540       0ULL,
2541       0ULL
2542     },
2543     {
2544       0x0000000050040000ULL,
2545       0x2802000000000000ULL,
2546       -1ULL,
2547       -1ULL,
2548       -1ULL
2549     }
2550 #endif
2551   },
2552   { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
2553     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
2554 #ifndef DISASM_ONLY
2555     {
2556       0xc00000007ffc0000ULL,
2557       0xfffe000000000000ULL,
2558       0x00000000780c0000ULL,
2559       0x3c06000000000000ULL,
2560       0ULL
2561     },
2562     {
2563       0x0000000050100000ULL,
2564       0x2808000000000000ULL,
2565       0x0000000050000000ULL,
2566       0x2c00000000000000ULL,
2567       -1ULL
2568     }
2569 #endif
2570   },
2571   { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
2572     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
2573 #ifndef DISASM_ONLY
2574     {
2575       0xc00000007ff00000ULL,
2576       0xfff8000000000000ULL,
2577       0x0000000078000000ULL,
2578       0x3c00000000000000ULL,
2579       0ULL
2580     },
2581     {
2582       0x0000000040300000ULL,
2583       0x1818000000000000ULL,
2584       0x0000000010000000ULL,
2585       0x0c00000000000000ULL,
2586       -1ULL
2587     }
2588 #endif
2589   },
2590   { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
2591     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2592 #ifndef DISASM_ONLY
2593     {
2594       0ULL,
2595       0xffc0000000000000ULL,
2596       0ULL,
2597       0ULL,
2598       0ULL
2599     },
2600     {
2601       -1ULL,
2602       0x1440000000000000ULL,
2603       -1ULL,
2604       -1ULL,
2605       -1ULL
2606     }
2607 #endif
2608   },
2609   { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
2610     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2611 #ifndef DISASM_ONLY
2612     {
2613       0ULL,
2614       0xffc0000000000000ULL,
2615       0ULL,
2616       0ULL,
2617       0ULL
2618     },
2619     {
2620       -1ULL,
2621       0x1400000000000000ULL,
2622       -1ULL,
2623       -1ULL,
2624       -1ULL
2625     }
2626 #endif
2627   },
2628   { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
2629     { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
2630 #ifndef DISASM_ONLY
2631     {
2632       0xc00000007f000000ULL,
2633       0ULL,
2634       0ULL,
2635       0ULL,
2636       0ULL
2637     },
2638     {
2639       0x0000000034000000ULL,
2640       -1ULL,
2641       -1ULL,
2642       -1ULL,
2643       -1ULL
2644     }
2645 #endif
2646   },
2647   { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
2648     { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
2649 #ifndef DISASM_ONLY
2650     {
2651       0xc00000007f000000ULL,
2652       0ULL,
2653       0ULL,
2654       0ULL,
2655       0ULL
2656     },
2657     {
2658       0x0000000035000000ULL,
2659       -1ULL,
2660       -1ULL,
2661       -1ULL,
2662       -1ULL
2663     }
2664 #endif
2665   },
2666   { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
2667     { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
2668 #ifndef DISASM_ONLY
2669     {
2670       0xc00000007f000000ULL,
2671       0ULL,
2672       0ULL,
2673       0ULL,
2674       0ULL
2675     },
2676     {
2677       0x0000000036000000ULL,
2678       -1ULL,
2679       -1ULL,
2680       -1ULL,
2681       -1ULL
2682     }
2683 #endif
2684   },
2685   { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
2686     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2687 #ifndef DISASM_ONLY
2688     {
2689       0ULL,
2690       0xffc0000000000000ULL,
2691       0ULL,
2692       0ULL,
2693       0ULL
2694     },
2695     {
2696       -1ULL,
2697       0x14c0000000000000ULL,
2698       -1ULL,
2699       -1ULL,
2700       -1ULL
2701     }
2702 #endif
2703   },
2704   { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
2705     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2706 #ifndef DISASM_ONLY
2707     {
2708       0ULL,
2709       0xffc0000000000000ULL,
2710       0ULL,
2711       0ULL,
2712       0ULL
2713     },
2714     {
2715       -1ULL,
2716       0x1480000000000000ULL,
2717       -1ULL,
2718       -1ULL,
2719       -1ULL
2720     }
2721 #endif
2722   },
2723   { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
2724     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2725 #ifndef DISASM_ONLY
2726     {
2727       0ULL,
2728       0xffc0000000000000ULL,
2729       0ULL,
2730       0ULL,
2731       0ULL
2732     },
2733     {
2734       -1ULL,
2735       0x1540000000000000ULL,
2736       -1ULL,
2737       -1ULL,
2738       -1ULL
2739     }
2740 #endif
2741   },
2742   { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
2743     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2744 #ifndef DISASM_ONLY
2745     {
2746       0ULL,
2747       0xffc0000000000000ULL,
2748       0ULL,
2749       0ULL,
2750       0ULL
2751     },
2752     {
2753       -1ULL,
2754       0x1500000000000000ULL,
2755       -1ULL,
2756       -1ULL,
2757       -1ULL
2758     }
2759 #endif
2760   },
2761   { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
2762     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2763 #ifndef DISASM_ONLY
2764     {
2765       0ULL,
2766       0xffc0000000000000ULL,
2767       0ULL,
2768       0ULL,
2769       0ULL
2770     },
2771     {
2772       -1ULL,
2773       0x15c0000000000000ULL,
2774       -1ULL,
2775       -1ULL,
2776       -1ULL
2777     }
2778 #endif
2779   },
2780   { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
2781     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2782 #ifndef DISASM_ONLY
2783     {
2784       0ULL,
2785       0xffc0000000000000ULL,
2786       0ULL,
2787       0ULL,
2788       0ULL
2789     },
2790     {
2791       -1ULL,
2792       0x1580000000000000ULL,
2793       -1ULL,
2794       -1ULL,
2795       -1ULL
2796     }
2797 #endif
2798   },
2799   { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
2800     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2801 #ifndef DISASM_ONLY
2802     {
2803       0ULL,
2804       0xffc0000000000000ULL,
2805       0ULL,
2806       0ULL,
2807       0ULL
2808     },
2809     {
2810       -1ULL,
2811       0x1640000000000000ULL,
2812       -1ULL,
2813       -1ULL,
2814       -1ULL
2815     }
2816 #endif
2817   },
2818   { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
2819     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2820 #ifndef DISASM_ONLY
2821     {
2822       0ULL,
2823       0xffc0000000000000ULL,
2824       0ULL,
2825       0ULL,
2826       0ULL
2827     },
2828     {
2829       -1ULL,
2830       0x1600000000000000ULL,
2831       -1ULL,
2832       -1ULL,
2833       -1ULL
2834     }
2835 #endif
2836   },
2837   { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
2838     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2839 #ifndef DISASM_ONLY
2840     {
2841       0ULL,
2842       0xffc0000000000000ULL,
2843       0ULL,
2844       0ULL,
2845       0ULL
2846     },
2847     {
2848       -1ULL,
2849       0x16c0000000000000ULL,
2850       -1ULL,
2851       -1ULL,
2852       -1ULL
2853     }
2854 #endif
2855   },
2856   { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
2857     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2858 #ifndef DISASM_ONLY
2859     {
2860       0ULL,
2861       0xffc0000000000000ULL,
2862       0ULL,
2863       0ULL,
2864       0ULL
2865     },
2866     {
2867       -1ULL,
2868       0x1680000000000000ULL,
2869       -1ULL,
2870       -1ULL,
2871       -1ULL
2872     }
2873 #endif
2874   },
2875   { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
2876     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2877 #ifndef DISASM_ONLY
2878     {
2879       0ULL,
2880       0xffc0000000000000ULL,
2881       0ULL,
2882       0ULL,
2883       0ULL
2884     },
2885     {
2886       -1ULL,
2887       0x1740000000000000ULL,
2888       -1ULL,
2889       -1ULL,
2890       -1ULL
2891     }
2892 #endif
2893   },
2894   { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
2895     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2896 #ifndef DISASM_ONLY
2897     {
2898       0ULL,
2899       0xffc0000000000000ULL,
2900       0ULL,
2901       0ULL,
2902       0ULL
2903     },
2904     {
2905       -1ULL,
2906       0x1700000000000000ULL,
2907       -1ULL,
2908       -1ULL,
2909       -1ULL
2910     }
2911 #endif
2912   },
2913   { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
2914     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2915 #ifndef DISASM_ONLY
2916     {
2917       0ULL,
2918       0xffc0000000000000ULL,
2919       0ULL,
2920       0ULL,
2921       0ULL
2922     },
2923     {
2924       -1ULL,
2925       0x17c0000000000000ULL,
2926       -1ULL,
2927       -1ULL,
2928       -1ULL
2929     }
2930 #endif
2931   },
2932   { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
2933     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
2934 #ifndef DISASM_ONLY
2935     {
2936       0ULL,
2937       0xffc0000000000000ULL,
2938       0ULL,
2939       0ULL,
2940       0ULL
2941     },
2942     {
2943       -1ULL,
2944       0x1780000000000000ULL,
2945       -1ULL,
2946       -1ULL,
2947       -1ULL
2948     }
2949 #endif
2950   },
2951   { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
2952     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
2953 #ifndef DISASM_ONLY
2954     {
2955       0xc00000007ffff000ULL,
2956       0ULL,
2957       0x00000000780ff000ULL,
2958       0ULL,
2959       0ULL
2960     },
2961     {
2962       0x0000000051481000ULL,
2963       -1ULL,
2964       0x00000000300c1000ULL,
2965       -1ULL,
2966       -1ULL
2967     }
2968 #endif
2969   },
2970   { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
2971     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
2972 #ifndef DISASM_ONLY
2973     {
2974       0xc00000007ffc0000ULL,
2975       0ULL,
2976       0x00000000780c0000ULL,
2977       0ULL,
2978       0ULL
2979     },
2980     {
2981       0x0000000050140000ULL,
2982       -1ULL,
2983       0x0000000048000000ULL,
2984       -1ULL,
2985       -1ULL
2986     }
2987 #endif
2988   },
2989   { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
2990     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
2991 #ifndef DISASM_ONLY
2992     {
2993       0xc00000007ffc0000ULL,
2994       0ULL,
2995       0x00000000780c0000ULL,
2996       0ULL,
2997       0ULL
2998     },
2999     {
3000       0x0000000050180000ULL,
3001       -1ULL,
3002       0x0000000048040000ULL,
3003       -1ULL,
3004       -1ULL
3005     }
3006 #endif
3007   },
3008   { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
3009     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3010 #ifndef DISASM_ONLY
3011     {
3012       0xc00000007ffc0000ULL,
3013       0xfffe000000000000ULL,
3014       0x00000000780c0000ULL,
3015       0x3c06000000000000ULL,
3016       0ULL
3017     },
3018     {
3019       0x00000000501c0000ULL,
3020       0x280a000000000000ULL,
3021       0x0000000040000000ULL,
3022       0x2404000000000000ULL,
3023       -1ULL
3024     }
3025 #endif
3026   },
3027   { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
3028     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
3029 #ifndef DISASM_ONLY
3030     {
3031       0xc00000007ff00000ULL,
3032       0xfff8000000000000ULL,
3033       0x0000000078000000ULL,
3034       0x3c00000000000000ULL,
3035       0ULL
3036     },
3037     {
3038       0x0000000040400000ULL,
3039       0x1820000000000000ULL,
3040       0x0000000018000000ULL,
3041       0x1000000000000000ULL,
3042       -1ULL
3043     }
3044 #endif
3045   },
3046   { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
3047     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3048 #ifndef DISASM_ONLY
3049     {
3050       0ULL,
3051       0xfffe000000000000ULL,
3052       0ULL,
3053       0ULL,
3054       0ULL
3055     },
3056     {
3057       -1ULL,
3058       0x280e000000000000ULL,
3059       -1ULL,
3060       -1ULL,
3061       -1ULL
3062     }
3063 #endif
3064   },
3065   { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
3066     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3067 #ifndef DISASM_ONLY
3068     {
3069       0ULL,
3070       0xfffe000000000000ULL,
3071       0ULL,
3072       0ULL,
3073       0ULL
3074     },
3075     {
3076       -1ULL,
3077       0x280c000000000000ULL,
3078       -1ULL,
3079       -1ULL,
3080       -1ULL
3081     }
3082 #endif
3083   },
3084   { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
3085     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3086 #ifndef DISASM_ONLY
3087     {
3088       0xc00000007ffc0000ULL,
3089       0xfffe000000000000ULL,
3090       0x00000000780c0000ULL,
3091       0x3c06000000000000ULL,
3092       0ULL
3093     },
3094     {
3095       0x0000000050200000ULL,
3096       0x2810000000000000ULL,
3097       0x0000000038000000ULL,
3098       0x2000000000000000ULL,
3099       -1ULL
3100     }
3101 #endif
3102   },
3103   { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
3104     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3105 #ifndef DISASM_ONLY
3106     {
3107       0xc00000007ffc0000ULL,
3108       0xfffe000000000000ULL,
3109       0x00000000780c0000ULL,
3110       0x3c06000000000000ULL,
3111       0ULL
3112     },
3113     {
3114       0x0000000050240000ULL,
3115       0x2812000000000000ULL,
3116       0x0000000038040000ULL,
3117       0x2002000000000000ULL,
3118       -1ULL
3119     }
3120 #endif
3121   },
3122   { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
3123     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3124 #ifndef DISASM_ONLY
3125     {
3126       0xc00000007ffc0000ULL,
3127       0xfffe000000000000ULL,
3128       0x00000000780c0000ULL,
3129       0x3c06000000000000ULL,
3130       0ULL
3131     },
3132     {
3133       0x0000000050280000ULL,
3134       0x2814000000000000ULL,
3135       0x0000000038080000ULL,
3136       0x2004000000000000ULL,
3137       -1ULL
3138     }
3139 #endif
3140   },
3141   { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
3142     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
3143 #ifndef DISASM_ONLY
3144     {
3145       0xc00000007ff00000ULL,
3146       0xfff8000000000000ULL,
3147       0x0000000078000000ULL,
3148       0x3c00000000000000ULL,
3149       0ULL
3150     },
3151     {
3152       0x0000000040500000ULL,
3153       0x1828000000000000ULL,
3154       0x0000000020000000ULL,
3155       0x1400000000000000ULL,
3156       -1ULL
3157     }
3158 #endif
3159   },
3160   { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
3161     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3162 #ifndef DISASM_ONLY
3163     {
3164       0xc00000007ffc0000ULL,
3165       0xfffe000000000000ULL,
3166       0x00000000780c0000ULL,
3167       0x3c06000000000000ULL,
3168       0ULL
3169     },
3170     {
3171       0x00000000502c0000ULL,
3172       0x2816000000000000ULL,
3173       0x00000000380c0000ULL,
3174       0x2006000000000000ULL,
3175       -1ULL
3176     }
3177 #endif
3178   },
3179   { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
3180     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
3181 #ifndef DISASM_ONLY
3182     {
3183       0xc00000007ff00000ULL,
3184       0xfff8000000000000ULL,
3185       0ULL,
3186       0ULL,
3187       0ULL
3188     },
3189     {
3190       0x0000000040600000ULL,
3191       0x1830000000000000ULL,
3192       -1ULL,
3193       -1ULL,
3194       -1ULL
3195     }
3196 #endif
3197   },
3198   { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
3199     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
3200 #ifndef DISASM_ONLY
3201     {
3202       0xc00000007ffc0000ULL,
3203       0xfffe000000000000ULL,
3204       0x00000000780c0000ULL,
3205       0x3c06000000000000ULL,
3206       0ULL
3207     },
3208     {
3209       0x0000000050300000ULL,
3210       0x2818000000000000ULL,
3211       0x0000000040040000ULL,
3212       0x2406000000000000ULL,
3213       -1ULL
3214     }
3215 #endif
3216   },
3217   { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
3218     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3219 #ifndef DISASM_ONLY
3220     {
3221       0xc00000007ffc0000ULL,
3222       0ULL,
3223       0ULL,
3224       0ULL,
3225       0ULL
3226     },
3227     {
3228       0x00000000504c0000ULL,
3229       -1ULL,
3230       -1ULL,
3231       -1ULL,
3232       -1ULL
3233     }
3234 #endif
3235   },
3236   { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
3237     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3238 #ifndef DISASM_ONLY
3239     {
3240       0xc00000007ffc0000ULL,
3241       0ULL,
3242       0ULL,
3243       0ULL,
3244       0ULL
3245     },
3246     {
3247       0x0000000050380000ULL,
3248       -1ULL,
3249       -1ULL,
3250       -1ULL,
3251       -1ULL
3252     }
3253 #endif
3254   },
3255   { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
3256     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3257 #ifndef DISASM_ONLY
3258     {
3259       0xc00000007ffc0000ULL,
3260       0ULL,
3261       0ULL,
3262       0ULL,
3263       0ULL
3264     },
3265     {
3266       0x0000000050340000ULL,
3267       -1ULL,
3268       -1ULL,
3269       -1ULL,
3270       -1ULL
3271     }
3272 #endif
3273   },
3274   { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
3275     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3276 #ifndef DISASM_ONLY
3277     {
3278       0xc00000007ffc0000ULL,
3279       0ULL,
3280       0ULL,
3281       0ULL,
3282       0ULL
3283     },
3284     {
3285       0x0000000050400000ULL,
3286       -1ULL,
3287       -1ULL,
3288       -1ULL,
3289       -1ULL
3290     }
3291 #endif
3292   },
3293   { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
3294     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3295 #ifndef DISASM_ONLY
3296     {
3297       0xc00000007ffc0000ULL,
3298       0ULL,
3299       0ULL,
3300       0ULL,
3301       0ULL
3302     },
3303     {
3304       0x00000000503c0000ULL,
3305       -1ULL,
3306       -1ULL,
3307       -1ULL,
3308       -1ULL
3309     }
3310 #endif
3311   },
3312   { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
3313     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3314 #ifndef DISASM_ONLY
3315     {
3316       0xc00000007ffc0000ULL,
3317       0ULL,
3318       0ULL,
3319       0ULL,
3320       0ULL
3321     },
3322     {
3323       0x0000000050480000ULL,
3324       -1ULL,
3325       -1ULL,
3326       -1ULL,
3327       -1ULL
3328     }
3329 #endif
3330   },
3331   { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
3332     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3333 #ifndef DISASM_ONLY
3334     {
3335       0xc00000007ffc0000ULL,
3336       0ULL,
3337       0ULL,
3338       0ULL,
3339       0ULL
3340     },
3341     {
3342       0x0000000050440000ULL,
3343       -1ULL,
3344       -1ULL,
3345       -1ULL,
3346       -1ULL
3347     }
3348 #endif
3349   },
3350   { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
3351     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3352 #ifndef DISASM_ONLY
3353     {
3354       0xc00000007ffc0000ULL,
3355       0ULL,
3356       0ULL,
3357       0ULL,
3358       0ULL
3359     },
3360     {
3361       0x0000000050500000ULL,
3362       -1ULL,
3363       -1ULL,
3364       -1ULL,
3365       -1ULL
3366     }
3367 #endif
3368   },
3369   { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
3370     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3371 #ifndef DISASM_ONLY
3372     {
3373       0xc00000007ffc0000ULL,
3374       0ULL,
3375       0ULL,
3376       0ULL,
3377       0ULL
3378     },
3379     {
3380       0x0000000050540000ULL,
3381       -1ULL,
3382       -1ULL,
3383       -1ULL,
3384       -1ULL
3385     }
3386 #endif
3387   },
3388   { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
3389     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
3390 #ifndef DISASM_ONLY
3391     {
3392       0xc00000007ffff000ULL,
3393       0ULL,
3394       0x00000000780ff000ULL,
3395       0ULL,
3396       0ULL
3397     },
3398     {
3399       0x0000000051482000ULL,
3400       -1ULL,
3401       0x00000000300c2000ULL,
3402       -1ULL,
3403       -1ULL
3404     }
3405 #endif
3406   },
3407   { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
3408     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3409 #ifndef DISASM_ONLY
3410     {
3411       0xc00000007ffc0000ULL,
3412       0ULL,
3413       0ULL,
3414       0ULL,
3415       0ULL
3416     },
3417     {
3418       0x0000000050640000ULL,
3419       -1ULL,
3420       -1ULL,
3421       -1ULL,
3422       -1ULL
3423     }
3424 #endif
3425   },
3426   { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
3427     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3428 #ifndef DISASM_ONLY
3429     {
3430       0xc00000007ffc0000ULL,
3431       0xfffe000000000000ULL,
3432       0ULL,
3433       0ULL,
3434       0ULL
3435     },
3436     {
3437       0x0000000050580000ULL,
3438       0x281a000000000000ULL,
3439       -1ULL,
3440       -1ULL,
3441       -1ULL
3442     }
3443 #endif
3444   },
3445   { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
3446     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3447 #ifndef DISASM_ONLY
3448     {
3449       0xc00000007ffc0000ULL,
3450       0xfffe000000000000ULL,
3451       0ULL,
3452       0ULL,
3453       0ULL
3454     },
3455     {
3456       0x00000000505c0000ULL,
3457       0x281c000000000000ULL,
3458       -1ULL,
3459       -1ULL,
3460       -1ULL
3461     }
3462 #endif
3463   },
3464   { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
3465     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3466 #ifndef DISASM_ONLY
3467     {
3468       0xc00000007ffc0000ULL,
3469       0xfffe000000000000ULL,
3470       0ULL,
3471       0ULL,
3472       0ULL
3473     },
3474     {
3475       0x0000000050600000ULL,
3476       0x281e000000000000ULL,
3477       -1ULL,
3478       -1ULL,
3479       -1ULL
3480     }
3481 #endif
3482   },
3483   { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
3484     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
3485 #ifndef DISASM_ONLY
3486     {
3487       0ULL,
3488       0xfffff80000000000ULL,
3489       0ULL,
3490       0ULL,
3491       0ULL
3492     },
3493     {
3494       -1ULL,
3495       0x286a080000000000ULL,
3496       -1ULL,
3497       -1ULL,
3498       -1ULL
3499     }
3500 #endif
3501   },
3502   { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
3503     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
3504 #ifndef DISASM_ONLY
3505     {
3506       0ULL,
3507       0xfffff80000000000ULL,
3508       0ULL,
3509       0ULL,
3510       0ULL
3511     },
3512     {
3513       -1ULL,
3514       0x286a100000000000ULL,
3515       -1ULL,
3516       -1ULL,
3517       -1ULL
3518     }
3519 #endif
3520   },
3521   { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
3522     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3523 #ifndef DISASM_ONLY
3524     {
3525       0ULL,
3526       0xfffe000000000000ULL,
3527       0ULL,
3528       0ULL,
3529       0ULL
3530     },
3531     {
3532       -1ULL,
3533       0x2822000000000000ULL,
3534       -1ULL,
3535       -1ULL,
3536       -1ULL
3537     }
3538 #endif
3539   },
3540   { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
3541     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3542 #ifndef DISASM_ONLY
3543     {
3544       0ULL,
3545       0xfffe000000000000ULL,
3546       0ULL,
3547       0ULL,
3548       0ULL
3549     },
3550     {
3551       -1ULL,
3552       0x2820000000000000ULL,
3553       -1ULL,
3554       -1ULL,
3555       -1ULL
3556     }
3557 #endif
3558   },
3559   { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
3560     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3561 #ifndef DISASM_ONLY
3562     {
3563       0xc00000007ffc0000ULL,
3564       0ULL,
3565       0ULL,
3566       0ULL,
3567       0ULL
3568     },
3569     {
3570       0x00000000506c0000ULL,
3571       -1ULL,
3572       -1ULL,
3573       -1ULL,
3574       -1ULL
3575     }
3576 #endif
3577   },
3578   { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
3579     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3580 #ifndef DISASM_ONLY
3581     {
3582       0xc00000007ffc0000ULL,
3583       0ULL,
3584       0ULL,
3585       0ULL,
3586       0ULL
3587     },
3588     {
3589       0x0000000050680000ULL,
3590       -1ULL,
3591       -1ULL,
3592       -1ULL,
3593       -1ULL
3594     }
3595 #endif
3596   },
3597   { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
3598     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3599 #ifndef DISASM_ONLY
3600     {
3601       0xc00000007ffc0000ULL,
3602       0ULL,
3603       0ULL,
3604       0ULL,
3605       0ULL
3606     },
3607     {
3608       0x0000000050700000ULL,
3609       -1ULL,
3610       -1ULL,
3611       -1ULL,
3612       -1ULL
3613     }
3614 #endif
3615   },
3616   { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
3617     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3618 #ifndef DISASM_ONLY
3619     {
3620       0xc00000007ffc0000ULL,
3621       0ULL,
3622       0ULL,
3623       0ULL,
3624       0ULL
3625     },
3626     {
3627       0x0000000050740000ULL,
3628       -1ULL,
3629       -1ULL,
3630       -1ULL,
3631       -1ULL
3632     }
3633 #endif
3634   },
3635   { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
3636     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3637 #ifndef DISASM_ONLY
3638     {
3639       0xc00000007ffc0000ULL,
3640       0ULL,
3641       0ULL,
3642       0ULL,
3643       0ULL
3644     },
3645     {
3646       0x0000000050780000ULL,
3647       -1ULL,
3648       -1ULL,
3649       -1ULL,
3650       -1ULL
3651     }
3652 #endif
3653   },
3654   { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
3655     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3656 #ifndef DISASM_ONLY
3657     {
3658       0xc00000007ffc0000ULL,
3659       0ULL,
3660       0ULL,
3661       0ULL,
3662       0ULL
3663     },
3664     {
3665       0x00000000507c0000ULL,
3666       -1ULL,
3667       -1ULL,
3668       -1ULL,
3669       -1ULL
3670     }
3671 #endif
3672   },
3673   { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
3674     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3675 #ifndef DISASM_ONLY
3676     {
3677       0xc00000007ffc0000ULL,
3678       0ULL,
3679       0ULL,
3680       0ULL,
3681       0ULL
3682     },
3683     {
3684       0x0000000050800000ULL,
3685       -1ULL,
3686       -1ULL,
3687       -1ULL,
3688       -1ULL
3689     }
3690 #endif
3691   },
3692   { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
3693     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3694 #ifndef DISASM_ONLY
3695     {
3696       0xc00000007ffc0000ULL,
3697       0ULL,
3698       0ULL,
3699       0ULL,
3700       0ULL
3701     },
3702     {
3703       0x0000000050840000ULL,
3704       -1ULL,
3705       -1ULL,
3706       -1ULL,
3707       -1ULL
3708     }
3709 #endif
3710   },
3711   { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
3712     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3713 #ifndef DISASM_ONLY
3714     {
3715       0ULL,
3716       0xfffe000000000000ULL,
3717       0ULL,
3718       0ULL,
3719       0ULL
3720     },
3721     {
3722       -1ULL,
3723       0x282a000000000000ULL,
3724       -1ULL,
3725       -1ULL,
3726       -1ULL
3727     }
3728 #endif
3729   },
3730   { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
3731     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3732 #ifndef DISASM_ONLY
3733     {
3734       0ULL,
3735       0xfffe000000000000ULL,
3736       0ULL,
3737       0ULL,
3738       0ULL
3739     },
3740     {
3741       -1ULL,
3742       0x2824000000000000ULL,
3743       -1ULL,
3744       -1ULL,
3745       -1ULL
3746     }
3747 #endif
3748   },
3749   { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
3750     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3751 #ifndef DISASM_ONLY
3752     {
3753       0ULL,
3754       0xfffe000000000000ULL,
3755       0ULL,
3756       0ULL,
3757       0ULL
3758     },
3759     {
3760       -1ULL,
3761       0x2828000000000000ULL,
3762       -1ULL,
3763       -1ULL,
3764       -1ULL
3765     }
3766 #endif
3767   },
3768   { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
3769     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3770 #ifndef DISASM_ONLY
3771     {
3772       0ULL,
3773       0xfffe000000000000ULL,
3774       0ULL,
3775       0ULL,
3776       0ULL
3777     },
3778     {
3779       -1ULL,
3780       0x2826000000000000ULL,
3781       -1ULL,
3782       -1ULL,
3783       -1ULL
3784     }
3785 #endif
3786   },
3787   { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
3788     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3789 #ifndef DISASM_ONLY
3790     {
3791       0ULL,
3792       0xfffe000000000000ULL,
3793       0ULL,
3794       0ULL,
3795       0ULL
3796     },
3797     {
3798       -1ULL,
3799       0x282e000000000000ULL,
3800       -1ULL,
3801       -1ULL,
3802       -1ULL
3803     }
3804 #endif
3805   },
3806   { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
3807     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3808 #ifndef DISASM_ONLY
3809     {
3810       0ULL,
3811       0xfffe000000000000ULL,
3812       0ULL,
3813       0ULL,
3814       0ULL
3815     },
3816     {
3817       -1ULL,
3818       0x282c000000000000ULL,
3819       -1ULL,
3820       -1ULL,
3821       -1ULL
3822     }
3823 #endif
3824   },
3825   { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
3826     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3827 #ifndef DISASM_ONLY
3828     {
3829       0ULL,
3830       0xfffe000000000000ULL,
3831       0ULL,
3832       0ULL,
3833       0ULL
3834     },
3835     {
3836       -1ULL,
3837       0x2832000000000000ULL,
3838       -1ULL,
3839       -1ULL,
3840       -1ULL
3841     }
3842 #endif
3843   },
3844   { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
3845     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
3846 #ifndef DISASM_ONLY
3847     {
3848       0ULL,
3849       0xfffe000000000000ULL,
3850       0ULL,
3851       0ULL,
3852       0ULL
3853     },
3854     {
3855       -1ULL,
3856       0x2830000000000000ULL,
3857       -1ULL,
3858       -1ULL,
3859       -1ULL
3860     }
3861 #endif
3862   },
3863   { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
3864     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
3865 #ifndef DISASM_ONLY
3866     {
3867       0ULL,
3868       0xfffff80000000000ULL,
3869       0ULL,
3870       0ULL,
3871       0ULL
3872     },
3873     {
3874       -1ULL,
3875       0x286a180000000000ULL,
3876       -1ULL,
3877       -1ULL,
3878       -1ULL
3879     }
3880 #endif
3881   },
3882   { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
3883     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
3884 #ifndef DISASM_ONLY
3885     {
3886       0ULL,
3887       0xfffff80000000000ULL,
3888       0ULL,
3889       0ULL,
3890       0ULL
3891     },
3892     {
3893       -1ULL,
3894       0x286a280000000000ULL,
3895       -1ULL,
3896       -1ULL,
3897       -1ULL
3898     }
3899 #endif
3900   },
3901   { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
3902     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
3903 #ifndef DISASM_ONLY
3904     {
3905       0ULL,
3906       0xfffff80000000000ULL,
3907       0ULL,
3908       0ULL,
3909       0ULL
3910     },
3911     {
3912       -1ULL,
3913       0x286a200000000000ULL,
3914       -1ULL,
3915       -1ULL,
3916       -1ULL
3917     }
3918 #endif
3919   },
3920   { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
3921     { {  }, {  }, {  }, {  }, { 0, } },
3922 #ifndef DISASM_ONLY
3923     {
3924       0xc00000007ffff000ULL,
3925       0xfffff80000000000ULL,
3926       0x00000000780ff000ULL,
3927       0x3c07f80000000000ULL,
3928       0ULL
3929     },
3930     {
3931       0x0000000051483000ULL,
3932       0x286a300000000000ULL,
3933       0x00000000300c3000ULL,
3934       0x1c06400000000000ULL,
3935       -1ULL
3936     }
3937 #endif
3938   },
3939   { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
3940     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3941 #ifndef DISASM_ONLY
3942     {
3943       0xc00000007ffc0000ULL,
3944       0ULL,
3945       0ULL,
3946       0ULL,
3947       0ULL
3948     },
3949     {
3950       0x0000000050880000ULL,
3951       -1ULL,
3952       -1ULL,
3953       -1ULL,
3954       -1ULL
3955     }
3956 #endif
3957   },
3958   { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
3959     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3960 #ifndef DISASM_ONLY
3961     {
3962       0xc00000007ffc0000ULL,
3963       0ULL,
3964       0ULL,
3965       0ULL,
3966       0ULL
3967     },
3968     {
3969       0x00000000508c0000ULL,
3970       -1ULL,
3971       -1ULL,
3972       -1ULL,
3973       -1ULL
3974     }
3975 #endif
3976   },
3977   { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
3978     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3979 #ifndef DISASM_ONLY
3980     {
3981       0xc00000007ffc0000ULL,
3982       0ULL,
3983       0ULL,
3984       0ULL,
3985       0ULL
3986     },
3987     {
3988       0x0000000050900000ULL,
3989       -1ULL,
3990       -1ULL,
3991       -1ULL,
3992       -1ULL
3993     }
3994 #endif
3995   },
3996   { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
3997     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
3998 #ifndef DISASM_ONLY
3999     {
4000       0xc00000007ffc0000ULL,
4001       0ULL,
4002       0ULL,
4003       0ULL,
4004       0ULL
4005     },
4006     {
4007       0x0000000050940000ULL,
4008       -1ULL,
4009       -1ULL,
4010       -1ULL,
4011       -1ULL
4012     }
4013 #endif
4014   },
4015   { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
4016     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
4017 #ifndef DISASM_ONLY
4018     {
4019       0xc00000007ffff000ULL,
4020       0ULL,
4021       0x00000000780ff000ULL,
4022       0ULL,
4023       0ULL
4024     },
4025     {
4026       0x0000000051484000ULL,
4027       -1ULL,
4028       0x00000000300c4000ULL,
4029       -1ULL,
4030       -1ULL
4031     }
4032 #endif
4033   },
4034   { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
4035     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4036 #ifndef DISASM_ONLY
4037     {
4038       0xc00000007ffc0000ULL,
4039       0ULL,
4040       0ULL,
4041       0ULL,
4042       0ULL
4043     },
4044     {
4045       0x0000000050980000ULL,
4046       -1ULL,
4047       -1ULL,
4048       -1ULL,
4049       -1ULL
4050     }
4051 #endif
4052   },
4053   { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
4054     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4055 #ifndef DISASM_ONLY
4056     {
4057       0xc00000007ffc0000ULL,
4058       0ULL,
4059       0ULL,
4060       0ULL,
4061       0ULL
4062     },
4063     {
4064       0x00000000509c0000ULL,
4065       -1ULL,
4066       -1ULL,
4067       -1ULL,
4068       -1ULL
4069     }
4070 #endif
4071   },
4072   { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
4073     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
4074 #ifndef DISASM_ONLY
4075     {
4076       0ULL,
4077       0xfffff80000000000ULL,
4078       0ULL,
4079       0ULL,
4080       0ULL
4081     },
4082     {
4083       -1ULL,
4084       0x286a380000000000ULL,
4085       -1ULL,
4086       -1ULL,
4087       -1ULL
4088     }
4089 #endif
4090   },
4091   { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
4092     { { 0, }, {  }, { 0, }, {  }, { 0, } },
4093 #ifndef DISASM_ONLY
4094     {
4095       0ULL,
4096       0xfffff80000000000ULL,
4097       0ULL,
4098       0x3c07f80000000000ULL,
4099       0ULL
4100     },
4101     {
4102       -1ULL,
4103       0x286a400000000000ULL,
4104       -1ULL,
4105       0x1c06480000000000ULL,
4106       -1ULL
4107     }
4108 #endif
4109   },
4110   { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
4111     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
4112 #ifndef DISASM_ONLY
4113     {
4114       0ULL,
4115       0xfffff80000000000ULL,
4116       0ULL,
4117       0ULL,
4118       0ULL
4119     },
4120     {
4121       -1ULL,
4122       0x286a480000000000ULL,
4123       -1ULL,
4124       -1ULL,
4125       -1ULL
4126     }
4127 #endif
4128   },
4129   { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
4130     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
4131 #ifndef DISASM_ONLY
4132     {
4133       0ULL,
4134       0xfffff80000000000ULL,
4135       0ULL,
4136       0ULL,
4137       0ULL
4138     },
4139     {
4140       -1ULL,
4141       0x286a500000000000ULL,
4142       -1ULL,
4143       -1ULL,
4144       -1ULL
4145     }
4146 #endif
4147   },
4148   { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
4149     { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
4150 #ifndef DISASM_ONLY
4151     {
4152       0ULL,
4153       0xfc00000000000000ULL,
4154       0ULL,
4155       0ULL,
4156       0ULL
4157     },
4158     {
4159       -1ULL,
4160       0x2400000000000000ULL,
4161       -1ULL,
4162       -1ULL,
4163       -1ULL
4164     }
4165 #endif
4166   },
4167   { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
4168     { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
4169 #ifndef DISASM_ONLY
4170     {
4171       0ULL,
4172       0xfc00000000000000ULL,
4173       0ULL,
4174       0ULL,
4175       0ULL
4176     },
4177     {
4178       -1ULL,
4179       0x2000000000000000ULL,
4180       -1ULL,
4181       -1ULL,
4182       -1ULL
4183     }
4184 #endif
4185   },
4186   { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
4187     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
4188 #ifndef DISASM_ONLY
4189     {
4190       0ULL,
4191       0xfffff80000000000ULL,
4192       0ULL,
4193       0x3c07f80000000000ULL,
4194       0ULL
4195     },
4196     {
4197       -1ULL,
4198       0x286a600000000000ULL,
4199       -1ULL,
4200       0x1c06580000000000ULL,
4201       -1ULL
4202     }
4203 #endif
4204   },
4205   { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
4206     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
4207 #ifndef DISASM_ONLY
4208     {
4209       0ULL,
4210       0xfffff80000000000ULL,
4211       0ULL,
4212       0x3c07f80000000000ULL,
4213       0ULL
4214     },
4215     {
4216       -1ULL,
4217       0x286a580000000000ULL,
4218       -1ULL,
4219       0x1c06500000000000ULL,
4220       -1ULL
4221     }
4222 #endif
4223   },
4224   { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
4225     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
4226 #ifndef DISASM_ONLY
4227     {
4228       0ULL,
4229       0xfffff80000000000ULL,
4230       0ULL,
4231       0x3c07f80000000000ULL,
4232       0ULL
4233     },
4234     {
4235       -1ULL,
4236       0x286a700000000000ULL,
4237       -1ULL,
4238       0x1c06680000000000ULL,
4239       -1ULL
4240     }
4241 #endif
4242   },
4243   { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
4244     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
4245 #ifndef DISASM_ONLY
4246     {
4247       0ULL,
4248       0xfffff80000000000ULL,
4249       0ULL,
4250       0x3c07f80000000000ULL,
4251       0ULL
4252     },
4253     {
4254       -1ULL,
4255       0x286a680000000000ULL,
4256       -1ULL,
4257       0x1c06600000000000ULL,
4258       -1ULL
4259     }
4260 #endif
4261   },
4262   { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
4263     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4264 #ifndef DISASM_ONLY
4265     {
4266       0ULL,
4267       0xfffff80000000000ULL,
4268       0ULL,
4269       0ULL,
4270       0xc200000004000000ULL
4271     },
4272     {
4273       -1ULL,
4274       0x286ae80000000000ULL,
4275       -1ULL,
4276       -1ULL,
4277       0x8200000004000000ULL
4278     }
4279 #endif
4280   },
4281   { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
4282     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4283 #ifndef DISASM_ONLY
4284     {
4285       0ULL,
4286       0xfffff80000000000ULL,
4287       0ULL,
4288       0ULL,
4289       0xc200000004000000ULL
4290     },
4291     {
4292       -1ULL,
4293       0x286a780000000000ULL,
4294       -1ULL,
4295       -1ULL,
4296       0x4000000000000000ULL
4297     }
4298 #endif
4299   },
4300   { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
4301     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4302 #ifndef DISASM_ONLY
4303     {
4304       0ULL,
4305       0xfff8000000000000ULL,
4306       0ULL,
4307       0ULL,
4308       0ULL
4309     },
4310     {
4311       -1ULL,
4312       0x1838000000000000ULL,
4313       -1ULL,
4314       -1ULL,
4315       -1ULL
4316     }
4317 #endif
4318   },
4319   { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
4320     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4321 #ifndef DISASM_ONLY
4322     {
4323       0ULL,
4324       0xfffff80000000000ULL,
4325       0ULL,
4326       0ULL,
4327       0xc200000004000000ULL
4328     },
4329     {
4330       -1ULL,
4331       0x286a800000000000ULL,
4332       -1ULL,
4333       -1ULL,
4334       0x4000000004000000ULL
4335     }
4336 #endif
4337   },
4338   { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
4339     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4340 #ifndef DISASM_ONLY
4341     {
4342       0ULL,
4343       0xfff8000000000000ULL,
4344       0ULL,
4345       0ULL,
4346       0ULL
4347     },
4348     {
4349       -1ULL,
4350       0x1840000000000000ULL,
4351       -1ULL,
4352       -1ULL,
4353       -1ULL
4354     }
4355 #endif
4356   },
4357   { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
4358     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4359 #ifndef DISASM_ONLY
4360     {
4361       0ULL,
4362       0xfffff80000000000ULL,
4363       0ULL,
4364       0ULL,
4365       0xc200000004000000ULL
4366     },
4367     {
4368       -1ULL,
4369       0x286a880000000000ULL,
4370       -1ULL,
4371       -1ULL,
4372       0x4200000000000000ULL
4373     }
4374 #endif
4375   },
4376   { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
4377     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4378 #ifndef DISASM_ONLY
4379     {
4380       0ULL,
4381       0xfff8000000000000ULL,
4382       0ULL,
4383       0ULL,
4384       0ULL
4385     },
4386     {
4387       -1ULL,
4388       0x1848000000000000ULL,
4389       -1ULL,
4390       -1ULL,
4391       -1ULL
4392     }
4393 #endif
4394   },
4395   { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
4396     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4397 #ifndef DISASM_ONLY
4398     {
4399       0ULL,
4400       0xfffff80000000000ULL,
4401       0ULL,
4402       0ULL,
4403       0xc200000004000000ULL
4404     },
4405     {
4406       -1ULL,
4407       0x286a900000000000ULL,
4408       -1ULL,
4409       -1ULL,
4410       0x4200000004000000ULL
4411     }
4412 #endif
4413   },
4414   { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
4415     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4416 #ifndef DISASM_ONLY
4417     {
4418       0ULL,
4419       0xfff8000000000000ULL,
4420       0ULL,
4421       0ULL,
4422       0ULL
4423     },
4424     {
4425       -1ULL,
4426       0x1850000000000000ULL,
4427       -1ULL,
4428       -1ULL,
4429       -1ULL
4430     }
4431 #endif
4432   },
4433   { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
4434     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4435 #ifndef DISASM_ONLY
4436     {
4437       0ULL,
4438       0xfffff80000000000ULL,
4439       0ULL,
4440       0ULL,
4441       0xc200000004000000ULL
4442     },
4443     {
4444       -1ULL,
4445       0x286a980000000000ULL,
4446       -1ULL,
4447       -1ULL,
4448       0x8000000004000000ULL
4449     }
4450 #endif
4451   },
4452   { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
4453     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4454 #ifndef DISASM_ONLY
4455     {
4456       0ULL,
4457       0xfff8000000000000ULL,
4458       0ULL,
4459       0ULL,
4460       0ULL
4461     },
4462     {
4463       -1ULL,
4464       0x1858000000000000ULL,
4465       -1ULL,
4466       -1ULL,
4467       -1ULL
4468     }
4469 #endif
4470   },
4471   { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
4472     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
4473 #ifndef DISASM_ONLY
4474     {
4475       0ULL,
4476       0xfffff80000000000ULL,
4477       0ULL,
4478       0ULL,
4479       0xc200000004000000ULL
4480     },
4481     {
4482       -1ULL,
4483       0x286aa00000000000ULL,
4484       -1ULL,
4485       -1ULL,
4486       0x8200000000000000ULL
4487     }
4488 #endif
4489   },
4490   { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
4491     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4492 #ifndef DISASM_ONLY
4493     {
4494       0ULL,
4495       0xfff8000000000000ULL,
4496       0ULL,
4497       0ULL,
4498       0ULL
4499     },
4500     {
4501       -1ULL,
4502       0x1860000000000000ULL,
4503       -1ULL,
4504       -1ULL,
4505       -1ULL
4506     }
4507 #endif
4508   },
4509   { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
4510     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4511 #ifndef DISASM_ONLY
4512     {
4513       0ULL,
4514       0xfff8000000000000ULL,
4515       0ULL,
4516       0ULL,
4517       0ULL
4518     },
4519     {
4520       -1ULL,
4521       0x18a0000000000000ULL,
4522       -1ULL,
4523       -1ULL,
4524       -1ULL
4525     }
4526 #endif
4527   },
4528   { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
4529     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4530 #ifndef DISASM_ONLY
4531     {
4532       0ULL,
4533       0xfffff80000000000ULL,
4534       0ULL,
4535       0ULL,
4536       0ULL
4537     },
4538     {
4539       -1ULL,
4540       0x286aa80000000000ULL,
4541       -1ULL,
4542       -1ULL,
4543       -1ULL
4544     }
4545 #endif
4546   },
4547   { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
4548     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4549 #ifndef DISASM_ONLY
4550     {
4551       0ULL,
4552       0xfff8000000000000ULL,
4553       0ULL,
4554       0ULL,
4555       0ULL
4556     },
4557     {
4558       -1ULL,
4559       0x18a8000000000000ULL,
4560       -1ULL,
4561       -1ULL,
4562       -1ULL
4563     }
4564 #endif
4565   },
4566   { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
4567     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4568 #ifndef DISASM_ONLY
4569     {
4570       0ULL,
4571       0xfffff80000000000ULL,
4572       0ULL,
4573       0ULL,
4574       0ULL
4575     },
4576     {
4577       -1ULL,
4578       0x286ae00000000000ULL,
4579       -1ULL,
4580       -1ULL,
4581       -1ULL
4582     }
4583 #endif
4584   },
4585   { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
4586     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4587 #ifndef DISASM_ONLY
4588     {
4589       0ULL,
4590       0xfffff80000000000ULL,
4591       0ULL,
4592       0ULL,
4593       0ULL
4594     },
4595     {
4596       -1ULL,
4597       0x286ab00000000000ULL,
4598       -1ULL,
4599       -1ULL,
4600       -1ULL
4601     }
4602 #endif
4603   },
4604   { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
4605     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4606 #ifndef DISASM_ONLY
4607     {
4608       0ULL,
4609       0xfff8000000000000ULL,
4610       0ULL,
4611       0ULL,
4612       0ULL
4613     },
4614     {
4615       -1ULL,
4616       0x1868000000000000ULL,
4617       -1ULL,
4618       -1ULL,
4619       -1ULL
4620     }
4621 #endif
4622   },
4623   { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
4624     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4625 #ifndef DISASM_ONLY
4626     {
4627       0ULL,
4628       0xfffff80000000000ULL,
4629       0ULL,
4630       0ULL,
4631       0ULL
4632     },
4633     {
4634       -1ULL,
4635       0x286ab80000000000ULL,
4636       -1ULL,
4637       -1ULL,
4638       -1ULL
4639     }
4640 #endif
4641   },
4642   { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
4643     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4644 #ifndef DISASM_ONLY
4645     {
4646       0ULL,
4647       0xfff8000000000000ULL,
4648       0ULL,
4649       0ULL,
4650       0ULL
4651     },
4652     {
4653       -1ULL,
4654       0x1870000000000000ULL,
4655       -1ULL,
4656       -1ULL,
4657       -1ULL
4658     }
4659 #endif
4660   },
4661   { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
4662     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4663 #ifndef DISASM_ONLY
4664     {
4665       0ULL,
4666       0xfffff80000000000ULL,
4667       0ULL,
4668       0ULL,
4669       0ULL
4670     },
4671     {
4672       -1ULL,
4673       0x286ac00000000000ULL,
4674       -1ULL,
4675       -1ULL,
4676       -1ULL
4677     }
4678 #endif
4679   },
4680   { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
4681     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4682 #ifndef DISASM_ONLY
4683     {
4684       0ULL,
4685       0xfff8000000000000ULL,
4686       0ULL,
4687       0ULL,
4688       0ULL
4689     },
4690     {
4691       -1ULL,
4692       0x1878000000000000ULL,
4693       -1ULL,
4694       -1ULL,
4695       -1ULL
4696     }
4697 #endif
4698   },
4699   { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
4700     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4701 #ifndef DISASM_ONLY
4702     {
4703       0ULL,
4704       0xfffff80000000000ULL,
4705       0ULL,
4706       0ULL,
4707       0ULL
4708     },
4709     {
4710       -1ULL,
4711       0x286ac80000000000ULL,
4712       -1ULL,
4713       -1ULL,
4714       -1ULL
4715     }
4716 #endif
4717   },
4718   { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
4719     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4720 #ifndef DISASM_ONLY
4721     {
4722       0ULL,
4723       0xfff8000000000000ULL,
4724       0ULL,
4725       0ULL,
4726       0ULL
4727     },
4728     {
4729       -1ULL,
4730       0x1880000000000000ULL,
4731       -1ULL,
4732       -1ULL,
4733       -1ULL
4734     }
4735 #endif
4736   },
4737   { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
4738     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4739 #ifndef DISASM_ONLY
4740     {
4741       0ULL,
4742       0xfffff80000000000ULL,
4743       0ULL,
4744       0ULL,
4745       0ULL
4746     },
4747     {
4748       -1ULL,
4749       0x286ad00000000000ULL,
4750       -1ULL,
4751       -1ULL,
4752       -1ULL
4753     }
4754 #endif
4755   },
4756   { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
4757     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4758 #ifndef DISASM_ONLY
4759     {
4760       0ULL,
4761       0xfff8000000000000ULL,
4762       0ULL,
4763       0ULL,
4764       0ULL
4765     },
4766     {
4767       -1ULL,
4768       0x1888000000000000ULL,
4769       -1ULL,
4770       -1ULL,
4771       -1ULL
4772     }
4773 #endif
4774   },
4775   { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
4776     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
4777 #ifndef DISASM_ONLY
4778     {
4779       0ULL,
4780       0xfffff80000000000ULL,
4781       0ULL,
4782       0ULL,
4783       0ULL
4784     },
4785     {
4786       -1ULL,
4787       0x286ad80000000000ULL,
4788       -1ULL,
4789       -1ULL,
4790       -1ULL
4791     }
4792 #endif
4793   },
4794   { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
4795     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4796 #ifndef DISASM_ONLY
4797     {
4798       0ULL,
4799       0xfff8000000000000ULL,
4800       0ULL,
4801       0ULL,
4802       0ULL
4803     },
4804     {
4805       -1ULL,
4806       0x1890000000000000ULL,
4807       -1ULL,
4808       -1ULL,
4809       -1ULL
4810     }
4811 #endif
4812   },
4813   { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
4814     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
4815 #ifndef DISASM_ONLY
4816     {
4817       0ULL,
4818       0xfff8000000000000ULL,
4819       0ULL,
4820       0ULL,
4821       0ULL
4822     },
4823     {
4824       -1ULL,
4825       0x1898000000000000ULL,
4826       -1ULL,
4827       -1ULL,
4828       -1ULL
4829     }
4830 #endif
4831   },
4832   { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
4833     { { 0, }, { 6 }, { 0, }, { 12 }, { 0, } },
4834 #ifndef DISASM_ONLY
4835     {
4836       0ULL,
4837       0xfffff80000000000ULL,
4838       0ULL,
4839       0x3c07f80000000000ULL,
4840       0ULL
4841     },
4842     {
4843       -1ULL,
4844       0x286af00000000000ULL,
4845       -1ULL,
4846       0x1c06700000000000ULL,
4847       -1ULL
4848     }
4849 #endif
4850   },
4851   { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
4852     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
4853 #ifndef DISASM_ONLY
4854     {
4855       0ULL,
4856       0xfffff80000000000ULL,
4857       0ULL,
4858       0ULL,
4859       0ULL
4860     },
4861     {
4862       -1ULL,
4863       0x286af80000000000ULL,
4864       -1ULL,
4865       -1ULL,
4866       -1ULL
4867     }
4868 #endif
4869   },
4870   { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
4871     { { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } },
4872 #ifndef DISASM_ONLY
4873     {
4874       0ULL,
4875       0xfff8000000000000ULL,
4876       0ULL,
4877       0ULL,
4878       0ULL
4879     },
4880     {
4881       -1ULL,
4882       0x18b0000000000000ULL,
4883       -1ULL,
4884       -1ULL,
4885       -1ULL
4886     }
4887 #endif
4888   },
4889   { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
4890     { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
4891 #ifndef DISASM_ONLY
4892     {
4893       0xc00000007f000000ULL,
4894       0ULL,
4895       0ULL,
4896       0ULL,
4897       0ULL
4898     },
4899     {
4900       0x0000000037000000ULL,
4901       -1ULL,
4902       -1ULL,
4903       -1ULL,
4904       -1ULL
4905     }
4906 #endif
4907   },
4908   { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
4909     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
4910 #ifndef DISASM_ONLY
4911     {
4912       0xc00000007ffc0000ULL,
4913       0xfffe000000000000ULL,
4914       0x00000000780c0000ULL,
4915       0x3c06000000000000ULL,
4916       0ULL
4917     },
4918     {
4919       0x0000000050a00000ULL,
4920       0x2834000000000000ULL,
4921       0x0000000048080000ULL,
4922       0x2804000000000000ULL,
4923       -1ULL
4924     }
4925 #endif
4926   },
4927   { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
4928     { { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } },
4929 #ifndef DISASM_ONLY
4930     {
4931       0ULL,
4932       0xfff8000000000000ULL,
4933       0ULL,
4934       0ULL,
4935       0ULL
4936     },
4937     {
4938       -1ULL,
4939       0x18b8000000000000ULL,
4940       -1ULL,
4941       -1ULL,
4942       -1ULL
4943     }
4944 #endif
4945   },
4946   { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
4947     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
4948 #ifndef DISASM_ONLY
4949     {
4950       0xc00000007ffc0000ULL,
4951       0ULL,
4952       0x00000000780c0000ULL,
4953       0ULL,
4954       0ULL
4955     },
4956     {
4957       0x0000000050d40000ULL,
4958       -1ULL,
4959       0x0000000068000000ULL,
4960       -1ULL,
4961       -1ULL
4962     }
4963 #endif
4964   },
4965   { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
4966     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4967 #ifndef DISASM_ONLY
4968     {
4969       0xc00000007ffc0000ULL,
4970       0ULL,
4971       0ULL,
4972       0ULL,
4973       0ULL
4974     },
4975     {
4976       0x0000000050d80000ULL,
4977       -1ULL,
4978       -1ULL,
4979       -1ULL,
4980       -1ULL
4981     }
4982 #endif
4983   },
4984   { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
4985     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4986 #ifndef DISASM_ONLY
4987     {
4988       0xc00000007ffc0000ULL,
4989       0ULL,
4990       0ULL,
4991       0ULL,
4992       0ULL
4993     },
4994     {
4995       0x0000000050dc0000ULL,
4996       -1ULL,
4997       -1ULL,
4998       -1ULL,
4999       -1ULL
5000     }
5001 #endif
5002   },
5003   { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
5004     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5005 #ifndef DISASM_ONLY
5006     {
5007       0xc00000007ffc0000ULL,
5008       0ULL,
5009       0ULL,
5010       0ULL,
5011       0ULL
5012     },
5013     {
5014       0x0000000050e00000ULL,
5015       -1ULL,
5016       -1ULL,
5017       -1ULL,
5018       -1ULL
5019     }
5020 #endif
5021   },
5022   { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
5023     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
5024 #ifndef DISASM_ONLY
5025     {
5026       0xc00000007ffc0000ULL,
5027       0ULL,
5028       0x00000000780c0000ULL,
5029       0ULL,
5030       0ULL
5031     },
5032     {
5033       0x0000000050e40000ULL,
5034       -1ULL,
5035       0x0000000068040000ULL,
5036       -1ULL,
5037       -1ULL
5038     }
5039 #endif
5040   },
5041   { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
5042     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5043 #ifndef DISASM_ONLY
5044     {
5045       0xc00000007ffc0000ULL,
5046       0ULL,
5047       0ULL,
5048       0ULL,
5049       0ULL
5050     },
5051     {
5052       0x0000000050e80000ULL,
5053       -1ULL,
5054       -1ULL,
5055       -1ULL,
5056       -1ULL
5057     }
5058 #endif
5059   },
5060   { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
5061     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5062 #ifndef DISASM_ONLY
5063     {
5064       0xc00000007ffc0000ULL,
5065       0ULL,
5066       0ULL,
5067       0ULL,
5068       0ULL
5069     },
5070     {
5071       0x0000000050ec0000ULL,
5072       -1ULL,
5073       -1ULL,
5074       -1ULL,
5075       -1ULL
5076     }
5077 #endif
5078   },
5079   { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
5080     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
5081 #ifndef DISASM_ONLY
5082     {
5083       0xc00000007ffc0000ULL,
5084       0ULL,
5085       0x00000000780c0000ULL,
5086       0ULL,
5087       0ULL
5088     },
5089     {
5090       0x0000000050f00000ULL,
5091       -1ULL,
5092       0x0000000068080000ULL,
5093       -1ULL,
5094       -1ULL
5095     }
5096 #endif
5097   },
5098   { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
5099     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5100 #ifndef DISASM_ONLY
5101     {
5102       0xc00000007ffc0000ULL,
5103       0ULL,
5104       0ULL,
5105       0ULL,
5106       0ULL
5107     },
5108     {
5109       0x0000000050f40000ULL,
5110       -1ULL,
5111       -1ULL,
5112       -1ULL,
5113       -1ULL
5114     }
5115 #endif
5116   },
5117   { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
5118     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
5119 #ifndef DISASM_ONLY
5120     {
5121       0xc00000007ffc0000ULL,
5122       0ULL,
5123       0x00000000780c0000ULL,
5124       0ULL,
5125       0ULL
5126     },
5127     {
5128       0x0000000050f80000ULL,
5129       -1ULL,
5130       0x00000000680c0000ULL,
5131       -1ULL,
5132       -1ULL
5133     }
5134 #endif
5135   },
5136   { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
5137     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
5138 #ifndef DISASM_ONLY
5139     {
5140       0xc00000007ffc0000ULL,
5141       0ULL,
5142       0x00000000780c0000ULL,
5143       0ULL,
5144       0ULL
5145     },
5146     {
5147       0x0000000050a80000ULL,
5148       -1ULL,
5149       0x0000000070000000ULL,
5150       -1ULL,
5151       -1ULL
5152     }
5153 #endif
5154   },
5155   { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
5156     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5157 #ifndef DISASM_ONLY
5158     {
5159       0xc00000007ffc0000ULL,
5160       0ULL,
5161       0ULL,
5162       0ULL,
5163       0ULL
5164     },
5165     {
5166       0x0000000050ac0000ULL,
5167       -1ULL,
5168       -1ULL,
5169       -1ULL,
5170       -1ULL
5171     }
5172 #endif
5173   },
5174   { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
5175     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5176 #ifndef DISASM_ONLY
5177     {
5178       0xc00000007ffc0000ULL,
5179       0ULL,
5180       0ULL,
5181       0ULL,
5182       0ULL
5183     },
5184     {
5185       0x0000000050b00000ULL,
5186       -1ULL,
5187       -1ULL,
5188       -1ULL,
5189       -1ULL
5190     }
5191 #endif
5192   },
5193   { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
5194     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5195 #ifndef DISASM_ONLY
5196     {
5197       0xc00000007ffc0000ULL,
5198       0ULL,
5199       0ULL,
5200       0ULL,
5201       0ULL
5202     },
5203     {
5204       0x0000000050b40000ULL,
5205       -1ULL,
5206       -1ULL,
5207       -1ULL,
5208       -1ULL
5209     }
5210 #endif
5211   },
5212   { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
5213     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
5214 #ifndef DISASM_ONLY
5215     {
5216       0xc00000007ffc0000ULL,
5217       0ULL,
5218       0x00000000780c0000ULL,
5219       0ULL,
5220       0ULL
5221     },
5222     {
5223       0x0000000050b80000ULL,
5224       -1ULL,
5225       0x0000000070040000ULL,
5226       -1ULL,
5227       -1ULL
5228     }
5229 #endif
5230   },
5231   { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
5232     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5233 #ifndef DISASM_ONLY
5234     {
5235       0xc00000007ffc0000ULL,
5236       0ULL,
5237       0ULL,
5238       0ULL,
5239       0ULL
5240     },
5241     {
5242       0x0000000050bc0000ULL,
5243       -1ULL,
5244       -1ULL,
5245       -1ULL,
5246       -1ULL
5247     }
5248 #endif
5249   },
5250   { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
5251     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5252 #ifndef DISASM_ONLY
5253     {
5254       0xc00000007ffc0000ULL,
5255       0ULL,
5256       0ULL,
5257       0ULL,
5258       0ULL
5259     },
5260     {
5261       0x0000000050c00000ULL,
5262       -1ULL,
5263       -1ULL,
5264       -1ULL,
5265       -1ULL
5266     }
5267 #endif
5268   },
5269   { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
5270     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
5271 #ifndef DISASM_ONLY
5272     {
5273       0xc00000007ffc0000ULL,
5274       0ULL,
5275       0x00000000780c0000ULL,
5276       0ULL,
5277       0ULL
5278     },
5279     {
5280       0x0000000050c40000ULL,
5281       -1ULL,
5282       0x0000000070080000ULL,
5283       -1ULL,
5284       -1ULL
5285     }
5286 #endif
5287   },
5288   { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
5289     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5290 #ifndef DISASM_ONLY
5291     {
5292       0xc00000007ffc0000ULL,
5293       0ULL,
5294       0ULL,
5295       0ULL,
5296       0ULL
5297     },
5298     {
5299       0x0000000050c80000ULL,
5300       -1ULL,
5301       -1ULL,
5302       -1ULL,
5303       -1ULL
5304     }
5305 #endif
5306   },
5307   { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
5308     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
5309 #ifndef DISASM_ONLY
5310     {
5311       0xc00000007ffc0000ULL,
5312       0ULL,
5313       0x00000000780c0000ULL,
5314       0ULL,
5315       0ULL
5316     },
5317     {
5318       0x0000000050cc0000ULL,
5319       -1ULL,
5320       0x00000000700c0000ULL,
5321       -1ULL,
5322       -1ULL
5323     }
5324 #endif
5325   },
5326   { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
5327     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
5328 #ifndef DISASM_ONLY
5329     {
5330       0xc00000007ffc0000ULL,
5331       0ULL,
5332       0x00000000780c0000ULL,
5333       0ULL,
5334       0ULL
5335     },
5336     {
5337       0x0000000050a40000ULL,
5338       -1ULL,
5339       0x0000000040080000ULL,
5340       -1ULL,
5341       -1ULL
5342     }
5343 #endif
5344   },
5345   { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
5346     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
5347 #ifndef DISASM_ONLY
5348     {
5349       0xc00000007ffc0000ULL,
5350       0ULL,
5351       0x00000000780c0000ULL,
5352       0ULL,
5353       0ULL
5354     },
5355     {
5356       0x0000000050d00000ULL,
5357       -1ULL,
5358       0x00000000400c0000ULL,
5359       -1ULL,
5360       -1ULL
5361     }
5362 #endif
5363   },
5364   { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
5365     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5366 #ifndef DISASM_ONLY
5367     {
5368       0xc00000007ffc0000ULL,
5369       0xfffe000000000000ULL,
5370       0x00000000780c0000ULL,
5371       0x3c06000000000000ULL,
5372       0ULL
5373     },
5374     {
5375       0x0000000050fc0000ULL,
5376       0x2836000000000000ULL,
5377       0x00000000480c0000ULL,
5378       0x2806000000000000ULL,
5379       -1ULL
5380     }
5381 #endif
5382   },
5383   { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
5384     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
5385 #ifndef DISASM_ONLY
5386     {
5387       0ULL,
5388       0xfffff80000000000ULL,
5389       0ULL,
5390       0ULL,
5391       0ULL
5392     },
5393     {
5394       -1ULL,
5395       0x286b000000000000ULL,
5396       -1ULL,
5397       -1ULL,
5398       -1ULL
5399     }
5400 #endif
5401   },
5402   { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
5403     { {  }, {  }, {  }, {  }, { 0, } },
5404 #ifndef DISASM_ONLY
5405     {
5406       0xc00000007ffff000ULL,
5407       0xfffff80000000000ULL,
5408       0x00000000780ff000ULL,
5409       0x3c07f80000000000ULL,
5410       0ULL
5411     },
5412     {
5413       0x0000000051485000ULL,
5414       0x286b080000000000ULL,
5415       0x00000000300c5000ULL,
5416       0x1c06780000000000ULL,
5417       -1ULL
5418     }
5419 #endif
5420   },
5421   { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
5422     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5423 #ifndef DISASM_ONLY
5424     {
5425       0xc00000007ffc0000ULL,
5426       0xfffe000000000000ULL,
5427       0x00000000780c0000ULL,
5428       0x3c06000000000000ULL,
5429       0ULL
5430     },
5431     {
5432       0x0000000051000000ULL,
5433       0x2838000000000000ULL,
5434       0x0000000050040000ULL,
5435       0x2c02000000000000ULL,
5436       -1ULL
5437     }
5438 #endif
5439   },
5440   { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
5441     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5442 #ifndef DISASM_ONLY
5443     {
5444       0xc00000007ffc0000ULL,
5445       0xfffe000000000000ULL,
5446       0x00000000780c0000ULL,
5447       0x3c06000000000000ULL,
5448       0ULL
5449     },
5450     {
5451       0x0000000051040000ULL,
5452       0x283a000000000000ULL,
5453       0x0000000050080000ULL,
5454       0x2c04000000000000ULL,
5455       -1ULL
5456     }
5457 #endif
5458   },
5459   { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
5460     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
5461 #ifndef DISASM_ONLY
5462     {
5463       0xc00000007ff00000ULL,
5464       0xfff8000000000000ULL,
5465       0ULL,
5466       0ULL,
5467       0ULL
5468     },
5469     {
5470       0x0000000040700000ULL,
5471       0x18c0000000000000ULL,
5472       -1ULL,
5473       -1ULL,
5474       -1ULL
5475     }
5476 #endif
5477   },
5478   { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
5479     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
5480 #ifndef DISASM_ONLY
5481     {
5482       0xc00000007ffff000ULL,
5483       0ULL,
5484       0x00000000780ff000ULL,
5485       0ULL,
5486       0ULL
5487     },
5488     {
5489       0x0000000051486000ULL,
5490       -1ULL,
5491       0x00000000300c6000ULL,
5492       -1ULL,
5493       -1ULL
5494     }
5495 #endif
5496   },
5497   { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
5498     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
5499 #ifndef DISASM_ONLY
5500     {
5501       0xc00000007ffff000ULL,
5502       0ULL,
5503       0x00000000780ff000ULL,
5504       0ULL,
5505       0ULL
5506     },
5507     {
5508       0x0000000051487000ULL,
5509       -1ULL,
5510       0x00000000300c7000ULL,
5511       -1ULL,
5512       -1ULL
5513     }
5514 #endif
5515   },
5516   { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
5517     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
5518 #ifndef DISASM_ONLY
5519     {
5520       0xc00000007ffff000ULL,
5521       0ULL,
5522       0x00000000780ff000ULL,
5523       0ULL,
5524       0ULL
5525     },
5526     {
5527       0x0000000051488000ULL,
5528       -1ULL,
5529       0x00000000300c8000ULL,
5530       -1ULL,
5531       -1ULL
5532     }
5533 #endif
5534   },
5535   { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
5536     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5537 #ifndef DISASM_ONLY
5538     {
5539       0xc00000007ffc0000ULL,
5540       0xfffe000000000000ULL,
5541       0x00000000780c0000ULL,
5542       0x3c06000000000000ULL,
5543       0ULL
5544     },
5545     {
5546       0x0000000051080000ULL,
5547       0x283c000000000000ULL,
5548       0x0000000058000000ULL,
5549       0x3000000000000000ULL,
5550       -1ULL
5551     }
5552 #endif
5553   },
5554   { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
5555     { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
5556 #ifndef DISASM_ONLY
5557     {
5558       0xc00000007ffc0000ULL,
5559       0xfffe000000000000ULL,
5560       0x00000000780c0000ULL,
5561       0x3c06000000000000ULL,
5562       0ULL
5563     },
5564     {
5565       0x0000000060040000ULL,
5566       0x3002000000000000ULL,
5567       0x0000000078000000ULL,
5568       0x3800000000000000ULL,
5569       -1ULL
5570     }
5571 #endif
5572   },
5573   { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
5574     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5575 #ifndef DISASM_ONLY
5576     {
5577       0xc00000007ffc0000ULL,
5578       0xfffe000000000000ULL,
5579       0x00000000780c0000ULL,
5580       0x3c06000000000000ULL,
5581       0ULL
5582     },
5583     {
5584       0x0000000051280000ULL,
5585       0x284c000000000000ULL,
5586       0x0000000058040000ULL,
5587       0x3002000000000000ULL,
5588       -1ULL
5589     }
5590 #endif
5591   },
5592   { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
5593     { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
5594 #ifndef DISASM_ONLY
5595     {
5596       0xc000000070000000ULL,
5597       0xf800000000000000ULL,
5598       0ULL,
5599       0ULL,
5600       0ULL
5601     },
5602     {
5603       0x0000000070000000ULL,
5604       0x3800000000000000ULL,
5605       -1ULL,
5606       -1ULL,
5607       -1ULL
5608     }
5609 #endif
5610   },
5611   { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
5612     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5613 #ifndef DISASM_ONLY
5614     {
5615       0xc00000007ffc0000ULL,
5616       0xfffe000000000000ULL,
5617       0x00000000780c0000ULL,
5618       0x3c06000000000000ULL,
5619       0ULL
5620     },
5621     {
5622       0x0000000051100000ULL,
5623       0x2840000000000000ULL,
5624       0x0000000030000000ULL,
5625       0x1c00000000000000ULL,
5626       -1ULL
5627     }
5628 #endif
5629   },
5630   { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
5631     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5632 #ifndef DISASM_ONLY
5633     {
5634       0xc00000007ffc0000ULL,
5635       0xfffe000000000000ULL,
5636       0x00000000780c0000ULL,
5637       0x3c06000000000000ULL,
5638       0ULL
5639     },
5640     {
5641       0x00000000510c0000ULL,
5642       0x283e000000000000ULL,
5643       0x0000000060040000ULL,
5644       0x3402000000000000ULL,
5645       -1ULL
5646     }
5647 #endif
5648   },
5649   { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
5650     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5651 #ifndef DISASM_ONLY
5652     {
5653       0xc00000007ffc0000ULL,
5654       0xfffe000000000000ULL,
5655       0x00000000780c0000ULL,
5656       0x3c06000000000000ULL,
5657       0ULL
5658     },
5659     {
5660       0x0000000051180000ULL,
5661       0x2844000000000000ULL,
5662       0x0000000030040000ULL,
5663       0x1c02000000000000ULL,
5664       -1ULL
5665     }
5666 #endif
5667   },
5668   { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
5669     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5670 #ifndef DISASM_ONLY
5671     {
5672       0xc00000007ffc0000ULL,
5673       0xfffe000000000000ULL,
5674       0x00000000780c0000ULL,
5675       0x3c06000000000000ULL,
5676       0ULL
5677     },
5678     {
5679       0x0000000051140000ULL,
5680       0x2842000000000000ULL,
5681       0x0000000060080000ULL,
5682       0x3404000000000000ULL,
5683       -1ULL
5684     }
5685 #endif
5686   },
5687   { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
5688     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5689 #ifndef DISASM_ONLY
5690     {
5691       0xc00000007ffc0000ULL,
5692       0xfffe000000000000ULL,
5693       0x00000000780c0000ULL,
5694       0x3c06000000000000ULL,
5695       0ULL
5696     },
5697     {
5698       0x0000000051200000ULL,
5699       0x2848000000000000ULL,
5700       0x0000000030080000ULL,
5701       0x1c04000000000000ULL,
5702       -1ULL
5703     }
5704 #endif
5705   },
5706   { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
5707     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5708 #ifndef DISASM_ONLY
5709     {
5710       0xc00000007ffc0000ULL,
5711       0xfffe000000000000ULL,
5712       0x00000000780c0000ULL,
5713       0x3c06000000000000ULL,
5714       0ULL
5715     },
5716     {
5717       0x00000000511c0000ULL,
5718       0x2846000000000000ULL,
5719       0x00000000600c0000ULL,
5720       0x3406000000000000ULL,
5721       -1ULL
5722     }
5723 #endif
5724   },
5725   { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
5726     { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
5727 #ifndef DISASM_ONLY
5728     {
5729       0xc00000007ffc0000ULL,
5730       0xfffe000000000000ULL,
5731       0x00000000780c0000ULL,
5732       0x3c06000000000000ULL,
5733       0ULL
5734     },
5735     {
5736       0x0000000060080000ULL,
5737       0x3004000000000000ULL,
5738       0x0000000078040000ULL,
5739       0x3802000000000000ULL,
5740       -1ULL
5741     }
5742 #endif
5743   },
5744   { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
5745     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
5746 #ifndef DISASM_ONLY
5747     {
5748       0xc00000007ffc0000ULL,
5749       0xfffe000000000000ULL,
5750       0ULL,
5751       0ULL,
5752       0ULL
5753     },
5754     {
5755       0x0000000051240000ULL,
5756       0x284a000000000000ULL,
5757       -1ULL,
5758       -1ULL,
5759       -1ULL
5760     }
5761 #endif
5762   },
5763   { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
5764     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
5765 #ifndef DISASM_ONLY
5766     {
5767       0xc00000007ffc0000ULL,
5768       0xfffe000000000000ULL,
5769       0ULL,
5770       0ULL,
5771       0ULL
5772     },
5773     {
5774       0x00000000600c0000ULL,
5775       0x3006000000000000ULL,
5776       -1ULL,
5777       -1ULL,
5778       -1ULL
5779     }
5780 #endif
5781   },
5782   { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
5783     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5784 #ifndef DISASM_ONLY
5785     {
5786       0xc00000007ffc0000ULL,
5787       0xfffe000000000000ULL,
5788       0x00000000780c0000ULL,
5789       0x3c06000000000000ULL,
5790       0ULL
5791     },
5792     {
5793       0x00000000512c0000ULL,
5794       0x284e000000000000ULL,
5795       0x0000000058080000ULL,
5796       0x3004000000000000ULL,
5797       -1ULL
5798     }
5799 #endif
5800   },
5801   { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
5802     { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
5803 #ifndef DISASM_ONLY
5804     {
5805       0xc00000007ffc0000ULL,
5806       0xfffe000000000000ULL,
5807       0x00000000780c0000ULL,
5808       0x3c06000000000000ULL,
5809       0ULL
5810     },
5811     {
5812       0x0000000060100000ULL,
5813       0x3008000000000000ULL,
5814       0x0000000078080000ULL,
5815       0x3804000000000000ULL,
5816       -1ULL
5817     }
5818 #endif
5819   },
5820   { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
5821     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
5822 #ifndef DISASM_ONLY
5823     {
5824       0xc00000007ffc0000ULL,
5825       0xfffe000000000000ULL,
5826       0x00000000780c0000ULL,
5827       0x3c06000000000000ULL,
5828       0ULL
5829     },
5830     {
5831       0x0000000051340000ULL,
5832       0x2852000000000000ULL,
5833       0x00000000580c0000ULL,
5834       0x3006000000000000ULL,
5835       -1ULL
5836     }
5837 #endif
5838   },
5839   { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
5840     { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
5841 #ifndef DISASM_ONLY
5842     {
5843       0xc00000007ffc0000ULL,
5844       0xfffe000000000000ULL,
5845       0x00000000780c0000ULL,
5846       0x3c06000000000000ULL,
5847       0ULL
5848     },
5849     {
5850       0x0000000060140000ULL,
5851       0x300a000000000000ULL,
5852       0x00000000780c0000ULL,
5853       0x3806000000000000ULL,
5854       -1ULL
5855     }
5856 #endif
5857   },
5858   { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
5859     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
5860 #ifndef DISASM_ONLY
5861     {
5862       0xc00000007ffc0000ULL,
5863       0xfffe000000000000ULL,
5864       0ULL,
5865       0ULL,
5866       0ULL
5867     },
5868     {
5869       0x0000000051300000ULL,
5870       0x2850000000000000ULL,
5871       -1ULL,
5872       -1ULL,
5873       -1ULL
5874     }
5875 #endif
5876   },
5877   { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
5878     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
5879 #ifndef DISASM_ONLY
5880     {
5881       0xc00000007ffc0000ULL,
5882       0xfffe000000000000ULL,
5883       0ULL,
5884       0ULL,
5885       0ULL
5886     },
5887     {
5888       0x0000000060180000ULL,
5889       0x300c000000000000ULL,
5890       -1ULL,
5891       -1ULL,
5892       -1ULL
5893     }
5894 #endif
5895   },
5896   { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
5897     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5898 #ifndef DISASM_ONLY
5899     {
5900       0xc00000007ffc0000ULL,
5901       0ULL,
5902       0ULL,
5903       0ULL,
5904       0ULL
5905     },
5906     {
5907       0x0000000051380000ULL,
5908       -1ULL,
5909       -1ULL,
5910       -1ULL,
5911       -1ULL
5912     }
5913 #endif
5914   },
5915   { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
5916     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
5917 #ifndef DISASM_ONLY
5918     {
5919       0ULL,
5920       0xfffe000000000000ULL,
5921       0ULL,
5922       0ULL,
5923       0xc200000004000000ULL
5924     },
5925     {
5926       -1ULL,
5927       0x2862000000000000ULL,
5928       -1ULL,
5929       -1ULL,
5930       0xc200000004000000ULL
5931     }
5932 #endif
5933   },
5934   { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
5935     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
5936 #ifndef DISASM_ONLY
5937     {
5938       0ULL,
5939       0xfffe000000000000ULL,
5940       0ULL,
5941       0ULL,
5942       0xc200000004000000ULL
5943     },
5944     {
5945       -1ULL,
5946       0x2854000000000000ULL,
5947       -1ULL,
5948       -1ULL,
5949       0xc000000000000000ULL
5950     }
5951 #endif
5952   },
5953   { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
5954     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
5955 #ifndef DISASM_ONLY
5956     {
5957       0ULL,
5958       0xfff8000000000000ULL,
5959       0ULL,
5960       0ULL,
5961       0ULL
5962     },
5963     {
5964       -1ULL,
5965       0x18c8000000000000ULL,
5966       -1ULL,
5967       -1ULL,
5968       -1ULL
5969     }
5970 #endif
5971   },
5972   { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
5973     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
5974 #ifndef DISASM_ONLY
5975     {
5976       0ULL,
5977       0xfffe000000000000ULL,
5978       0ULL,
5979       0ULL,
5980       0xc200000004000000ULL
5981     },
5982     {
5983       -1ULL,
5984       0x2856000000000000ULL,
5985       -1ULL,
5986       -1ULL,
5987       0xc000000004000000ULL
5988     }
5989 #endif
5990   },
5991   { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
5992     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
5993 #ifndef DISASM_ONLY
5994     {
5995       0ULL,
5996       0xfff8000000000000ULL,
5997       0ULL,
5998       0ULL,
5999       0ULL
6000     },
6001     {
6002       -1ULL,
6003       0x18d0000000000000ULL,
6004       -1ULL,
6005       -1ULL,
6006       -1ULL
6007     }
6008 #endif
6009   },
6010   { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
6011     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
6012 #ifndef DISASM_ONLY
6013     {
6014       0ULL,
6015       0xfffe000000000000ULL,
6016       0ULL,
6017       0ULL,
6018       0xc200000004000000ULL
6019     },
6020     {
6021       -1ULL,
6022       0x2858000000000000ULL,
6023       -1ULL,
6024       -1ULL,
6025       0xc200000000000000ULL
6026     }
6027 #endif
6028   },
6029   { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
6030     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6031 #ifndef DISASM_ONLY
6032     {
6033       0ULL,
6034       0xfff8000000000000ULL,
6035       0ULL,
6036       0ULL,
6037       0ULL
6038     },
6039     {
6040       -1ULL,
6041       0x18d8000000000000ULL,
6042       -1ULL,
6043       -1ULL,
6044       -1ULL
6045     }
6046 #endif
6047   },
6048   { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
6049     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6050 #ifndef DISASM_ONLY
6051     {
6052       0ULL,
6053       0xfff8000000000000ULL,
6054       0ULL,
6055       0ULL,
6056       0ULL
6057     },
6058     {
6059       -1ULL,
6060       0x1900000000000000ULL,
6061       -1ULL,
6062       -1ULL,
6063       -1ULL
6064     }
6065 #endif
6066   },
6067   { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
6068     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
6069 #ifndef DISASM_ONLY
6070     {
6071       0ULL,
6072       0xfffe000000000000ULL,
6073       0ULL,
6074       0ULL,
6075       0ULL
6076     },
6077     {
6078       -1ULL,
6079       0x2860000000000000ULL,
6080       -1ULL,
6081       -1ULL,
6082       -1ULL
6083     }
6084 #endif
6085   },
6086   { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
6087     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
6088 #ifndef DISASM_ONLY
6089     {
6090       0ULL,
6091       0xfffe000000000000ULL,
6092       0ULL,
6093       0ULL,
6094       0ULL
6095     },
6096     {
6097       -1ULL,
6098       0x285a000000000000ULL,
6099       -1ULL,
6100       -1ULL,
6101       -1ULL
6102     }
6103 #endif
6104   },
6105   { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
6106     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6107 #ifndef DISASM_ONLY
6108     {
6109       0ULL,
6110       0xfff8000000000000ULL,
6111       0ULL,
6112       0ULL,
6113       0ULL
6114     },
6115     {
6116       -1ULL,
6117       0x18e0000000000000ULL,
6118       -1ULL,
6119       -1ULL,
6120       -1ULL
6121     }
6122 #endif
6123   },
6124   { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
6125     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
6126 #ifndef DISASM_ONLY
6127     {
6128       0ULL,
6129       0xfffe000000000000ULL,
6130       0ULL,
6131       0ULL,
6132       0ULL
6133     },
6134     {
6135       -1ULL,
6136       0x285c000000000000ULL,
6137       -1ULL,
6138       -1ULL,
6139       -1ULL
6140     }
6141 #endif
6142   },
6143   { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
6144     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6145 #ifndef DISASM_ONLY
6146     {
6147       0ULL,
6148       0xfff8000000000000ULL,
6149       0ULL,
6150       0ULL,
6151       0ULL
6152     },
6153     {
6154       -1ULL,
6155       0x18e8000000000000ULL,
6156       -1ULL,
6157       -1ULL,
6158       -1ULL
6159     }
6160 #endif
6161   },
6162   { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
6163     { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
6164 #ifndef DISASM_ONLY
6165     {
6166       0ULL,
6167       0xfffe000000000000ULL,
6168       0ULL,
6169       0ULL,
6170       0ULL
6171     },
6172     {
6173       -1ULL,
6174       0x285e000000000000ULL,
6175       -1ULL,
6176       -1ULL,
6177       -1ULL
6178     }
6179 #endif
6180   },
6181   { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
6182     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6183 #ifndef DISASM_ONLY
6184     {
6185       0ULL,
6186       0xfff8000000000000ULL,
6187       0ULL,
6188       0ULL,
6189       0ULL
6190     },
6191     {
6192       -1ULL,
6193       0x18f0000000000000ULL,
6194       -1ULL,
6195       -1ULL,
6196       -1ULL
6197     }
6198 #endif
6199   },
6200   { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
6201     { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
6202 #ifndef DISASM_ONLY
6203     {
6204       0ULL,
6205       0xfff8000000000000ULL,
6206       0ULL,
6207       0ULL,
6208       0ULL
6209     },
6210     {
6211       -1ULL,
6212       0x18f8000000000000ULL,
6213       -1ULL,
6214       -1ULL,
6215       -1ULL
6216     }
6217 #endif
6218   },
6219   { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
6220     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
6221 #ifndef DISASM_ONLY
6222     {
6223       0xc00000007ffc0000ULL,
6224       0xfffe000000000000ULL,
6225       0x00000000780c0000ULL,
6226       0x3c06000000000000ULL,
6227       0ULL
6228     },
6229     {
6230       0x0000000051440000ULL,
6231       0x2868000000000000ULL,
6232       0x00000000280c0000ULL,
6233       0x1806000000000000ULL,
6234       -1ULL
6235     }
6236 #endif
6237   },
6238   { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
6239     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
6240 #ifndef DISASM_ONLY
6241     {
6242       0xc00000007ffc0000ULL,
6243       0xfffe000000000000ULL,
6244       0x00000000780c0000ULL,
6245       0x3c06000000000000ULL,
6246       0ULL
6247     },
6248     {
6249       0x0000000051400000ULL,
6250       0x2866000000000000ULL,
6251       0x0000000028080000ULL,
6252       0x1804000000000000ULL,
6253       -1ULL
6254     }
6255 #endif
6256   },
6257   { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
6258     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6259 #ifndef DISASM_ONLY
6260     {
6261       0xc00000007ffc0000ULL,
6262       0xfffe000000000000ULL,
6263       0ULL,
6264       0ULL,
6265       0ULL
6266     },
6267     {
6268       0x00000000513c0000ULL,
6269       0x2864000000000000ULL,
6270       -1ULL,
6271       -1ULL,
6272       -1ULL
6273     }
6274 #endif
6275   },
6276   { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
6277     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
6278 #ifndef DISASM_ONLY
6279     {
6280       0ULL,
6281       0xfffff80000000000ULL,
6282       0ULL,
6283       0ULL,
6284       0ULL
6285     },
6286     {
6287       -1ULL,
6288       0x286b100000000000ULL,
6289       -1ULL,
6290       -1ULL,
6291       -1ULL
6292     }
6293 #endif
6294   },
6295   { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
6296     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
6297 #ifndef DISASM_ONLY
6298     {
6299       0ULL,
6300       0xfffff80000000000ULL,
6301       0ULL,
6302       0ULL,
6303       0ULL
6304     },
6305     {
6306       -1ULL,
6307       0x286b180000000000ULL,
6308       -1ULL,
6309       -1ULL,
6310       -1ULL
6311     }
6312 #endif
6313   },
6314   { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
6315     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
6316 #ifndef DISASM_ONLY
6317     {
6318       0ULL,
6319       0xfffff80000000000ULL,
6320       0ULL,
6321       0ULL,
6322       0ULL
6323     },
6324     {
6325       -1ULL,
6326       0x286b200000000000ULL,
6327       -1ULL,
6328       -1ULL,
6329       -1ULL
6330     }
6331 #endif
6332   },
6333   { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
6334     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
6335 #ifndef DISASM_ONLY
6336     {
6337       0ULL,
6338       0xfffff80000000000ULL,
6339       0ULL,
6340       0ULL,
6341       0ULL
6342     },
6343     {
6344       -1ULL,
6345       0x286b280000000000ULL,
6346       -1ULL,
6347       -1ULL,
6348       -1ULL
6349     }
6350 #endif
6351   },
6352   { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
6353     { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
6354 #ifndef DISASM_ONLY
6355     {
6356       0xc00000007ffff000ULL,
6357       0ULL,
6358       0x00000000780ff000ULL,
6359       0ULL,
6360       0ULL
6361     },
6362     {
6363       0x0000000051489000ULL,
6364       -1ULL,
6365       0x00000000300c9000ULL,
6366       -1ULL,
6367       -1ULL
6368     }
6369 #endif
6370   },
6371   { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
6372     { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
6373 #ifndef DISASM_ONLY
6374     {
6375       0xc00000007ffff000ULL,
6376       0ULL,
6377       0x00000000780ff000ULL,
6378       0ULL,
6379       0ULL
6380     },
6381     {
6382       0x000000005148a000ULL,
6383       -1ULL,
6384       0x00000000300ca000ULL,
6385       -1ULL,
6386       -1ULL
6387     }
6388 #endif
6389   },
6390   { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
6391     { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
6392 #ifndef DISASM_ONLY
6393     {
6394       0xc00000007ffff000ULL,
6395       0ULL,
6396       0x00000000780ff000ULL,
6397       0ULL,
6398       0ULL
6399     },
6400     {
6401       0x000000005148b000ULL,
6402       -1ULL,
6403       0x00000000300cb000ULL,
6404       -1ULL,
6405       -1ULL
6406     }
6407 #endif
6408   },
6409   { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
6410     { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
6411 #ifndef DISASM_ONLY
6412     {
6413       0xc00000007ffff000ULL,
6414       0ULL,
6415       0x00000000780ff000ULL,
6416       0ULL,
6417       0ULL
6418     },
6419     {
6420       0x000000005148c000ULL,
6421       -1ULL,
6422       0x00000000300cc000ULL,
6423       -1ULL,
6424       -1ULL
6425     }
6426 #endif
6427   },
6428   { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
6429     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6430 #ifndef DISASM_ONLY
6431     {
6432       0xc00000007ffc0000ULL,
6433       0xfffe000000000000ULL,
6434       0ULL,
6435       0ULL,
6436       0ULL
6437     },
6438     {
6439       0x0000000051500000ULL,
6440       0x286e000000000000ULL,
6441       -1ULL,
6442       -1ULL,
6443       -1ULL
6444     }
6445 #endif
6446   },
6447   { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
6448     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6449 #ifndef DISASM_ONLY
6450     {
6451       0xc00000007ff00000ULL,
6452       0xfff8000000000000ULL,
6453       0ULL,
6454       0ULL,
6455       0ULL
6456     },
6457     {
6458       0x0000000040800000ULL,
6459       0x1908000000000000ULL,
6460       -1ULL,
6461       -1ULL,
6462       -1ULL
6463     }
6464 #endif
6465   },
6466   { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
6467     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6468 #ifndef DISASM_ONLY
6469     {
6470       0xc00000007ffc0000ULL,
6471       0xfffe000000000000ULL,
6472       0ULL,
6473       0ULL,
6474       0ULL
6475     },
6476     {
6477       0x00000000514c0000ULL,
6478       0x286c000000000000ULL,
6479       -1ULL,
6480       -1ULL,
6481       -1ULL
6482     }
6483 #endif
6484   },
6485   { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
6486     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6487 #ifndef DISASM_ONLY
6488     {
6489       0xc00000007ffc0000ULL,
6490       0ULL,
6491       0ULL,
6492       0ULL,
6493       0ULL
6494     },
6495     {
6496       0x0000000051540000ULL,
6497       -1ULL,
6498       -1ULL,
6499       -1ULL,
6500       -1ULL
6501     }
6502 #endif
6503   },
6504   { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
6505     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6506 #ifndef DISASM_ONLY
6507     {
6508       0xc00000007ffc0000ULL,
6509       0ULL,
6510       0ULL,
6511       0ULL,
6512       0ULL
6513     },
6514     {
6515       0x0000000051580000ULL,
6516       -1ULL,
6517       -1ULL,
6518       -1ULL,
6519       -1ULL
6520     }
6521 #endif
6522   },
6523   { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
6524     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6525 #ifndef DISASM_ONLY
6526     {
6527       0xc00000007ffc0000ULL,
6528       0xfffe000000000000ULL,
6529       0ULL,
6530       0ULL,
6531       0ULL
6532     },
6533     {
6534       0x00000000515c0000ULL,
6535       0x2870000000000000ULL,
6536       -1ULL,
6537       -1ULL,
6538       -1ULL
6539     }
6540 #endif
6541   },
6542   { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
6543     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6544 #ifndef DISASM_ONLY
6545     {
6546       0xc00000007ff00000ULL,
6547       0xfff8000000000000ULL,
6548       0ULL,
6549       0ULL,
6550       0ULL
6551     },
6552     {
6553       0x0000000040900000ULL,
6554       0x1910000000000000ULL,
6555       -1ULL,
6556       -1ULL,
6557       -1ULL
6558     }
6559 #endif
6560   },
6561   { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
6562     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6563 #ifndef DISASM_ONLY
6564     {
6565       0xc00000007ffc0000ULL,
6566       0xfffe000000000000ULL,
6567       0ULL,
6568       0ULL,
6569       0ULL
6570     },
6571     {
6572       0x0000000051600000ULL,
6573       0x2872000000000000ULL,
6574       -1ULL,
6575       -1ULL,
6576       -1ULL
6577     }
6578 #endif
6579   },
6580   { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
6581     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6582 #ifndef DISASM_ONLY
6583     {
6584       0xc00000007ffc0000ULL,
6585       0xfffe000000000000ULL,
6586       0ULL,
6587       0ULL,
6588       0ULL
6589     },
6590     {
6591       0x0000000051640000ULL,
6592       0x2874000000000000ULL,
6593       -1ULL,
6594       -1ULL,
6595       -1ULL
6596     }
6597 #endif
6598   },
6599   { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
6600     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6601 #ifndef DISASM_ONLY
6602     {
6603       0xc00000007ffc0000ULL,
6604       0xfffe000000000000ULL,
6605       0ULL,
6606       0ULL,
6607       0ULL
6608     },
6609     {
6610       0x0000000051680000ULL,
6611       0x2876000000000000ULL,
6612       -1ULL,
6613       -1ULL,
6614       -1ULL
6615     }
6616 #endif
6617   },
6618   { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
6619     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6620 #ifndef DISASM_ONLY
6621     {
6622       0xc00000007ff00000ULL,
6623       0xfff8000000000000ULL,
6624       0ULL,
6625       0ULL,
6626       0ULL
6627     },
6628     {
6629       0x0000000040a00000ULL,
6630       0x1918000000000000ULL,
6631       -1ULL,
6632       -1ULL,
6633       -1ULL
6634     }
6635 #endif
6636   },
6637   { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
6638     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6639 #ifndef DISASM_ONLY
6640     {
6641       0xc00000007ffc0000ULL,
6642       0xfffe000000000000ULL,
6643       0ULL,
6644       0ULL,
6645       0ULL
6646     },
6647     {
6648       0x00000000516c0000ULL,
6649       0x2878000000000000ULL,
6650       -1ULL,
6651       -1ULL,
6652       -1ULL
6653     }
6654 #endif
6655   },
6656   { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
6657     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6658 #ifndef DISASM_ONLY
6659     {
6660       0xc00000007ff00000ULL,
6661       0xfff8000000000000ULL,
6662       0ULL,
6663       0ULL,
6664       0ULL
6665     },
6666     {
6667       0x0000000040b00000ULL,
6668       0x1920000000000000ULL,
6669       -1ULL,
6670       -1ULL,
6671       -1ULL
6672     }
6673 #endif
6674   },
6675   { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
6676     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6677 #ifndef DISASM_ONLY
6678     {
6679       0xc00000007ffc0000ULL,
6680       0xfffe000000000000ULL,
6681       0ULL,
6682       0ULL,
6683       0ULL
6684     },
6685     {
6686       0x0000000051700000ULL,
6687       0x287a000000000000ULL,
6688       -1ULL,
6689       -1ULL,
6690       -1ULL
6691     }
6692 #endif
6693   },
6694   { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
6695     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6696 #ifndef DISASM_ONLY
6697     {
6698       0xc00000007ffc0000ULL,
6699       0ULL,
6700       0ULL,
6701       0ULL,
6702       0ULL
6703     },
6704     {
6705       0x0000000052880000ULL,
6706       -1ULL,
6707       -1ULL,
6708       -1ULL,
6709       -1ULL
6710     }
6711 #endif
6712   },
6713   { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
6714     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6715 #ifndef DISASM_ONLY
6716     {
6717       0xc00000007ffc0000ULL,
6718       0ULL,
6719       0ULL,
6720       0ULL,
6721       0ULL
6722     },
6723     {
6724       0x0000000052840000ULL,
6725       -1ULL,
6726       -1ULL,
6727       -1ULL,
6728       -1ULL
6729     }
6730 #endif
6731   },
6732   { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
6733     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6734 #ifndef DISASM_ONLY
6735     {
6736       0xc00000007ffc0000ULL,
6737       0ULL,
6738       0ULL,
6739       0ULL,
6740       0ULL
6741     },
6742     {
6743       0x0000000051780000ULL,
6744       -1ULL,
6745       -1ULL,
6746       -1ULL,
6747       -1ULL
6748     }
6749 #endif
6750   },
6751   { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
6752     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6753 #ifndef DISASM_ONLY
6754     {
6755       0xc00000007ffc0000ULL,
6756       0ULL,
6757       0ULL,
6758       0ULL,
6759       0ULL
6760     },
6761     {
6762       0x0000000051740000ULL,
6763       -1ULL,
6764       -1ULL,
6765       -1ULL,
6766       -1ULL
6767     }
6768 #endif
6769   },
6770   { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
6771     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6772 #ifndef DISASM_ONLY
6773     {
6774       0xc00000007ffc0000ULL,
6775       0ULL,
6776       0ULL,
6777       0ULL,
6778       0ULL
6779     },
6780     {
6781       0x0000000051880000ULL,
6782       -1ULL,
6783       -1ULL,
6784       -1ULL,
6785       -1ULL
6786     }
6787 #endif
6788   },
6789   { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
6790     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6791 #ifndef DISASM_ONLY
6792     {
6793       0xc00000007ffc0000ULL,
6794       0ULL,
6795       0ULL,
6796       0ULL,
6797       0ULL
6798     },
6799     {
6800       0x00000000517c0000ULL,
6801       -1ULL,
6802       -1ULL,
6803       -1ULL,
6804       -1ULL
6805     }
6806 #endif
6807   },
6808   { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
6809     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6810 #ifndef DISASM_ONLY
6811     {
6812       0xc00000007ffc0000ULL,
6813       0ULL,
6814       0ULL,
6815       0ULL,
6816       0ULL
6817     },
6818     {
6819       0x0000000052900000ULL,
6820       -1ULL,
6821       -1ULL,
6822       -1ULL,
6823       -1ULL
6824     }
6825 #endif
6826   },
6827   { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
6828     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6829 #ifndef DISASM_ONLY
6830     {
6831       0xc00000007ffc0000ULL,
6832       0ULL,
6833       0ULL,
6834       0ULL,
6835       0ULL
6836     },
6837     {
6838       0x00000000528c0000ULL,
6839       -1ULL,
6840       -1ULL,
6841       -1ULL,
6842       -1ULL
6843     }
6844 #endif
6845   },
6846   { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
6847     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6848 #ifndef DISASM_ONLY
6849     {
6850       0xc00000007ffc0000ULL,
6851       0ULL,
6852       0ULL,
6853       0ULL,
6854       0ULL
6855     },
6856     {
6857       0x0000000051840000ULL,
6858       -1ULL,
6859       -1ULL,
6860       -1ULL,
6861       -1ULL
6862     }
6863 #endif
6864   },
6865   { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
6866     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6867 #ifndef DISASM_ONLY
6868     {
6869       0xc00000007ffc0000ULL,
6870       0ULL,
6871       0ULL,
6872       0ULL,
6873       0ULL
6874     },
6875     {
6876       0x0000000051800000ULL,
6877       -1ULL,
6878       -1ULL,
6879       -1ULL,
6880       -1ULL
6881     }
6882 #endif
6883   },
6884   { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
6885     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6886 #ifndef DISASM_ONLY
6887     {
6888       0xc00000007ffc0000ULL,
6889       0xfffe000000000000ULL,
6890       0ULL,
6891       0ULL,
6892       0ULL
6893     },
6894     {
6895       0x00000000518c0000ULL,
6896       0x287c000000000000ULL,
6897       -1ULL,
6898       -1ULL,
6899       -1ULL
6900     }
6901 #endif
6902   },
6903   { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
6904     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6905 #ifndef DISASM_ONLY
6906     {
6907       0xc00000007ffc0000ULL,
6908       0xfffe000000000000ULL,
6909       0ULL,
6910       0ULL,
6911       0ULL
6912     },
6913     {
6914       0x0000000051900000ULL,
6915       0x287e000000000000ULL,
6916       -1ULL,
6917       -1ULL,
6918       -1ULL
6919     }
6920 #endif
6921   },
6922   { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
6923     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6924 #ifndef DISASM_ONLY
6925     {
6926       0xc00000007ffc0000ULL,
6927       0xfffe000000000000ULL,
6928       0ULL,
6929       0ULL,
6930       0ULL
6931     },
6932     {
6933       0x0000000051940000ULL,
6934       0x2880000000000000ULL,
6935       -1ULL,
6936       -1ULL,
6937       -1ULL
6938     }
6939 #endif
6940   },
6941   { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
6942     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6943 #ifndef DISASM_ONLY
6944     {
6945       0xc00000007ff00000ULL,
6946       0xfff8000000000000ULL,
6947       0ULL,
6948       0ULL,
6949       0ULL
6950     },
6951     {
6952       0x0000000040c00000ULL,
6953       0x1928000000000000ULL,
6954       -1ULL,
6955       -1ULL,
6956       -1ULL
6957     }
6958 #endif
6959   },
6960   { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
6961     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
6962 #ifndef DISASM_ONLY
6963     {
6964       0xc00000007ffc0000ULL,
6965       0xfffe000000000000ULL,
6966       0ULL,
6967       0ULL,
6968       0ULL
6969     },
6970     {
6971       0x0000000051980000ULL,
6972       0x2882000000000000ULL,
6973       -1ULL,
6974       -1ULL,
6975       -1ULL
6976     }
6977 #endif
6978   },
6979   { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
6980     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
6981 #ifndef DISASM_ONLY
6982     {
6983       0xc00000007ff00000ULL,
6984       0xfff8000000000000ULL,
6985       0ULL,
6986       0ULL,
6987       0ULL
6988     },
6989     {
6990       0x0000000040d00000ULL,
6991       0x1930000000000000ULL,
6992       -1ULL,
6993       -1ULL,
6994       -1ULL
6995     }
6996 #endif
6997   },
6998   { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
6999     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7000 #ifndef DISASM_ONLY
7001     {
7002       0xc00000007ffc0000ULL,
7003       0xfffe000000000000ULL,
7004       0ULL,
7005       0ULL,
7006       0ULL
7007     },
7008     {
7009       0x00000000519c0000ULL,
7010       0x2884000000000000ULL,
7011       -1ULL,
7012       -1ULL,
7013       -1ULL
7014     }
7015 #endif
7016   },
7017   { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
7018     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7019 #ifndef DISASM_ONLY
7020     {
7021       0xc00000007ffc0000ULL,
7022       0ULL,
7023       0ULL,
7024       0ULL,
7025       0ULL
7026     },
7027     {
7028       0x0000000051a00000ULL,
7029       -1ULL,
7030       -1ULL,
7031       -1ULL,
7032       -1ULL
7033     }
7034 #endif
7035   },
7036   { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
7037     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7038 #ifndef DISASM_ONLY
7039     {
7040       0xc00000007ffc0000ULL,
7041       0ULL,
7042       0ULL,
7043       0ULL,
7044       0ULL
7045     },
7046     {
7047       0x0000000051a80000ULL,
7048       -1ULL,
7049       -1ULL,
7050       -1ULL,
7051       -1ULL
7052     }
7053 #endif
7054   },
7055   { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
7056     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7057 #ifndef DISASM_ONLY
7058     {
7059       0xc00000007ffc0000ULL,
7060       0ULL,
7061       0ULL,
7062       0ULL,
7063       0ULL
7064     },
7065     {
7066       0x0000000051a40000ULL,
7067       -1ULL,
7068       -1ULL,
7069       -1ULL,
7070       -1ULL
7071     }
7072 #endif
7073   },
7074   { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
7075     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7076 #ifndef DISASM_ONLY
7077     {
7078       0xc00000007ffc0000ULL,
7079       0xfffe000000000000ULL,
7080       0ULL,
7081       0ULL,
7082       0ULL
7083     },
7084     {
7085       0x0000000051ac0000ULL,
7086       0x2886000000000000ULL,
7087       -1ULL,
7088       -1ULL,
7089       -1ULL
7090     }
7091 #endif
7092   },
7093   { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
7094     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7095 #ifndef DISASM_ONLY
7096     {
7097       0xc00000007ffc0000ULL,
7098       0ULL,
7099       0ULL,
7100       0ULL,
7101       0ULL
7102     },
7103     {
7104       0x0000000051b00000ULL,
7105       -1ULL,
7106       -1ULL,
7107       -1ULL,
7108       -1ULL
7109     }
7110 #endif
7111   },
7112   { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
7113     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7114 #ifndef DISASM_ONLY
7115     {
7116       0xc00000007ffc0000ULL,
7117       0ULL,
7118       0ULL,
7119       0ULL,
7120       0ULL
7121     },
7122     {
7123       0x0000000051b40000ULL,
7124       -1ULL,
7125       -1ULL,
7126       -1ULL,
7127       -1ULL
7128     }
7129 #endif
7130   },
7131   { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
7132     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7133 #ifndef DISASM_ONLY
7134     {
7135       0xc00000007ffc0000ULL,
7136       0xfffe000000000000ULL,
7137       0ULL,
7138       0ULL,
7139       0ULL
7140     },
7141     {
7142       0x0000000051b80000ULL,
7143       0x2888000000000000ULL,
7144       -1ULL,
7145       -1ULL,
7146       -1ULL
7147     }
7148 #endif
7149   },
7150   { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
7151     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
7152 #ifndef DISASM_ONLY
7153     {
7154       0xc00000007ffc0000ULL,
7155       0xfffe000000000000ULL,
7156       0ULL,
7157       0ULL,
7158       0ULL
7159     },
7160     {
7161       0x00000000601c0000ULL,
7162       0x300e000000000000ULL,
7163       -1ULL,
7164       -1ULL,
7165       -1ULL
7166     }
7167 #endif
7168   },
7169   { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
7170     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7171 #ifndef DISASM_ONLY
7172     {
7173       0xc00000007ffc0000ULL,
7174       0xfffe000000000000ULL,
7175       0ULL,
7176       0ULL,
7177       0ULL
7178     },
7179     {
7180       0x0000000051bc0000ULL,
7181       0x288a000000000000ULL,
7182       -1ULL,
7183       -1ULL,
7184       -1ULL
7185     }
7186 #endif
7187   },
7188   { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
7189     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
7190 #ifndef DISASM_ONLY
7191     {
7192       0xc00000007ffc0000ULL,
7193       0xfffe000000000000ULL,
7194       0ULL,
7195       0ULL,
7196       0ULL
7197     },
7198     {
7199       0x0000000060200000ULL,
7200       0x3010000000000000ULL,
7201       -1ULL,
7202       -1ULL,
7203       -1ULL
7204     }
7205 #endif
7206   },
7207   { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
7208     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7209 #ifndef DISASM_ONLY
7210     {
7211       0xc00000007ffc0000ULL,
7212       0xfffe000000000000ULL,
7213       0ULL,
7214       0ULL,
7215       0ULL
7216     },
7217     {
7218       0x0000000051c00000ULL,
7219       0x288c000000000000ULL,
7220       -1ULL,
7221       -1ULL,
7222       -1ULL
7223     }
7224 #endif
7225   },
7226   { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
7227     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
7228 #ifndef DISASM_ONLY
7229     {
7230       0xc00000007ffc0000ULL,
7231       0xfffe000000000000ULL,
7232       0ULL,
7233       0ULL,
7234       0ULL
7235     },
7236     {
7237       0x0000000060240000ULL,
7238       0x3012000000000000ULL,
7239       -1ULL,
7240       -1ULL,
7241       -1ULL
7242     }
7243 #endif
7244   },
7245   { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
7246     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7247 #ifndef DISASM_ONLY
7248     {
7249       0xc00000007ffc0000ULL,
7250       0xfffe000000000000ULL,
7251       0ULL,
7252       0ULL,
7253       0ULL
7254     },
7255     {
7256       0x0000000051c80000ULL,
7257       0x2890000000000000ULL,
7258       -1ULL,
7259       -1ULL,
7260       -1ULL
7261     }
7262 #endif
7263   },
7264   { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
7265     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7266 #ifndef DISASM_ONLY
7267     {
7268       0xc00000007ffc0000ULL,
7269       0xfffe000000000000ULL,
7270       0ULL,
7271       0ULL,
7272       0ULL
7273     },
7274     {
7275       0x0000000051c40000ULL,
7276       0x288e000000000000ULL,
7277       -1ULL,
7278       -1ULL,
7279       -1ULL
7280     }
7281 #endif
7282   },
7283   { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
7284     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7285 #ifndef DISASM_ONLY
7286     {
7287       0xc00000007ffc0000ULL,
7288       0xfffe000000000000ULL,
7289       0ULL,
7290       0ULL,
7291       0ULL
7292     },
7293     {
7294       0x0000000051d00000ULL,
7295       0x2894000000000000ULL,
7296       -1ULL,
7297       -1ULL,
7298       -1ULL
7299     }
7300 #endif
7301   },
7302   { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
7303     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7304 #ifndef DISASM_ONLY
7305     {
7306       0xc00000007ff00000ULL,
7307       0xfff8000000000000ULL,
7308       0ULL,
7309       0ULL,
7310       0ULL
7311     },
7312     {
7313       0x0000000040e00000ULL,
7314       0x1938000000000000ULL,
7315       -1ULL,
7316       -1ULL,
7317       -1ULL
7318     }
7319 #endif
7320   },
7321   { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
7322     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7323 #ifndef DISASM_ONLY
7324     {
7325       0xc00000007ffc0000ULL,
7326       0xfffe000000000000ULL,
7327       0ULL,
7328       0ULL,
7329       0ULL
7330     },
7331     {
7332       0x0000000051cc0000ULL,
7333       0x2892000000000000ULL,
7334       -1ULL,
7335       -1ULL,
7336       -1ULL
7337     }
7338 #endif
7339   },
7340   { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
7341     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7342 #ifndef DISASM_ONLY
7343     {
7344       0xc00000007ffc0000ULL,
7345       0ULL,
7346       0ULL,
7347       0ULL,
7348       0ULL
7349     },
7350     {
7351       0x0000000051d40000ULL,
7352       -1ULL,
7353       -1ULL,
7354       -1ULL,
7355       -1ULL
7356     }
7357 #endif
7358   },
7359   { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
7360     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7361 #ifndef DISASM_ONLY
7362     {
7363       0xc00000007ffc0000ULL,
7364       0ULL,
7365       0ULL,
7366       0ULL,
7367       0ULL
7368     },
7369     {
7370       0x0000000051d80000ULL,
7371       -1ULL,
7372       -1ULL,
7373       -1ULL,
7374       -1ULL
7375     }
7376 #endif
7377   },
7378   { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
7379     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7380 #ifndef DISASM_ONLY
7381     {
7382       0xc00000007ffc0000ULL,
7383       0xfffe000000000000ULL,
7384       0ULL,
7385       0ULL,
7386       0ULL
7387     },
7388     {
7389       0x0000000051dc0000ULL,
7390       0x2896000000000000ULL,
7391       -1ULL,
7392       -1ULL,
7393       -1ULL
7394     }
7395 #endif
7396   },
7397   { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
7398     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7399 #ifndef DISASM_ONLY
7400     {
7401       0xc00000007ff00000ULL,
7402       0xfff8000000000000ULL,
7403       0ULL,
7404       0ULL,
7405       0ULL
7406     },
7407     {
7408       0x0000000040f00000ULL,
7409       0x1940000000000000ULL,
7410       -1ULL,
7411       -1ULL,
7412       -1ULL
7413     }
7414 #endif
7415   },
7416   { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
7417     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7418 #ifndef DISASM_ONLY
7419     {
7420       0xc00000007ffc0000ULL,
7421       0xfffe000000000000ULL,
7422       0ULL,
7423       0ULL,
7424       0ULL
7425     },
7426     {
7427       0x0000000051e00000ULL,
7428       0x2898000000000000ULL,
7429       -1ULL,
7430       -1ULL,
7431       -1ULL
7432     }
7433 #endif
7434   },
7435   { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
7436     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7437 #ifndef DISASM_ONLY
7438     {
7439       0xc00000007ffc0000ULL,
7440       0xfffe000000000000ULL,
7441       0ULL,
7442       0ULL,
7443       0ULL
7444     },
7445     {
7446       0x0000000051e40000ULL,
7447       0x289a000000000000ULL,
7448       -1ULL,
7449       -1ULL,
7450       -1ULL
7451     }
7452 #endif
7453   },
7454   { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
7455     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7456 #ifndef DISASM_ONLY
7457     {
7458       0xc00000007ffc0000ULL,
7459       0xfffe000000000000ULL,
7460       0ULL,
7461       0ULL,
7462       0ULL
7463     },
7464     {
7465       0x0000000051e80000ULL,
7466       0x289c000000000000ULL,
7467       -1ULL,
7468       -1ULL,
7469       -1ULL
7470     }
7471 #endif
7472   },
7473   { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
7474     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7475 #ifndef DISASM_ONLY
7476     {
7477       0xc00000007ff00000ULL,
7478       0xfff8000000000000ULL,
7479       0ULL,
7480       0ULL,
7481       0ULL
7482     },
7483     {
7484       0x0000000041000000ULL,
7485       0x1948000000000000ULL,
7486       -1ULL,
7487       -1ULL,
7488       -1ULL
7489     }
7490 #endif
7491   },
7492   { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
7493     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7494 #ifndef DISASM_ONLY
7495     {
7496       0xc00000007ffc0000ULL,
7497       0xfffe000000000000ULL,
7498       0ULL,
7499       0ULL,
7500       0ULL
7501     },
7502     {
7503       0x0000000051ec0000ULL,
7504       0x289e000000000000ULL,
7505       -1ULL,
7506       -1ULL,
7507       -1ULL
7508     }
7509 #endif
7510   },
7511   { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
7512     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7513 #ifndef DISASM_ONLY
7514     {
7515       0xc00000007ff00000ULL,
7516       0xfff8000000000000ULL,
7517       0ULL,
7518       0ULL,
7519       0ULL
7520     },
7521     {
7522       0x0000000041100000ULL,
7523       0x1950000000000000ULL,
7524       -1ULL,
7525       -1ULL,
7526       -1ULL
7527     }
7528 #endif
7529   },
7530   { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
7531     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7532 #ifndef DISASM_ONLY
7533     {
7534       0xc00000007ffc0000ULL,
7535       0xfffe000000000000ULL,
7536       0ULL,
7537       0ULL,
7538       0ULL
7539     },
7540     {
7541       0x0000000051f00000ULL,
7542       0x28a0000000000000ULL,
7543       -1ULL,
7544       -1ULL,
7545       -1ULL
7546     }
7547 #endif
7548   },
7549   { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
7550     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7551 #ifndef DISASM_ONLY
7552     {
7553       0xc00000007ffc0000ULL,
7554       0ULL,
7555       0ULL,
7556       0ULL,
7557       0ULL
7558     },
7559     {
7560       0x0000000051f80000ULL,
7561       -1ULL,
7562       -1ULL,
7563       -1ULL,
7564       -1ULL
7565     }
7566 #endif
7567   },
7568   { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
7569     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7570 #ifndef DISASM_ONLY
7571     {
7572       0xc00000007ffc0000ULL,
7573       0ULL,
7574       0ULL,
7575       0ULL,
7576       0ULL
7577     },
7578     {
7579       0x0000000051f40000ULL,
7580       -1ULL,
7581       -1ULL,
7582       -1ULL,
7583       -1ULL
7584     }
7585 #endif
7586   },
7587   { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
7588     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7589 #ifndef DISASM_ONLY
7590     {
7591       0xc00000007ffc0000ULL,
7592       0xfffe000000000000ULL,
7593       0ULL,
7594       0ULL,
7595       0ULL
7596     },
7597     {
7598       0x0000000051fc0000ULL,
7599       0x28a2000000000000ULL,
7600       -1ULL,
7601       -1ULL,
7602       -1ULL
7603     }
7604 #endif
7605   },
7606   { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
7607     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7608 #ifndef DISASM_ONLY
7609     {
7610       0xc00000007ffc0000ULL,
7611       0xfffe000000000000ULL,
7612       0ULL,
7613       0ULL,
7614       0ULL
7615     },
7616     {
7617       0x0000000052000000ULL,
7618       0x28a4000000000000ULL,
7619       -1ULL,
7620       -1ULL,
7621       -1ULL
7622     }
7623 #endif
7624   },
7625   { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
7626     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7627 #ifndef DISASM_ONLY
7628     {
7629       0xc00000007ffc0000ULL,
7630       0xfffe000000000000ULL,
7631       0ULL,
7632       0ULL,
7633       0ULL
7634     },
7635     {
7636       0x0000000052040000ULL,
7637       0x28a6000000000000ULL,
7638       -1ULL,
7639       -1ULL,
7640       -1ULL
7641     }
7642 #endif
7643   },
7644   { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
7645     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7646 #ifndef DISASM_ONLY
7647     {
7648       0xc00000007ff00000ULL,
7649       0xfff8000000000000ULL,
7650       0ULL,
7651       0ULL,
7652       0ULL
7653     },
7654     {
7655       0x0000000041200000ULL,
7656       0x1958000000000000ULL,
7657       -1ULL,
7658       -1ULL,
7659       -1ULL
7660     }
7661 #endif
7662   },
7663   { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
7664     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7665 #ifndef DISASM_ONLY
7666     {
7667       0xc00000007ffc0000ULL,
7668       0xfffe000000000000ULL,
7669       0ULL,
7670       0ULL,
7671       0ULL
7672     },
7673     {
7674       0x0000000052080000ULL,
7675       0x28a8000000000000ULL,
7676       -1ULL,
7677       -1ULL,
7678       -1ULL
7679     }
7680 #endif
7681   },
7682   { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
7683     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
7684 #ifndef DISASM_ONLY
7685     {
7686       0xc00000007ff00000ULL,
7687       0xfff8000000000000ULL,
7688       0ULL,
7689       0ULL,
7690       0ULL
7691     },
7692     {
7693       0x0000000041300000ULL,
7694       0x1960000000000000ULL,
7695       -1ULL,
7696       -1ULL,
7697       -1ULL
7698     }
7699 #endif
7700   },
7701   { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
7702     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7703 #ifndef DISASM_ONLY
7704     {
7705       0xc00000007ffc0000ULL,
7706       0xfffe000000000000ULL,
7707       0ULL,
7708       0ULL,
7709       0ULL
7710     },
7711     {
7712       0x00000000520c0000ULL,
7713       0x28aa000000000000ULL,
7714       -1ULL,
7715       -1ULL,
7716       -1ULL
7717     }
7718 #endif
7719   },
7720   { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
7721     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7722 #ifndef DISASM_ONLY
7723     {
7724       0xc00000007ffc0000ULL,
7725       0ULL,
7726       0ULL,
7727       0ULL,
7728       0ULL
7729     },
7730     {
7731       0x0000000052100000ULL,
7732       -1ULL,
7733       -1ULL,
7734       -1ULL,
7735       -1ULL
7736     }
7737 #endif
7738   },
7739   { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
7740     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7741 #ifndef DISASM_ONLY
7742     {
7743       0xc00000007ffc0000ULL,
7744       0ULL,
7745       0ULL,
7746       0ULL,
7747       0ULL
7748     },
7749     {
7750       0x0000000052140000ULL,
7751       -1ULL,
7752       -1ULL,
7753       -1ULL,
7754       -1ULL
7755     }
7756 #endif
7757   },
7758   { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
7759     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7760 #ifndef DISASM_ONLY
7761     {
7762       0xc00000007ffc0000ULL,
7763       0ULL,
7764       0ULL,
7765       0ULL,
7766       0ULL
7767     },
7768     {
7769       0x0000000052180000ULL,
7770       -1ULL,
7771       -1ULL,
7772       -1ULL,
7773       -1ULL
7774     }
7775 #endif
7776   },
7777   { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
7778     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7779 #ifndef DISASM_ONLY
7780     {
7781       0xc00000007ffc0000ULL,
7782       0xfffe000000000000ULL,
7783       0ULL,
7784       0ULL,
7785       0ULL
7786     },
7787     {
7788       0x00000000521c0000ULL,
7789       0x28ac000000000000ULL,
7790       -1ULL,
7791       -1ULL,
7792       -1ULL
7793     }
7794 #endif
7795   },
7796   { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
7797     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7798 #ifndef DISASM_ONLY
7799     {
7800       0xc00000007ffc0000ULL,
7801       0xfffe000000000000ULL,
7802       0ULL,
7803       0ULL,
7804       0ULL
7805     },
7806     {
7807       0x0000000052200000ULL,
7808       0x28ae000000000000ULL,
7809       -1ULL,
7810       -1ULL,
7811       -1ULL
7812     }
7813 #endif
7814   },
7815   { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
7816     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7817 #ifndef DISASM_ONLY
7818     {
7819       0xc00000007ffc0000ULL,
7820       0xfffe000000000000ULL,
7821       0ULL,
7822       0ULL,
7823       0ULL
7824     },
7825     {
7826       0x0000000052240000ULL,
7827       0x28b0000000000000ULL,
7828       -1ULL,
7829       -1ULL,
7830       -1ULL
7831     }
7832 #endif
7833   },
7834   { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
7835     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7836 #ifndef DISASM_ONLY
7837     {
7838       0xc00000007ffc0000ULL,
7839       0xfffe000000000000ULL,
7840       0ULL,
7841       0ULL,
7842       0ULL
7843     },
7844     {
7845       0x0000000052280000ULL,
7846       0x28b2000000000000ULL,
7847       -1ULL,
7848       -1ULL,
7849       -1ULL
7850     }
7851 #endif
7852   },
7853   { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
7854     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7855 #ifndef DISASM_ONLY
7856     {
7857       0xc00000007ffc0000ULL,
7858       0ULL,
7859       0ULL,
7860       0ULL,
7861       0ULL
7862     },
7863     {
7864       0x00000000522c0000ULL,
7865       -1ULL,
7866       -1ULL,
7867       -1ULL,
7868       -1ULL
7869     }
7870 #endif
7871   },
7872   { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
7873     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7874 #ifndef DISASM_ONLY
7875     {
7876       0xc00000007ffc0000ULL,
7877       0ULL,
7878       0ULL,
7879       0ULL,
7880       0ULL
7881     },
7882     {
7883       0x0000000052300000ULL,
7884       -1ULL,
7885       -1ULL,
7886       -1ULL,
7887       -1ULL
7888     }
7889 #endif
7890   },
7891   { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
7892     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7893 #ifndef DISASM_ONLY
7894     {
7895       0xc00000007ffc0000ULL,
7896       0ULL,
7897       0ULL,
7898       0ULL,
7899       0ULL
7900     },
7901     {
7902       0x0000000052340000ULL,
7903       -1ULL,
7904       -1ULL,
7905       -1ULL,
7906       -1ULL
7907     }
7908 #endif
7909   },
7910   { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
7911     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7912 #ifndef DISASM_ONLY
7913     {
7914       0xc00000007ffc0000ULL,
7915       0ULL,
7916       0ULL,
7917       0ULL,
7918       0ULL
7919     },
7920     {
7921       0x0000000052380000ULL,
7922       -1ULL,
7923       -1ULL,
7924       -1ULL,
7925       -1ULL
7926     }
7927 #endif
7928   },
7929   { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
7930     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7931 #ifndef DISASM_ONLY
7932     {
7933       0xc00000007ffc0000ULL,
7934       0xfffe000000000000ULL,
7935       0ULL,
7936       0ULL,
7937       0ULL
7938     },
7939     {
7940       0x0000000052400000ULL,
7941       0x28b6000000000000ULL,
7942       -1ULL,
7943       -1ULL,
7944       -1ULL
7945     }
7946 #endif
7947   },
7948   { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
7949     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
7950 #ifndef DISASM_ONLY
7951     {
7952       0xc00000007ffc0000ULL,
7953       0xfffe000000000000ULL,
7954       0ULL,
7955       0ULL,
7956       0ULL
7957     },
7958     {
7959       0x0000000060280000ULL,
7960       0x3014000000000000ULL,
7961       -1ULL,
7962       -1ULL,
7963       -1ULL
7964     }
7965 #endif
7966   },
7967   { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
7968     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7969 #ifndef DISASM_ONLY
7970     {
7971       0xc00000007ffc0000ULL,
7972       0xfffe000000000000ULL,
7973       0ULL,
7974       0ULL,
7975       0ULL
7976     },
7977     {
7978       0x00000000523c0000ULL,
7979       0x28b4000000000000ULL,
7980       -1ULL,
7981       -1ULL,
7982       -1ULL
7983     }
7984 #endif
7985   },
7986   { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
7987     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
7988 #ifndef DISASM_ONLY
7989     {
7990       0xc00000007ffc0000ULL,
7991       0xfffe000000000000ULL,
7992       0ULL,
7993       0ULL,
7994       0ULL
7995     },
7996     {
7997       0x0000000052440000ULL,
7998       0x28b8000000000000ULL,
7999       -1ULL,
8000       -1ULL,
8001       -1ULL
8002     }
8003 #endif
8004   },
8005   { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
8006     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
8007 #ifndef DISASM_ONLY
8008     {
8009       0xc00000007ffc0000ULL,
8010       0xfffe000000000000ULL,
8011       0ULL,
8012       0ULL,
8013       0ULL
8014     },
8015     {
8016       0x00000000602c0000ULL,
8017       0x3016000000000000ULL,
8018       -1ULL,
8019       -1ULL,
8020       -1ULL
8021     }
8022 #endif
8023   },
8024   { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
8025     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8026 #ifndef DISASM_ONLY
8027     {
8028       0xc00000007ffc0000ULL,
8029       0xfffe000000000000ULL,
8030       0ULL,
8031       0ULL,
8032       0ULL
8033     },
8034     {
8035       0x0000000052480000ULL,
8036       0x28ba000000000000ULL,
8037       -1ULL,
8038       -1ULL,
8039       -1ULL
8040     }
8041 #endif
8042   },
8043   { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
8044     { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
8045 #ifndef DISASM_ONLY
8046     {
8047       0xc00000007ffc0000ULL,
8048       0xfffe000000000000ULL,
8049       0ULL,
8050       0ULL,
8051       0ULL
8052     },
8053     {
8054       0x0000000060300000ULL,
8055       0x3018000000000000ULL,
8056       -1ULL,
8057       -1ULL,
8058       -1ULL
8059     }
8060 #endif
8061   },
8062   { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
8063     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8064 #ifndef DISASM_ONLY
8065     {
8066       0xc00000007ffc0000ULL,
8067       0xfffe000000000000ULL,
8068       0ULL,
8069       0ULL,
8070       0ULL
8071     },
8072     {
8073       0x0000000052500000ULL,
8074       0x28be000000000000ULL,
8075       -1ULL,
8076       -1ULL,
8077       -1ULL
8078     }
8079 #endif
8080   },
8081   { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
8082     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8083 #ifndef DISASM_ONLY
8084     {
8085       0xc00000007ffc0000ULL,
8086       0xfffe000000000000ULL,
8087       0ULL,
8088       0ULL,
8089       0ULL
8090     },
8091     {
8092       0x00000000524c0000ULL,
8093       0x28bc000000000000ULL,
8094       -1ULL,
8095       -1ULL,
8096       -1ULL
8097     }
8098 #endif
8099   },
8100   { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
8101     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8102 #ifndef DISASM_ONLY
8103     {
8104       0xc00000007ffc0000ULL,
8105       0xfffe000000000000ULL,
8106       0ULL,
8107       0ULL,
8108       0ULL
8109     },
8110     {
8111       0x0000000052580000ULL,
8112       0x28c2000000000000ULL,
8113       -1ULL,
8114       -1ULL,
8115       -1ULL
8116     }
8117 #endif
8118   },
8119   { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
8120     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8121 #ifndef DISASM_ONLY
8122     {
8123       0xc00000007ffc0000ULL,
8124       0xfffe000000000000ULL,
8125       0ULL,
8126       0ULL,
8127       0ULL
8128     },
8129     {
8130       0x0000000052540000ULL,
8131       0x28c0000000000000ULL,
8132       -1ULL,
8133       -1ULL,
8134       -1ULL
8135     }
8136 #endif
8137   },
8138   { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
8139     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8140 #ifndef DISASM_ONLY
8141     {
8142       0xc00000007ffc0000ULL,
8143       0xfffe000000000000ULL,
8144       0ULL,
8145       0ULL,
8146       0ULL
8147     },
8148     {
8149       0x00000000525c0000ULL,
8150       0x28c4000000000000ULL,
8151       -1ULL,
8152       -1ULL,
8153       -1ULL
8154     }
8155 #endif
8156   },
8157   { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
8158     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8159 #ifndef DISASM_ONLY
8160     {
8161       0xc00000007ffc0000ULL,
8162       0xfffe000000000000ULL,
8163       0ULL,
8164       0ULL,
8165       0ULL
8166     },
8167     {
8168       0x0000000052600000ULL,
8169       0x28c6000000000000ULL,
8170       -1ULL,
8171       -1ULL,
8172       -1ULL
8173     }
8174 #endif
8175   },
8176   { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
8177     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8178 #ifndef DISASM_ONLY
8179     {
8180       0xc00000007ffc0000ULL,
8181       0xfffe000000000000ULL,
8182       0ULL,
8183       0ULL,
8184       0ULL
8185     },
8186     {
8187       0x0000000052640000ULL,
8188       0x28c8000000000000ULL,
8189       -1ULL,
8190       -1ULL,
8191       -1ULL
8192     }
8193 #endif
8194   },
8195   { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
8196     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8197 #ifndef DISASM_ONLY
8198     {
8199       0xc00000007ffc0000ULL,
8200       0xfffe000000000000ULL,
8201       0ULL,
8202       0ULL,
8203       0ULL
8204     },
8205     {
8206       0x00000000526c0000ULL,
8207       0x28cc000000000000ULL,
8208       -1ULL,
8209       -1ULL,
8210       -1ULL
8211     }
8212 #endif
8213   },
8214   { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
8215     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8216 #ifndef DISASM_ONLY
8217     {
8218       0xc00000007ffc0000ULL,
8219       0xfffe000000000000ULL,
8220       0ULL,
8221       0ULL,
8222       0ULL
8223     },
8224     {
8225       0x0000000052680000ULL,
8226       0x28ca000000000000ULL,
8227       -1ULL,
8228       -1ULL,
8229       -1ULL
8230     }
8231 #endif
8232   },
8233   { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
8234     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8235 #ifndef DISASM_ONLY
8236     {
8237       0xc00000007ffc0000ULL,
8238       0xfffe000000000000ULL,
8239       0ULL,
8240       0ULL,
8241       0ULL
8242     },
8243     {
8244       0x0000000052700000ULL,
8245       0x28ce000000000000ULL,
8246       -1ULL,
8247       -1ULL,
8248       -1ULL
8249     }
8250 #endif
8251   },
8252   { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
8253     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8254 #ifndef DISASM_ONLY
8255     {
8256       0xc00000007ffc0000ULL,
8257       0xfffe000000000000ULL,
8258       0ULL,
8259       0ULL,
8260       0ULL
8261     },
8262     {
8263       0x0000000052740000ULL,
8264       0x28d0000000000000ULL,
8265       -1ULL,
8266       -1ULL,
8267       -1ULL
8268     }
8269 #endif
8270   },
8271   { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
8272     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8273 #ifndef DISASM_ONLY
8274     {
8275       0xc00000007ffc0000ULL,
8276       0xfffe000000000000ULL,
8277       0ULL,
8278       0ULL,
8279       0ULL
8280     },
8281     {
8282       0x00000000527c0000ULL,
8283       0x28d4000000000000ULL,
8284       -1ULL,
8285       -1ULL,
8286       -1ULL
8287     }
8288 #endif
8289   },
8290   { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
8291     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
8292 #ifndef DISASM_ONLY
8293     {
8294       0xc00000007ffc0000ULL,
8295       0xfffe000000000000ULL,
8296       0ULL,
8297       0ULL,
8298       0ULL
8299     },
8300     {
8301       0x0000000052780000ULL,
8302       0x28d2000000000000ULL,
8303       -1ULL,
8304       -1ULL,
8305       -1ULL
8306     }
8307 #endif
8308   },
8309   { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
8310     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
8311 #ifndef DISASM_ONLY
8312     {
8313       0ULL,
8314       0xfffff80000000000ULL,
8315       0ULL,
8316       0ULL,
8317       0ULL
8318     },
8319     {
8320       -1ULL,
8321       0x286b300000000000ULL,
8322       -1ULL,
8323       -1ULL,
8324       -1ULL
8325     }
8326 #endif
8327   },
8328   { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
8329     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
8330 #ifndef DISASM_ONLY
8331     {
8332       0xc00000007ffc0000ULL,
8333       0xfffe000000000000ULL,
8334       0x00000000780c0000ULL,
8335       0x3c06000000000000ULL,
8336       0ULL
8337     },
8338     {
8339       0x0000000052800000ULL,
8340       0x28d6000000000000ULL,
8341       0x00000000500c0000ULL,
8342       0x2c06000000000000ULL,
8343       -1ULL
8344     }
8345 #endif
8346   },
8347   { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
8348     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
8349 #ifndef DISASM_ONLY
8350     {
8351       0xc00000007ff00000ULL,
8352       0xfff8000000000000ULL,
8353       0ULL,
8354       0ULL,
8355       0ULL
8356     },
8357     {
8358       0x0000000041400000ULL,
8359       0x1968000000000000ULL,
8360       -1ULL,
8361       -1ULL,
8362       -1ULL
8363     }
8364 #endif
8365   },
8366   { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
8367 #ifndef DISASM_ONLY
8368     { 0, }, { 0, }
8369 #endif
8370   }
8371 };
8372 
8373 #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
8374 #define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
8375 
8376 static const unsigned short decode_X0_fsm[936] =
8377 {
8378   BITFIELD(22, 9) /* index 0 */,
8379   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8380   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8381   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8382   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8383   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8384   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8385   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8386   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8387   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8388   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8389   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8390   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8391   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8392   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8393   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8394   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8395   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8396   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8397   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8398   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8399   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8400   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8401   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8402   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8403   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8404   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8405   CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
8406   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8407   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8408   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8409   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8410   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8411   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8412   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8413   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8414   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8415   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8416   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8417   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8418   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8419   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8420   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8421   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
8422   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8423   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8424   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8425   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
8426   TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
8427   TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
8428   TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
8429   TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
8430   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8431   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8432   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8433   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8434   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8435   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8436   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8437   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
8438   CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
8439   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8440   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8441   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8442   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8443   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8444   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8445   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8446   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8447   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8448   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8449   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8450   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8451   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8452   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8453   TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
8454   CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
8455   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8456   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8457   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8458   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8459   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8460   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8461   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8462   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8463   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8464   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8465   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8466   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8467   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8468   TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8469   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8470   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8471   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8472   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8473   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8474   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8475   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8476   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8477   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8478   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8479   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8480   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8481   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8482   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8483   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8484   TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8485   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8486   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8487   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8488   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8489   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8490   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8491   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8492   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8493   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8494   CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
8495   BITFIELD(6, 2) /* index 513 */,
8496   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
8497   BITFIELD(8, 2) /* index 518 */,
8498   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
8499   BITFIELD(10, 2) /* index 523 */,
8500   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
8501   BITFIELD(20, 2) /* index 528 */,
8502   TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
8503   BITFIELD(6, 2) /* index 533 */,
8504   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
8505   BITFIELD(8, 2) /* index 538 */,
8506   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
8507   BITFIELD(10, 2) /* index 543 */,
8508   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
8509   BITFIELD(0, 2) /* index 548 */,
8510   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
8511   BITFIELD(2, 2) /* index 553 */,
8512   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
8513   BITFIELD(4, 2) /* index 558 */,
8514   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
8515   BITFIELD(6, 2) /* index 563 */,
8516   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
8517   BITFIELD(8, 2) /* index 568 */,
8518   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
8519   BITFIELD(10, 2) /* index 573 */,
8520   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
8521   BITFIELD(20, 2) /* index 578 */,
8522   TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
8523   BITFIELD(20, 2) /* index 583 */,
8524   TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
8525   TILEGX_OPC_V1CMPLTUI,
8526   BITFIELD(20, 2) /* index 588 */,
8527   TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
8528   TILEGX_OPC_V2CMPEQI,
8529   BITFIELD(20, 2) /* index 593 */,
8530   TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
8531   TILEGX_OPC_V2MINSI,
8532   BITFIELD(20, 2) /* index 598 */,
8533   TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8534   BITFIELD(18, 4) /* index 603 */,
8535   TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
8536   TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
8537   TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
8538   TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
8539   BITFIELD(18, 4) /* index 620 */,
8540   TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
8541   TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
8542   TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
8543   TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
8544   TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
8545   TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
8546   BITFIELD(18, 4) /* index 637 */,
8547   TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
8548   TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
8549   TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
8550   TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
8551   TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
8552   TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
8553   BITFIELD(18, 4) /* index 654 */,
8554   TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
8555   TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
8556   TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
8557   TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
8558   TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
8559   TILEGX_OPC_MZ,
8560   BITFIELD(18, 4) /* index 671 */,
8561   TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
8562   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
8563   TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
8564   TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
8565   TILEGX_OPC_SUBXSC,
8566   BITFIELD(12, 2) /* index 688 */,
8567   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
8568   BITFIELD(14, 2) /* index 693 */,
8569   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
8570   BITFIELD(16, 2) /* index 698 */,
8571   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
8572   BITFIELD(18, 4) /* index 703 */,
8573   TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
8574   TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
8575   TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
8576   TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
8577   TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
8578   BITFIELD(12, 4) /* index 720 */,
8579   TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
8580   CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
8581   CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8582   BITFIELD(16, 2) /* index 737 */,
8583   TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8584   BITFIELD(16, 2) /* index 742 */,
8585   TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8586   BITFIELD(16, 2) /* index 747 */,
8587   TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8588   BITFIELD(16, 2) /* index 752 */,
8589   TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8590   BITFIELD(16, 2) /* index 757 */,
8591   TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8592   BITFIELD(16, 2) /* index 762 */,
8593   TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8594   BITFIELD(16, 2) /* index 767 */,
8595   TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8596   BITFIELD(16, 2) /* index 772 */,
8597   TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8598   BITFIELD(16, 2) /* index 777 */,
8599   TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8600   BITFIELD(16, 2) /* index 782 */,
8601   TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8602   BITFIELD(16, 2) /* index 787 */,
8603   TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8604   BITFIELD(16, 2) /* index 792 */,
8605   TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8606   BITFIELD(18, 4) /* index 797 */,
8607   TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
8608   TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
8609   TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
8610   TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
8611   TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
8612   BITFIELD(18, 4) /* index 814 */,
8613   TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
8614   TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
8615   TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
8616   TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
8617   TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
8618   BITFIELD(18, 4) /* index 831 */,
8619   TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
8620   TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
8621   TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
8622   TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
8623   TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
8624   BITFIELD(18, 4) /* index 848 */,
8625   TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
8626   TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
8627   TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
8628   TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
8629   TILEGX_OPC_V4SUB,
8630   BITFIELD(18, 3) /* index 865 */,
8631   CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
8632   TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8633   BITFIELD(21, 1) /* index 874 */,
8634   TILEGX_OPC_XOR, TILEGX_OPC_NONE,
8635   BITFIELD(21, 1) /* index 877 */,
8636   TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
8637   BITFIELD(21, 1) /* index 880 */,
8638   TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
8639   BITFIELD(21, 1) /* index 883 */,
8640   TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
8641   BITFIELD(21, 1) /* index 886 */,
8642   TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
8643   BITFIELD(18, 4) /* index 889 */,
8644   TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
8645   TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
8646   TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
8647   TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8648   TILEGX_OPC_NONE,
8649   BITFIELD(0, 2) /* index 906 */,
8650   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8651   CHILD(911),
8652   BITFIELD(2, 2) /* index 911 */,
8653   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8654   CHILD(916),
8655   BITFIELD(4, 2) /* index 916 */,
8656   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8657   CHILD(921),
8658   BITFIELD(6, 2) /* index 921 */,
8659   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8660   CHILD(926),
8661   BITFIELD(8, 2) /* index 926 */,
8662   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8663   CHILD(931),
8664   BITFIELD(10, 2) /* index 931 */,
8665   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
8666   TILEGX_OPC_INFOL,
8667 };
8668 
8669 static const unsigned short decode_X1_fsm[1266] =
8670 {
8671   BITFIELD(53, 9) /* index 0 */,
8672   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8673   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8674   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8675   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8676   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8677   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8678   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8679   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8680   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8681   CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
8682   CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
8683   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8684   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8685   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8686   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8687   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8688   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8689   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8690   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8691   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8692   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8693   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8694   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8695   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8696   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8697   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
8698   TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
8699   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8700   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8701   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8702   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8703   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8704   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8705   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8706   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
8707   TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
8708   TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
8709   TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
8710   TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
8711   TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
8712   TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
8713   TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
8714   TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
8715   CHILD(598), CHILD(703), CHILD(723), CHILD(728), CHILD(753), CHILD(758),
8716   CHILD(763), CHILD(768), CHILD(773), CHILD(778), TILEGX_OPC_NONE,
8717   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8718   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8719   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8720   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8721   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8722   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8723   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8724   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8725   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8726   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8727   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8728   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8729   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
8730   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8731   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8732   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8733   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8734   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8735   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8736   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
8737   TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
8738   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8739   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8740   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8741   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8742   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8743   TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
8744   CHILD(783), CHILD(800), CHILD(832), CHILD(849), CHILD(1168), CHILD(1185),
8745   CHILD(1202), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8746   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8747   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8748   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8749   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8750   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8751   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8752   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8753   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8754   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8755   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8756   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8757   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8758   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8759   TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1219), TILEGX_OPC_NONE,
8760   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8761   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8762   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8763   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8764   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8765   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8766   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8767   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8768   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8769   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8770   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8771   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8772   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8773   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8774   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8775   TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1236), CHILD(1236), CHILD(1236),
8776   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8777   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8778   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8779   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8780   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8781   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8782   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8783   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8784   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8785   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8786   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8787   CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
8788   CHILD(1236),
8789   BITFIELD(37, 2) /* index 513 */,
8790   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
8791   BITFIELD(39, 2) /* index 518 */,
8792   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
8793   BITFIELD(41, 2) /* index 523 */,
8794   TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
8795   BITFIELD(51, 2) /* index 528 */,
8796   TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
8797   BITFIELD(37, 2) /* index 533 */,
8798   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
8799   BITFIELD(39, 2) /* index 538 */,
8800   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
8801   BITFIELD(41, 2) /* index 543 */,
8802   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
8803   BITFIELD(31, 2) /* index 548 */,
8804   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
8805   BITFIELD(33, 2) /* index 553 */,
8806   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
8807   BITFIELD(35, 2) /* index 558 */,
8808   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
8809   BITFIELD(37, 2) /* index 563 */,
8810   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
8811   BITFIELD(39, 2) /* index 568 */,
8812   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
8813   BITFIELD(41, 2) /* index 573 */,
8814   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
8815   BITFIELD(51, 2) /* index 578 */,
8816   TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
8817   BITFIELD(31, 2) /* index 583 */,
8818   TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
8819   BITFIELD(33, 2) /* index 588 */,
8820   TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
8821   BITFIELD(35, 2) /* index 593 */,
8822   TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
8823   TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
8824   BITFIELD(51, 2) /* index 598 */,
8825   CHILD(603), CHILD(618), CHILD(633), CHILD(648),
8826   BITFIELD(31, 2) /* index 603 */,
8827   TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
8828   BITFIELD(33, 2) /* index 608 */,
8829   TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
8830   BITFIELD(35, 2) /* index 613 */,
8831   TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
8832   TILEGX_OPC_PREFETCH_ADD_L1,
8833   BITFIELD(31, 2) /* index 618 */,
8834   TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
8835   BITFIELD(33, 2) /* index 623 */,
8836   TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
8837   BITFIELD(35, 2) /* index 628 */,
8838   TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
8839   TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
8840   BITFIELD(31, 2) /* index 633 */,
8841   TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
8842   BITFIELD(33, 2) /* index 638 */,
8843   TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
8844   BITFIELD(35, 2) /* index 643 */,
8845   TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
8846   TILEGX_OPC_PREFETCH_ADD_L2,
8847   BITFIELD(31, 2) /* index 648 */,
8848   CHILD(653), CHILD(653), CHILD(653), CHILD(673),
8849   BITFIELD(43, 2) /* index 653 */,
8850   CHILD(658), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
8851   BITFIELD(45, 2) /* index 658 */,
8852   CHILD(663), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
8853   BITFIELD(47, 2) /* index 663 */,
8854   CHILD(668), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
8855   BITFIELD(49, 2) /* index 668 */,
8856   TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
8857   TILEGX_OPC_LD4S_ADD,
8858   BITFIELD(33, 2) /* index 673 */,
8859   CHILD(653), CHILD(653), CHILD(653), CHILD(678),
8860   BITFIELD(35, 2) /* index 678 */,
8861   CHILD(653), CHILD(653), CHILD(653), CHILD(683),
8862   BITFIELD(43, 2) /* index 683 */,
8863   CHILD(688), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8864   TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8865   BITFIELD(45, 2) /* index 688 */,
8866   CHILD(693), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8867   TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8868   BITFIELD(47, 2) /* index 693 */,
8869   CHILD(698), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8870   TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8871   BITFIELD(49, 2) /* index 698 */,
8872   TILEGX_OPC_LD4S_TLS, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8873   TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
8874   BITFIELD(51, 2) /* index 703 */,
8875   CHILD(708), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
8876   TILEGX_OPC_LDNT2S_ADD,
8877   BITFIELD(31, 2) /* index 708 */,
8878   TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(713),
8879   BITFIELD(33, 2) /* index 713 */,
8880   TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(718),
8881   BITFIELD(35, 2) /* index 718 */,
8882   TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
8883   TILEGX_OPC_PREFETCH_ADD_L3,
8884   BITFIELD(51, 2) /* index 723 */,
8885   TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
8886   TILEGX_OPC_LDNT_ADD,
8887   BITFIELD(51, 2) /* index 728 */,
8888   CHILD(733), TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
8889   BITFIELD(43, 2) /* index 733 */,
8890   CHILD(738), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
8891   BITFIELD(45, 2) /* index 738 */,
8892   CHILD(743), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
8893   BITFIELD(47, 2) /* index 743 */,
8894   CHILD(748), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
8895   BITFIELD(49, 2) /* index 748 */,
8896   TILEGX_OPC_LD_TLS, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
8897   BITFIELD(51, 2) /* index 753 */,
8898   TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
8899   BITFIELD(51, 2) /* index 758 */,
8900   TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
8901   TILEGX_OPC_STNT_ADD,
8902   BITFIELD(51, 2) /* index 763 */,
8903   TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
8904   TILEGX_OPC_V1CMPLTSI,
8905   BITFIELD(51, 2) /* index 768 */,
8906   TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
8907   TILEGX_OPC_V2ADDI,
8908   BITFIELD(51, 2) /* index 773 */,
8909   TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
8910   TILEGX_OPC_V2MAXSI,
8911   BITFIELD(51, 2) /* index 778 */,
8912   TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8913   BITFIELD(49, 4) /* index 783 */,
8914   TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
8915   TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
8916   TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
8917   TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
8918   TILEGX_OPC_DBLALIGN6,
8919   BITFIELD(49, 4) /* index 800 */,
8920   TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
8921   TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
8922   TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
8923   TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
8924   CHILD(817), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
8925   BITFIELD(43, 2) /* index 817 */,
8926   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(822),
8927   BITFIELD(45, 2) /* index 822 */,
8928   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(827),
8929   BITFIELD(47, 2) /* index 827 */,
8930   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
8931   BITFIELD(49, 4) /* index 832 */,
8932   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
8933   TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
8934   TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
8935   TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
8936   TILEGX_OPC_STNT4,
8937   BITFIELD(46, 7) /* index 849 */,
8938   TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
8939   TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
8940   TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
8941   TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
8942   TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
8943   TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
8944   TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
8945   TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
8946   TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
8947   TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(978), CHILD(987),
8948   CHILD(1066), CHILD(1150), CHILD(1159), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
8949   TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
8950   TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
8951   TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
8952   TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
8953   TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
8954   TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
8955   TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
8956   TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
8957   TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
8958   TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
8959   TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
8960   TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
8961   TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
8962   TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
8963   TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
8964   TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
8965   TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
8966   TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
8967   TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
8968   TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
8969   TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
8970   TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
8971   TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
8972   TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
8973   TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
8974   TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
8975   BITFIELD(43, 3) /* index 978 */,
8976   TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
8977   TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
8978   BITFIELD(43, 3) /* index 987 */,
8979   CHILD(996), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
8980   TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(1051),
8981   BITFIELD(31, 2) /* index 996 */,
8982   CHILD(1001), CHILD(1026), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8983   BITFIELD(33, 2) /* index 1001 */,
8984   TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1006),
8985   BITFIELD(35, 2) /* index 1006 */,
8986   TILEGX_OPC_ILL, CHILD(1011), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8987   BITFIELD(37, 2) /* index 1011 */,
8988   TILEGX_OPC_ILL, CHILD(1016), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8989   BITFIELD(39, 2) /* index 1016 */,
8990   TILEGX_OPC_ILL, CHILD(1021), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8991   BITFIELD(41, 2) /* index 1021 */,
8992   TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
8993   BITFIELD(33, 2) /* index 1026 */,
8994   TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1031),
8995   BITFIELD(35, 2) /* index 1031 */,
8996   TILEGX_OPC_ILL, CHILD(1036), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8997   BITFIELD(37, 2) /* index 1036 */,
8998   TILEGX_OPC_ILL, CHILD(1041), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
8999   BITFIELD(39, 2) /* index 1041 */,
9000   TILEGX_OPC_ILL, CHILD(1046), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
9001   BITFIELD(41, 2) /* index 1046 */,
9002   TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
9003   BITFIELD(31, 2) /* index 1051 */,
9004   TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1056),
9005   BITFIELD(33, 2) /* index 1056 */,
9006   TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1061),
9007   BITFIELD(35, 2) /* index 1061 */,
9008   TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
9009   TILEGX_OPC_PREFETCH_L1_FAULT,
9010   BITFIELD(43, 3) /* index 1066 */,
9011   CHILD(1075), CHILD(1090), CHILD(1105), CHILD(1120), CHILD(1135),
9012   TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
9013   BITFIELD(31, 2) /* index 1075 */,
9014   TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1080),
9015   BITFIELD(33, 2) /* index 1080 */,
9016   TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1085),
9017   BITFIELD(35, 2) /* index 1085 */,
9018   TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
9019   BITFIELD(31, 2) /* index 1090 */,
9020   TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1095),
9021   BITFIELD(33, 2) /* index 1095 */,
9022   TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1100),
9023   BITFIELD(35, 2) /* index 1100 */,
9024   TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
9025   TILEGX_OPC_PREFETCH_L2_FAULT,
9026   BITFIELD(31, 2) /* index 1105 */,
9027   TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1110),
9028   BITFIELD(33, 2) /* index 1110 */,
9029   TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1115),
9030   BITFIELD(35, 2) /* index 1115 */,
9031   TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
9032   BITFIELD(31, 2) /* index 1120 */,
9033   TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1125),
9034   BITFIELD(33, 2) /* index 1125 */,
9035   TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1130),
9036   BITFIELD(35, 2) /* index 1130 */,
9037   TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
9038   TILEGX_OPC_PREFETCH_L3_FAULT,
9039   BITFIELD(31, 2) /* index 1135 */,
9040   TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1140),
9041   BITFIELD(33, 2) /* index 1140 */,
9042   TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1145),
9043   BITFIELD(35, 2) /* index 1145 */,
9044   TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
9045   BITFIELD(43, 3) /* index 1150 */,
9046   TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
9047   TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
9048   BITFIELD(43, 3) /* index 1159 */,
9049   TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
9050   TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
9051   BITFIELD(49, 4) /* index 1168 */,
9052   TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
9053   TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
9054   TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
9055   TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
9056   TILEGX_OPC_V2CMPLTU,
9057   BITFIELD(49, 4) /* index 1185 */,
9058   TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
9059   TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
9060   TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
9061   TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
9062   TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
9063   BITFIELD(49, 4) /* index 1202 */,
9064   TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
9065   TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
9066   TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
9067   TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9068   TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9069   BITFIELD(49, 4) /* index 1219 */,
9070   TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
9071   TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
9072   TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
9073   TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9074   TILEGX_OPC_NONE,
9075   BITFIELD(31, 2) /* index 1236 */,
9076   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9077   CHILD(1241),
9078   BITFIELD(33, 2) /* index 1241 */,
9079   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9080   CHILD(1246),
9081   BITFIELD(35, 2) /* index 1246 */,
9082   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9083   CHILD(1251),
9084   BITFIELD(37, 2) /* index 1251 */,
9085   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9086   CHILD(1256),
9087   BITFIELD(39, 2) /* index 1256 */,
9088   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9089   CHILD(1261),
9090   BITFIELD(41, 2) /* index 1261 */,
9091   TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
9092   TILEGX_OPC_INFOL,
9093 };
9094 
9095 static const unsigned short decode_Y0_fsm[178] =
9096 {
9097   BITFIELD(27, 4) /* index 0 */,
9098   CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
9099   TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
9100   CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
9101   CHILD(173),
9102   BITFIELD(6, 2) /* index 17 */,
9103   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
9104   BITFIELD(8, 2) /* index 22 */,
9105   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
9106   BITFIELD(10, 2) /* index 27 */,
9107   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
9108   BITFIELD(0, 2) /* index 32 */,
9109   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
9110   BITFIELD(2, 2) /* index 37 */,
9111   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
9112   BITFIELD(4, 2) /* index 42 */,
9113   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
9114   BITFIELD(6, 2) /* index 47 */,
9115   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
9116   BITFIELD(8, 2) /* index 52 */,
9117   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
9118   BITFIELD(10, 2) /* index 57 */,
9119   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
9120   BITFIELD(18, 2) /* index 62 */,
9121   TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
9122   BITFIELD(15, 5) /* index 67 */,
9123   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
9124   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
9125   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
9126   TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
9127   TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
9128   TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
9129   TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
9130   TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
9131   CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9132   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9133   BITFIELD(12, 3) /* index 100 */,
9134   TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
9135   TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
9136   TILEGX_OPC_REVBITS,
9137   BITFIELD(12, 3) /* index 109 */,
9138   TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
9139   TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9140   TILEGX_OPC_NONE,
9141   BITFIELD(18, 2) /* index 118 */,
9142   TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
9143   BITFIELD(18, 2) /* index 123 */,
9144   TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
9145   BITFIELD(18, 2) /* index 128 */,
9146   TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
9147   BITFIELD(18, 2) /* index 133 */,
9148   TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
9149   BITFIELD(12, 2) /* index 138 */,
9150   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
9151   BITFIELD(14, 2) /* index 143 */,
9152   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
9153   BITFIELD(16, 2) /* index 148 */,
9154   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
9155   BITFIELD(18, 2) /* index 153 */,
9156   TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
9157   BITFIELD(18, 2) /* index 158 */,
9158   TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
9159   TILEGX_OPC_SHL3ADDX,
9160   BITFIELD(18, 2) /* index 163 */,
9161   TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
9162   TILEGX_OPC_MUL_LU_LU,
9163   BITFIELD(18, 2) /* index 168 */,
9164   TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
9165   TILEGX_OPC_MULA_LU_LU,
9166   BITFIELD(18, 2) /* index 173 */,
9167   TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
9168 };
9169 
9170 static const unsigned short decode_Y1_fsm[167] =
9171 {
9172   BITFIELD(58, 4) /* index 0 */,
9173   TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
9174   TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
9175   CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
9176   BITFIELD(37, 2) /* index 17 */,
9177   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
9178   BITFIELD(39, 2) /* index 22 */,
9179   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
9180   BITFIELD(41, 2) /* index 27 */,
9181   TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
9182   BITFIELD(31, 2) /* index 32 */,
9183   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
9184   BITFIELD(33, 2) /* index 37 */,
9185   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
9186   BITFIELD(35, 2) /* index 42 */,
9187   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
9188   BITFIELD(37, 2) /* index 47 */,
9189   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
9190   BITFIELD(39, 2) /* index 52 */,
9191   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
9192   BITFIELD(41, 2) /* index 57 */,
9193   TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
9194   BITFIELD(49, 2) /* index 62 */,
9195   TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
9196   BITFIELD(47, 4) /* index 67 */,
9197   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
9198   TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
9199   TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
9200   TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
9201   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
9202   BITFIELD(43, 3) /* index 84 */,
9203   CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
9204   CHILD(111), CHILD(114),
9205   BITFIELD(46, 1) /* index 93 */,
9206   TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
9207   BITFIELD(46, 1) /* index 96 */,
9208   TILEGX_OPC_NONE, TILEGX_OPC_ILL,
9209   BITFIELD(46, 1) /* index 99 */,
9210   TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
9211   BITFIELD(46, 1) /* index 102 */,
9212   TILEGX_OPC_NONE, TILEGX_OPC_JALR,
9213   BITFIELD(46, 1) /* index 105 */,
9214   TILEGX_OPC_NONE, TILEGX_OPC_JRP,
9215   BITFIELD(46, 1) /* index 108 */,
9216   TILEGX_OPC_NONE, TILEGX_OPC_JR,
9217   BITFIELD(46, 1) /* index 111 */,
9218   TILEGX_OPC_NONE, TILEGX_OPC_LNK,
9219   BITFIELD(46, 1) /* index 114 */,
9220   TILEGX_OPC_NONE, TILEGX_OPC_NOP,
9221   BITFIELD(49, 2) /* index 117 */,
9222   TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
9223   BITFIELD(49, 2) /* index 122 */,
9224   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
9225   BITFIELD(49, 2) /* index 127 */,
9226   TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
9227   BITFIELD(49, 2) /* index 132 */,
9228   TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
9229   BITFIELD(43, 2) /* index 137 */,
9230   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
9231   BITFIELD(45, 2) /* index 142 */,
9232   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
9233   BITFIELD(47, 2) /* index 147 */,
9234   TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
9235   BITFIELD(49, 2) /* index 152 */,
9236   TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
9237   BITFIELD(49, 2) /* index 157 */,
9238   TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
9239   TILEGX_OPC_SHL3ADDX,
9240   BITFIELD(49, 2) /* index 162 */,
9241   TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
9242 };
9243 
9244 static const unsigned short decode_Y2_fsm[118] =
9245 {
9246   BITFIELD(62, 2) /* index 0 */,
9247   TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
9248   BITFIELD(55, 3) /* index 5 */,
9249   CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
9250   CHILD(43),
9251   BITFIELD(26, 1) /* index 14 */,
9252   TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
9253   BITFIELD(26, 1) /* index 17 */,
9254   CHILD(20), CHILD(30),
9255   BITFIELD(51, 2) /* index 20 */,
9256   TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
9257   BITFIELD(53, 2) /* index 25 */,
9258   TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
9259   TILEGX_OPC_PREFETCH_L1_FAULT,
9260   BITFIELD(51, 2) /* index 30 */,
9261   TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
9262   BITFIELD(53, 2) /* index 35 */,
9263   TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
9264   BITFIELD(26, 1) /* index 40 */,
9265   TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
9266   BITFIELD(26, 1) /* index 43 */,
9267   CHILD(46), CHILD(56),
9268   BITFIELD(51, 2) /* index 46 */,
9269   TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
9270   BITFIELD(53, 2) /* index 51 */,
9271   TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
9272   TILEGX_OPC_PREFETCH_L2_FAULT,
9273   BITFIELD(51, 2) /* index 56 */,
9274   TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
9275   BITFIELD(53, 2) /* index 61 */,
9276   TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
9277   BITFIELD(56, 2) /* index 66 */,
9278   CHILD(71), CHILD(74), CHILD(90), CHILD(93),
9279   BITFIELD(26, 1) /* index 71 */,
9280   TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
9281   BITFIELD(26, 1) /* index 74 */,
9282   TILEGX_OPC_NONE, CHILD(77),
9283   BITFIELD(51, 2) /* index 77 */,
9284   TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
9285   BITFIELD(53, 2) /* index 82 */,
9286   TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
9287   BITFIELD(55, 1) /* index 87 */,
9288   TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
9289   BITFIELD(26, 1) /* index 90 */,
9290   TILEGX_OPC_LD4U, TILEGX_OPC_LD,
9291   BITFIELD(26, 1) /* index 93 */,
9292   CHILD(96), TILEGX_OPC_LD,
9293   BITFIELD(51, 2) /* index 96 */,
9294   TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
9295   BITFIELD(53, 2) /* index 101 */,
9296   TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
9297   BITFIELD(55, 1) /* index 106 */,
9298   TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
9299   BITFIELD(26, 1) /* index 109 */,
9300   CHILD(112), CHILD(115),
9301   BITFIELD(57, 1) /* index 112 */,
9302   TILEGX_OPC_ST1, TILEGX_OPC_ST4,
9303   BITFIELD(57, 1) /* index 115 */,
9304   TILEGX_OPC_ST2, TILEGX_OPC_ST,
9305 };
9306 
9307 #undef BITFIELD
9308 #undef CHILD
9309 
9310 const unsigned short * const
9311 tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
9312 {
9313   decode_X0_fsm,
9314   decode_X1_fsm,
9315   decode_Y0_fsm,
9316   decode_Y1_fsm,
9317   decode_Y2_fsm
9318 };
9319 
9320 const struct tilegx_operand tilegx_operands[35] =
9321 {
9322   {
9323     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
9324     8, 1, 0, 0, 0, 0,
9325     create_Imm8_X0, get_Imm8_X0
9326   },
9327   {
9328     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
9329     8, 1, 0, 0, 0, 0,
9330     create_Imm8_X1, get_Imm8_X1
9331   },
9332   {
9333     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
9334     8, 1, 0, 0, 0, 0,
9335     create_Imm8_Y0, get_Imm8_Y0
9336   },
9337   {
9338     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
9339     8, 1, 0, 0, 0, 0,
9340     create_Imm8_Y1, get_Imm8_Y1
9341   },
9342   {
9343     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
9344     16, 1, 0, 0, 0, 0,
9345     create_Imm16_X0, get_Imm16_X0
9346   },
9347   {
9348     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
9349     16, 1, 0, 0, 0, 0,
9350     create_Imm16_X1, get_Imm16_X1
9351   },
9352   {
9353     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9354     6, 0, 0, 1, 0, 0,
9355     create_Dest_X1, get_Dest_X1
9356   },
9357   {
9358     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9359     6, 0, 1, 0, 0, 0,
9360     create_SrcA_X1, get_SrcA_X1
9361   },
9362   {
9363     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9364     6, 0, 0, 1, 0, 0,
9365     create_Dest_X0, get_Dest_X0
9366   },
9367   {
9368     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9369     6, 0, 1, 0, 0, 0,
9370     create_SrcA_X0, get_SrcA_X0
9371   },
9372   {
9373     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9374     6, 0, 0, 1, 0, 0,
9375     create_Dest_Y0, get_Dest_Y0
9376   },
9377   {
9378     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9379     6, 0, 1, 0, 0, 0,
9380     create_SrcA_Y0, get_SrcA_Y0
9381   },
9382   {
9383     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9384     6, 0, 0, 1, 0, 0,
9385     create_Dest_Y1, get_Dest_Y1
9386   },
9387   {
9388     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9389     6, 0, 1, 0, 0, 0,
9390     create_SrcA_Y1, get_SrcA_Y1
9391   },
9392   {
9393     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9394     6, 0, 1, 0, 0, 0,
9395     create_SrcA_Y2, get_SrcA_Y2
9396   },
9397   {
9398     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9399     6, 0, 1, 1, 0, 0,
9400     create_SrcA_X1, get_SrcA_X1
9401   },
9402   {
9403     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9404     6, 0, 1, 0, 0, 0,
9405     create_SrcB_X0, get_SrcB_X0
9406   },
9407   {
9408     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9409     6, 0, 1, 0, 0, 0,
9410     create_SrcB_X1, get_SrcB_X1
9411   },
9412   {
9413     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9414     6, 0, 1, 0, 0, 0,
9415     create_SrcB_Y0, get_SrcB_Y0
9416   },
9417   {
9418     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9419     6, 0, 1, 0, 0, 0,
9420     create_SrcB_Y1, get_SrcB_Y1
9421   },
9422   {
9423     TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
9424     17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
9425     create_BrOff_X1, get_BrOff_X1
9426   },
9427   {
9428     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0),
9429     6, 0, 0, 0, 0, 0,
9430     create_BFStart_X0, get_BFStart_X0
9431   },
9432   {
9433     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0),
9434     6, 0, 0, 0, 0, 0,
9435     create_BFEnd_X0, get_BFEnd_X0
9436   },
9437   {
9438     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9439     6, 0, 1, 1, 0, 0,
9440     create_Dest_X0, get_Dest_X0
9441   },
9442   {
9443     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9444     6, 0, 1, 1, 0, 0,
9445     create_Dest_Y0, get_Dest_Y0
9446   },
9447   {
9448     TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
9449     27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
9450     create_JumpOff_X1, get_JumpOff_X1
9451   },
9452   {
9453     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9454     6, 0, 0, 1, 0, 0,
9455     create_SrcBDest_Y2, get_SrcBDest_Y2
9456   },
9457   {
9458     TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
9459     14, 0, 0, 0, 0, 0,
9460     create_MF_Imm14_X1, get_MF_Imm14_X1
9461   },
9462   {
9463     TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
9464     14, 0, 0, 0, 0, 0,
9465     create_MT_Imm14_X1, get_MT_Imm14_X1
9466   },
9467   {
9468     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
9469     6, 0, 0, 0, 0, 0,
9470     create_ShAmt_X0, get_ShAmt_X0
9471   },
9472   {
9473     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
9474     6, 0, 0, 0, 0, 0,
9475     create_ShAmt_X1, get_ShAmt_X1
9476   },
9477   {
9478     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
9479     6, 0, 0, 0, 0, 0,
9480     create_ShAmt_Y0, get_ShAmt_Y0
9481   },
9482   {
9483     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
9484     6, 0, 0, 0, 0, 0,
9485     create_ShAmt_Y1, get_ShAmt_Y1
9486   },
9487   {
9488     TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
9489     6, 0, 1, 0, 0, 0,
9490     create_SrcBDest_Y2, get_SrcBDest_Y2
9491   },
9492   {
9493     TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
9494     8, 1, 0, 0, 0, 0,
9495     create_Dest_Imm8_X1, get_Dest_Imm8_X1
9496   }
9497 };
9498 
9499 /* Given a set of bundle bits and a specific pipe, returns which
9500  * instruction the bundle contains in that pipe.
9501  */
9502 const struct tilegx_opcode *
find_opcode(tilegx_bundle_bits bits,tilegx_pipeline pipe)9503 find_opcode(tilegx_bundle_bits bits, tilegx_pipeline pipe)
9504 {
9505   const unsigned short *table = tilegx_bundle_decoder_fsms[pipe];
9506   int index = 0;
9507 
9508   while (1)
9509   {
9510     unsigned short bitspec = table[index];
9511     unsigned int bitfield =
9512       ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
9513 
9514     unsigned short next = table[index + 1 + bitfield];
9515     if (next <= TILEGX_OPC_NONE)
9516       return &tilegx_opcodes[next];
9517 
9518     index = next - TILEGX_OPC_NONE;
9519   }
9520 }
9521 
9522 int
parse_insn_tilegx(tilegx_bundle_bits bits,unsigned long long pc,struct tilegx_decoded_instruction decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])9523 parse_insn_tilegx(tilegx_bundle_bits bits,
9524                   unsigned long long pc,
9525                   struct tilegx_decoded_instruction
9526                   decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
9527 {
9528   int num_instructions = 0;
9529   int pipe;
9530 
9531   int min_pipe, max_pipe;
9532   if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
9533   {
9534     min_pipe = TILEGX_PIPELINE_X0;
9535     max_pipe = TILEGX_PIPELINE_X1;
9536   }
9537   else
9538   {
9539     min_pipe = TILEGX_PIPELINE_Y0;
9540     max_pipe = TILEGX_PIPELINE_Y2;
9541   }
9542 
9543   /* For each pipe, find an instruction that fits. */
9544   for (pipe = min_pipe; pipe <= max_pipe; pipe++)
9545   {
9546     const struct tilegx_opcode *opc;
9547     struct tilegx_decoded_instruction *d;
9548     int i;
9549 
9550     d = &decoded[num_instructions++];
9551     opc = find_opcode (bits, (tilegx_pipeline)pipe);
9552     d->opcode = opc;
9553 
9554     /* Decode each operand, sign extending, etc. as appropriate. */
9555     for (i = 0; i < opc->num_operands; i++)
9556     {
9557       const struct tilegx_operand *op =
9558         &tilegx_operands[opc->operands[pipe][i]];
9559       int raw_opval = op->extract (bits);
9560       long long opval;
9561 
9562       if (op->is_signed)
9563       {
9564         /* Sign-extend the operand. */
9565         int shift = (int)((sizeof(int) * 8) - op->num_bits);
9566         raw_opval = (raw_opval << shift) >> shift;
9567       }
9568 
9569       /* Adjust PC-relative scaled branch offsets. */
9570       if (op->type == TILEGX_OP_TYPE_ADDRESS)
9571         opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
9572       else
9573         opval = raw_opval;
9574 
9575       /* Record the final value. */
9576       d->operands[i] = op;
9577       d->operand_values[i] = opval;
9578     }
9579   }
9580 
9581   return num_instructions;
9582 }
9583 
9584 struct tilegx_spr
9585 {
9586   /* The number */
9587   int number;
9588 
9589   /* The name */
9590   const char *name;
9591 };
9592 
9593 static int
tilegx_spr_compare(const void * a_ptr,const void * b_ptr)9594 tilegx_spr_compare (const void *a_ptr, const void *b_ptr)
9595 {
9596   const struct tilegx_spr *a = (const struct tilegx_spr *) a_ptr;
9597   const struct tilegx_spr *b = (const struct tilegx_spr *) b_ptr;
9598   return (a->number - b->number);
9599 }
9600 
9601 const struct tilegx_spr tilegx_sprs[] = {
9602   { 0, "MPL_MEM_ERROR_SET_0" },
9603   { 1, "MPL_MEM_ERROR_SET_1" },
9604   { 2, "MPL_MEM_ERROR_SET_2" },
9605   { 3, "MPL_MEM_ERROR_SET_3" },
9606   { 4, "MPL_MEM_ERROR" },
9607   { 5, "MEM_ERROR_CBOX_ADDR" },
9608   { 6, "MEM_ERROR_CBOX_STATUS" },
9609   { 7, "MEM_ERROR_ENABLE" },
9610   { 8, "MEM_ERROR_MBOX_ADDR" },
9611   { 9, "MEM_ERROR_MBOX_STATUS" },
9612   { 10, "SBOX_ERROR" },
9613   { 11, "XDN_DEMUX_ERROR" },
9614   { 256, "MPL_SINGLE_STEP_3_SET_0" },
9615   { 257, "MPL_SINGLE_STEP_3_SET_1" },
9616   { 258, "MPL_SINGLE_STEP_3_SET_2" },
9617   { 259, "MPL_SINGLE_STEP_3_SET_3" },
9618   { 260, "MPL_SINGLE_STEP_3" },
9619   { 261, "SINGLE_STEP_CONTROL_3" },
9620   { 512, "MPL_SINGLE_STEP_2_SET_0" },
9621   { 513, "MPL_SINGLE_STEP_2_SET_1" },
9622   { 514, "MPL_SINGLE_STEP_2_SET_2" },
9623   { 515, "MPL_SINGLE_STEP_2_SET_3" },
9624   { 516, "MPL_SINGLE_STEP_2" },
9625   { 517, "SINGLE_STEP_CONTROL_2" },
9626   { 768, "MPL_SINGLE_STEP_1_SET_0" },
9627   { 769, "MPL_SINGLE_STEP_1_SET_1" },
9628   { 770, "MPL_SINGLE_STEP_1_SET_2" },
9629   { 771, "MPL_SINGLE_STEP_1_SET_3" },
9630   { 772, "MPL_SINGLE_STEP_1" },
9631   { 773, "SINGLE_STEP_CONTROL_1" },
9632   { 1024, "MPL_SINGLE_STEP_0_SET_0" },
9633   { 1025, "MPL_SINGLE_STEP_0_SET_1" },
9634   { 1026, "MPL_SINGLE_STEP_0_SET_2" },
9635   { 1027, "MPL_SINGLE_STEP_0_SET_3" },
9636   { 1028, "MPL_SINGLE_STEP_0" },
9637   { 1029, "SINGLE_STEP_CONTROL_0" },
9638   { 1280, "MPL_IDN_COMPLETE_SET_0" },
9639   { 1281, "MPL_IDN_COMPLETE_SET_1" },
9640   { 1282, "MPL_IDN_COMPLETE_SET_2" },
9641   { 1283, "MPL_IDN_COMPLETE_SET_3" },
9642   { 1284, "MPL_IDN_COMPLETE" },
9643   { 1285, "IDN_COMPLETE_PENDING" },
9644   { 1536, "MPL_UDN_COMPLETE_SET_0" },
9645   { 1537, "MPL_UDN_COMPLETE_SET_1" },
9646   { 1538, "MPL_UDN_COMPLETE_SET_2" },
9647   { 1539, "MPL_UDN_COMPLETE_SET_3" },
9648   { 1540, "MPL_UDN_COMPLETE" },
9649   { 1541, "UDN_COMPLETE_PENDING" },
9650   { 1792, "MPL_ITLB_MISS_SET_0" },
9651   { 1793, "MPL_ITLB_MISS_SET_1" },
9652   { 1794, "MPL_ITLB_MISS_SET_2" },
9653   { 1795, "MPL_ITLB_MISS_SET_3" },
9654   { 1796, "MPL_ITLB_MISS" },
9655   { 1797, "ITLB_TSB_BASE_ADDR_0" },
9656   { 1798, "ITLB_TSB_BASE_ADDR_1" },
9657   { 1920, "ITLB_CURRENT_ATTR" },
9658   { 1921, "ITLB_CURRENT_PA" },
9659   { 1922, "ITLB_CURRENT_VA" },
9660   { 1923, "ITLB_INDEX" },
9661   { 1924, "ITLB_MATCH_0" },
9662   { 1925, "ITLB_PERF" },
9663   { 1926, "ITLB_PR" },
9664   { 1927, "ITLB_TSB_ADDR_0" },
9665   { 1928, "ITLB_TSB_ADDR_1" },
9666   { 1929, "ITLB_TSB_FILL_CURRENT_ATTR" },
9667   { 1930, "ITLB_TSB_FILL_MATCH" },
9668   { 1931, "NUMBER_ITLB" },
9669   { 1932, "REPLACEMENT_ITLB" },
9670   { 1933, "WIRED_ITLB" },
9671   { 2048, "MPL_ILL_SET_0" },
9672   { 2049, "MPL_ILL_SET_1" },
9673   { 2050, "MPL_ILL_SET_2" },
9674   { 2051, "MPL_ILL_SET_3" },
9675   { 2052, "MPL_ILL" },
9676   { 2304, "MPL_GPV_SET_0" },
9677   { 2305, "MPL_GPV_SET_1" },
9678   { 2306, "MPL_GPV_SET_2" },
9679   { 2307, "MPL_GPV_SET_3" },
9680   { 2308, "MPL_GPV" },
9681   { 2309, "GPV_REASON" },
9682   { 2560, "MPL_IDN_ACCESS_SET_0" },
9683   { 2561, "MPL_IDN_ACCESS_SET_1" },
9684   { 2562, "MPL_IDN_ACCESS_SET_2" },
9685   { 2563, "MPL_IDN_ACCESS_SET_3" },
9686   { 2564, "MPL_IDN_ACCESS" },
9687   { 2565, "IDN_DEMUX_COUNT_0" },
9688   { 2566, "IDN_DEMUX_COUNT_1" },
9689   { 2567, "IDN_FLUSH_EGRESS" },
9690   { 2568, "IDN_PENDING" },
9691   { 2569, "IDN_ROUTE_ORDER" },
9692   { 2570, "IDN_SP_FIFO_CNT" },
9693   { 2688, "IDN_DATA_AVAIL" },
9694   { 2816, "MPL_UDN_ACCESS_SET_0" },
9695   { 2817, "MPL_UDN_ACCESS_SET_1" },
9696   { 2818, "MPL_UDN_ACCESS_SET_2" },
9697   { 2819, "MPL_UDN_ACCESS_SET_3" },
9698   { 2820, "MPL_UDN_ACCESS" },
9699   { 2821, "UDN_DEMUX_COUNT_0" },
9700   { 2822, "UDN_DEMUX_COUNT_1" },
9701   { 2823, "UDN_DEMUX_COUNT_2" },
9702   { 2824, "UDN_DEMUX_COUNT_3" },
9703   { 2825, "UDN_FLUSH_EGRESS" },
9704   { 2826, "UDN_PENDING" },
9705   { 2827, "UDN_ROUTE_ORDER" },
9706   { 2828, "UDN_SP_FIFO_CNT" },
9707   { 2944, "UDN_DATA_AVAIL" },
9708   { 3072, "MPL_SWINT_3_SET_0" },
9709   { 3073, "MPL_SWINT_3_SET_1" },
9710   { 3074, "MPL_SWINT_3_SET_2" },
9711   { 3075, "MPL_SWINT_3_SET_3" },
9712   { 3076, "MPL_SWINT_3" },
9713   { 3328, "MPL_SWINT_2_SET_0" },
9714   { 3329, "MPL_SWINT_2_SET_1" },
9715   { 3330, "MPL_SWINT_2_SET_2" },
9716   { 3331, "MPL_SWINT_2_SET_3" },
9717   { 3332, "MPL_SWINT_2" },
9718   { 3584, "MPL_SWINT_1_SET_0" },
9719   { 3585, "MPL_SWINT_1_SET_1" },
9720   { 3586, "MPL_SWINT_1_SET_2" },
9721   { 3587, "MPL_SWINT_1_SET_3" },
9722   { 3588, "MPL_SWINT_1" },
9723   { 3840, "MPL_SWINT_0_SET_0" },
9724   { 3841, "MPL_SWINT_0_SET_1" },
9725   { 3842, "MPL_SWINT_0_SET_2" },
9726   { 3843, "MPL_SWINT_0_SET_3" },
9727   { 3844, "MPL_SWINT_0" },
9728   { 4096, "MPL_ILL_TRANS_SET_0" },
9729   { 4097, "MPL_ILL_TRANS_SET_1" },
9730   { 4098, "MPL_ILL_TRANS_SET_2" },
9731   { 4099, "MPL_ILL_TRANS_SET_3" },
9732   { 4100, "MPL_ILL_TRANS" },
9733   { 4101, "ILL_TRANS_REASON" },
9734   { 4102, "ILL_VA_PC" },
9735   { 4352, "MPL_UNALIGN_DATA_SET_0" },
9736   { 4353, "MPL_UNALIGN_DATA_SET_1" },
9737   { 4354, "MPL_UNALIGN_DATA_SET_2" },
9738   { 4355, "MPL_UNALIGN_DATA_SET_3" },
9739   { 4356, "MPL_UNALIGN_DATA" },
9740   { 4608, "MPL_DTLB_MISS_SET_0" },
9741   { 4609, "MPL_DTLB_MISS_SET_1" },
9742   { 4610, "MPL_DTLB_MISS_SET_2" },
9743   { 4611, "MPL_DTLB_MISS_SET_3" },
9744   { 4612, "MPL_DTLB_MISS" },
9745   { 4613, "DTLB_TSB_BASE_ADDR_0" },
9746   { 4614, "DTLB_TSB_BASE_ADDR_1" },
9747   { 4736, "AAR" },
9748   { 4737, "CACHE_PINNED_WAYS" },
9749   { 4738, "DTLB_BAD_ADDR" },
9750   { 4739, "DTLB_BAD_ADDR_REASON" },
9751   { 4740, "DTLB_CURRENT_ATTR" },
9752   { 4741, "DTLB_CURRENT_PA" },
9753   { 4742, "DTLB_CURRENT_VA" },
9754   { 4743, "DTLB_INDEX" },
9755   { 4744, "DTLB_MATCH_0" },
9756   { 4745, "DTLB_PERF" },
9757   { 4746, "DTLB_TSB_ADDR_0" },
9758   { 4747, "DTLB_TSB_ADDR_1" },
9759   { 4748, "DTLB_TSB_FILL_CURRENT_ATTR" },
9760   { 4749, "DTLB_TSB_FILL_MATCH" },
9761   { 4750, "NUMBER_DTLB" },
9762   { 4751, "REPLACEMENT_DTLB" },
9763   { 4752, "WIRED_DTLB" },
9764   { 4864, "MPL_DTLB_ACCESS_SET_0" },
9765   { 4865, "MPL_DTLB_ACCESS_SET_1" },
9766   { 4866, "MPL_DTLB_ACCESS_SET_2" },
9767   { 4867, "MPL_DTLB_ACCESS_SET_3" },
9768   { 4868, "MPL_DTLB_ACCESS" },
9769   { 5120, "MPL_IDN_FIREWALL_SET_0" },
9770   { 5121, "MPL_IDN_FIREWALL_SET_1" },
9771   { 5122, "MPL_IDN_FIREWALL_SET_2" },
9772   { 5123, "MPL_IDN_FIREWALL_SET_3" },
9773   { 5124, "MPL_IDN_FIREWALL" },
9774   { 5125, "IDN_DIRECTION_PROTECT" },
9775   { 5376, "MPL_UDN_FIREWALL_SET_0" },
9776   { 5377, "MPL_UDN_FIREWALL_SET_1" },
9777   { 5378, "MPL_UDN_FIREWALL_SET_2" },
9778   { 5379, "MPL_UDN_FIREWALL_SET_3" },
9779   { 5380, "MPL_UDN_FIREWALL" },
9780   { 5381, "UDN_DIRECTION_PROTECT" },
9781   { 5632, "MPL_TILE_TIMER_SET_0" },
9782   { 5633, "MPL_TILE_TIMER_SET_1" },
9783   { 5634, "MPL_TILE_TIMER_SET_2" },
9784   { 5635, "MPL_TILE_TIMER_SET_3" },
9785   { 5636, "MPL_TILE_TIMER" },
9786   { 5637, "TILE_TIMER_CONTROL" },
9787   { 5888, "MPL_AUX_TILE_TIMER_SET_0" },
9788   { 5889, "MPL_AUX_TILE_TIMER_SET_1" },
9789   { 5890, "MPL_AUX_TILE_TIMER_SET_2" },
9790   { 5891, "MPL_AUX_TILE_TIMER_SET_3" },
9791   { 5892, "MPL_AUX_TILE_TIMER" },
9792   { 5893, "AUX_TILE_TIMER_CONTROL" },
9793   { 6144, "MPL_IDN_TIMER_SET_0" },
9794   { 6145, "MPL_IDN_TIMER_SET_1" },
9795   { 6146, "MPL_IDN_TIMER_SET_2" },
9796   { 6147, "MPL_IDN_TIMER_SET_3" },
9797   { 6148, "MPL_IDN_TIMER" },
9798   { 6149, "IDN_DEADLOCK_COUNT" },
9799   { 6150, "IDN_DEADLOCK_TIMEOUT" },
9800   { 6400, "MPL_UDN_TIMER_SET_0" },
9801   { 6401, "MPL_UDN_TIMER_SET_1" },
9802   { 6402, "MPL_UDN_TIMER_SET_2" },
9803   { 6403, "MPL_UDN_TIMER_SET_3" },
9804   { 6404, "MPL_UDN_TIMER" },
9805   { 6405, "UDN_DEADLOCK_COUNT" },
9806   { 6406, "UDN_DEADLOCK_TIMEOUT" },
9807   { 6656, "MPL_IDN_AVAIL_SET_0" },
9808   { 6657, "MPL_IDN_AVAIL_SET_1" },
9809   { 6658, "MPL_IDN_AVAIL_SET_2" },
9810   { 6659, "MPL_IDN_AVAIL_SET_3" },
9811   { 6660, "MPL_IDN_AVAIL" },
9812   { 6661, "IDN_AVAIL_EN" },
9813   { 6912, "MPL_UDN_AVAIL_SET_0" },
9814   { 6913, "MPL_UDN_AVAIL_SET_1" },
9815   { 6914, "MPL_UDN_AVAIL_SET_2" },
9816   { 6915, "MPL_UDN_AVAIL_SET_3" },
9817   { 6916, "MPL_UDN_AVAIL" },
9818   { 6917, "UDN_AVAIL_EN" },
9819   { 7168, "MPL_IPI_3_SET_0" },
9820   { 7169, "MPL_IPI_3_SET_1" },
9821   { 7170, "MPL_IPI_3_SET_2" },
9822   { 7171, "MPL_IPI_3_SET_3" },
9823   { 7172, "MPL_IPI_3" },
9824   { 7173, "IPI_EVENT_3" },
9825   { 7174, "IPI_EVENT_RESET_3" },
9826   { 7175, "IPI_EVENT_SET_3" },
9827   { 7176, "IPI_MASK_3" },
9828   { 7177, "IPI_MASK_RESET_3" },
9829   { 7178, "IPI_MASK_SET_3" },
9830   { 7424, "MPL_IPI_2_SET_0" },
9831   { 7425, "MPL_IPI_2_SET_1" },
9832   { 7426, "MPL_IPI_2_SET_2" },
9833   { 7427, "MPL_IPI_2_SET_3" },
9834   { 7428, "MPL_IPI_2" },
9835   { 7429, "IPI_EVENT_2" },
9836   { 7430, "IPI_EVENT_RESET_2" },
9837   { 7431, "IPI_EVENT_SET_2" },
9838   { 7432, "IPI_MASK_2" },
9839   { 7433, "IPI_MASK_RESET_2" },
9840   { 7434, "IPI_MASK_SET_2" },
9841   { 7680, "MPL_IPI_1_SET_0" },
9842   { 7681, "MPL_IPI_1_SET_1" },
9843   { 7682, "MPL_IPI_1_SET_2" },
9844   { 7683, "MPL_IPI_1_SET_3" },
9845   { 7684, "MPL_IPI_1" },
9846   { 7685, "IPI_EVENT_1" },
9847   { 7686, "IPI_EVENT_RESET_1" },
9848   { 7687, "IPI_EVENT_SET_1" },
9849   { 7688, "IPI_MASK_1" },
9850   { 7689, "IPI_MASK_RESET_1" },
9851   { 7690, "IPI_MASK_SET_1" },
9852   { 7936, "MPL_IPI_0_SET_0" },
9853   { 7937, "MPL_IPI_0_SET_1" },
9854   { 7938, "MPL_IPI_0_SET_2" },
9855   { 7939, "MPL_IPI_0_SET_3" },
9856   { 7940, "MPL_IPI_0" },
9857   { 7941, "IPI_EVENT_0" },
9858   { 7942, "IPI_EVENT_RESET_0" },
9859   { 7943, "IPI_EVENT_SET_0" },
9860   { 7944, "IPI_MASK_0" },
9861   { 7945, "IPI_MASK_RESET_0" },
9862   { 7946, "IPI_MASK_SET_0" },
9863   { 8192, "MPL_PERF_COUNT_SET_0" },
9864   { 8193, "MPL_PERF_COUNT_SET_1" },
9865   { 8194, "MPL_PERF_COUNT_SET_2" },
9866   { 8195, "MPL_PERF_COUNT_SET_3" },
9867   { 8196, "MPL_PERF_COUNT" },
9868   { 8197, "PERF_COUNT_0" },
9869   { 8198, "PERF_COUNT_1" },
9870   { 8199, "PERF_COUNT_CTL" },
9871   { 8200, "PERF_COUNT_DN_CTL" },
9872   { 8201, "PERF_COUNT_STS" },
9873   { 8202, "WATCH_MASK" },
9874   { 8203, "WATCH_VAL" },
9875   { 8448, "MPL_AUX_PERF_COUNT_SET_0" },
9876   { 8449, "MPL_AUX_PERF_COUNT_SET_1" },
9877   { 8450, "MPL_AUX_PERF_COUNT_SET_2" },
9878   { 8451, "MPL_AUX_PERF_COUNT_SET_3" },
9879   { 8452, "MPL_AUX_PERF_COUNT" },
9880   { 8453, "AUX_PERF_COUNT_0" },
9881   { 8454, "AUX_PERF_COUNT_1" },
9882   { 8455, "AUX_PERF_COUNT_CTL" },
9883   { 8456, "AUX_PERF_COUNT_STS" },
9884   { 8704, "MPL_INTCTRL_3_SET_0" },
9885   { 8705, "MPL_INTCTRL_3_SET_1" },
9886   { 8706, "MPL_INTCTRL_3_SET_2" },
9887   { 8707, "MPL_INTCTRL_3_SET_3" },
9888   { 8708, "MPL_INTCTRL_3" },
9889   { 8709, "INTCTRL_3_STATUS" },
9890   { 8710, "INTERRUPT_MASK_3" },
9891   { 8711, "INTERRUPT_MASK_RESET_3" },
9892   { 8712, "INTERRUPT_MASK_SET_3" },
9893   { 8713, "INTERRUPT_VECTOR_BASE_3" },
9894   { 8714, "SINGLE_STEP_EN_0_3" },
9895   { 8715, "SINGLE_STEP_EN_1_3" },
9896   { 8716, "SINGLE_STEP_EN_2_3" },
9897   { 8717, "SINGLE_STEP_EN_3_3" },
9898   { 8832, "EX_CONTEXT_3_0" },
9899   { 8833, "EX_CONTEXT_3_1" },
9900   { 8834, "SYSTEM_SAVE_3_0" },
9901   { 8835, "SYSTEM_SAVE_3_1" },
9902   { 8836, "SYSTEM_SAVE_3_2" },
9903   { 8837, "SYSTEM_SAVE_3_3" },
9904   { 8960, "MPL_INTCTRL_2_SET_0" },
9905   { 8961, "MPL_INTCTRL_2_SET_1" },
9906   { 8962, "MPL_INTCTRL_2_SET_2" },
9907   { 8963, "MPL_INTCTRL_2_SET_3" },
9908   { 8964, "MPL_INTCTRL_2" },
9909   { 8965, "INTCTRL_2_STATUS" },
9910   { 8966, "INTERRUPT_MASK_2" },
9911   { 8967, "INTERRUPT_MASK_RESET_2" },
9912   { 8968, "INTERRUPT_MASK_SET_2" },
9913   { 8969, "INTERRUPT_VECTOR_BASE_2" },
9914   { 8970, "SINGLE_STEP_EN_0_2" },
9915   { 8971, "SINGLE_STEP_EN_1_2" },
9916   { 8972, "SINGLE_STEP_EN_2_2" },
9917   { 8973, "SINGLE_STEP_EN_3_2" },
9918   { 9088, "EX_CONTEXT_2_0" },
9919   { 9089, "EX_CONTEXT_2_1" },
9920   { 9090, "SYSTEM_SAVE_2_0" },
9921   { 9091, "SYSTEM_SAVE_2_1" },
9922   { 9092, "SYSTEM_SAVE_2_2" },
9923   { 9093, "SYSTEM_SAVE_2_3" },
9924   { 9216, "MPL_INTCTRL_1_SET_0" },
9925   { 9217, "MPL_INTCTRL_1_SET_1" },
9926   { 9218, "MPL_INTCTRL_1_SET_2" },
9927   { 9219, "MPL_INTCTRL_1_SET_3" },
9928   { 9220, "MPL_INTCTRL_1" },
9929   { 9221, "INTCTRL_1_STATUS" },
9930   { 9222, "INTERRUPT_MASK_1" },
9931   { 9223, "INTERRUPT_MASK_RESET_1" },
9932   { 9224, "INTERRUPT_MASK_SET_1" },
9933   { 9225, "INTERRUPT_VECTOR_BASE_1" },
9934   { 9226, "SINGLE_STEP_EN_0_1" },
9935   { 9227, "SINGLE_STEP_EN_1_1" },
9936   { 9228, "SINGLE_STEP_EN_2_1" },
9937   { 9229, "SINGLE_STEP_EN_3_1" },
9938   { 9344, "EX_CONTEXT_1_0" },
9939   { 9345, "EX_CONTEXT_1_1" },
9940   { 9346, "SYSTEM_SAVE_1_0" },
9941   { 9347, "SYSTEM_SAVE_1_1" },
9942   { 9348, "SYSTEM_SAVE_1_2" },
9943   { 9349, "SYSTEM_SAVE_1_3" },
9944   { 9472, "MPL_INTCTRL_0_SET_0" },
9945   { 9473, "MPL_INTCTRL_0_SET_1" },
9946   { 9474, "MPL_INTCTRL_0_SET_2" },
9947   { 9475, "MPL_INTCTRL_0_SET_3" },
9948   { 9476, "MPL_INTCTRL_0" },
9949   { 9477, "INTCTRL_0_STATUS" },
9950   { 9478, "INTERRUPT_MASK_0" },
9951   { 9479, "INTERRUPT_MASK_RESET_0" },
9952   { 9480, "INTERRUPT_MASK_SET_0" },
9953   { 9481, "INTERRUPT_VECTOR_BASE_0" },
9954   { 9482, "SINGLE_STEP_EN_0_0" },
9955   { 9483, "SINGLE_STEP_EN_1_0" },
9956   { 9484, "SINGLE_STEP_EN_2_0" },
9957   { 9485, "SINGLE_STEP_EN_3_0" },
9958   { 9600, "EX_CONTEXT_0_0" },
9959   { 9601, "EX_CONTEXT_0_1" },
9960   { 9602, "SYSTEM_SAVE_0_0" },
9961   { 9603, "SYSTEM_SAVE_0_1" },
9962   { 9604, "SYSTEM_SAVE_0_2" },
9963   { 9605, "SYSTEM_SAVE_0_3" },
9964   { 9728, "MPL_BOOT_ACCESS_SET_0" },
9965   { 9729, "MPL_BOOT_ACCESS_SET_1" },
9966   { 9730, "MPL_BOOT_ACCESS_SET_2" },
9967   { 9731, "MPL_BOOT_ACCESS_SET_3" },
9968   { 9732, "MPL_BOOT_ACCESS" },
9969   { 9733, "BIG_ENDIAN_CONFIG" },
9970   { 9734, "CACHE_INVALIDATION_COMPRESSION_MODE" },
9971   { 9735, "CACHE_INVALIDATION_MASK_0" },
9972   { 9736, "CACHE_INVALIDATION_MASK_1" },
9973   { 9737, "CACHE_INVALIDATION_MASK_2" },
9974   { 9738, "CBOX_CACHEASRAM_CONFIG" },
9975   { 9739, "CBOX_CACHE_CONFIG" },
9976   { 9740, "CBOX_HOME_MAP_ADDR" },
9977   { 9741, "CBOX_HOME_MAP_DATA" },
9978   { 9742, "CBOX_MMAP_0" },
9979   { 9743, "CBOX_MMAP_1" },
9980   { 9744, "CBOX_MMAP_2" },
9981   { 9745, "CBOX_MMAP_3" },
9982   { 9746, "CBOX_MSR" },
9983   { 9747, "DIAG_BCST_CTL" },
9984   { 9748, "DIAG_BCST_MASK" },
9985   { 9749, "DIAG_BCST_TRIGGER" },
9986   { 9750, "DIAG_MUX_CTL" },
9987   { 9751, "DIAG_TRACE_CTL" },
9988   { 9752, "DIAG_TRACE_DATA" },
9989   { 9753, "DIAG_TRACE_STS" },
9990   { 9754, "IDN_DEMUX_BUF_THRESH" },
9991   { 9755, "L1_I_PIN_WAY_0" },
9992   { 9756, "MEM_ROUTE_ORDER" },
9993   { 9757, "MEM_STRIPE_CONFIG" },
9994   { 9758, "PERF_COUNT_PLS" },
9995   { 9759, "PSEUDO_RANDOM_NUMBER_MODIFY" },
9996   { 9760, "QUIESCE_CTL" },
9997   { 9761, "RSHIM_COORD" },
9998   { 9762, "SBOX_CONFIG" },
9999   { 9763, "UDN_DEMUX_BUF_THRESH" },
10000   { 9764, "XDN_CORE_STARVATION_COUNT" },
10001   { 9765, "XDN_ROUND_ROBIN_ARB_CTL" },
10002   { 9856, "CYCLE_MODIFY" },
10003   { 9857, "I_AAR" },
10004   { 9984, "MPL_WORLD_ACCESS_SET_0" },
10005   { 9985, "MPL_WORLD_ACCESS_SET_1" },
10006   { 9986, "MPL_WORLD_ACCESS_SET_2" },
10007   { 9987, "MPL_WORLD_ACCESS_SET_3" },
10008   { 9988, "MPL_WORLD_ACCESS" },
10009   { 9989, "DONE" },
10010   { 9990, "DSTREAM_PF" },
10011   { 9991, "FAIL" },
10012   { 9992, "INTERRUPT_CRITICAL_SECTION" },
10013   { 9993, "PASS" },
10014   { 9994, "PSEUDO_RANDOM_NUMBER" },
10015   { 9995, "TILE_COORD" },
10016   { 9996, "TILE_RTF_HWM" },
10017   { 10112, "CMPEXCH_VALUE" },
10018   { 10113, "CYCLE" },
10019   { 10114, "EVENT_BEGIN" },
10020   { 10115, "EVENT_END" },
10021   { 10116, "PROC_STATUS" },
10022   { 10117, "SIM_CONTROL" },
10023   { 10118, "SIM_SOCKET" },
10024   { 10119, "STATUS_SATURATE" },
10025   { 10240, "MPL_I_ASID_SET_0" },
10026   { 10241, "MPL_I_ASID_SET_1" },
10027   { 10242, "MPL_I_ASID_SET_2" },
10028   { 10243, "MPL_I_ASID_SET_3" },
10029   { 10244, "MPL_I_ASID" },
10030   { 10245, "I_ASID" },
10031   { 10496, "MPL_D_ASID_SET_0" },
10032   { 10497, "MPL_D_ASID_SET_1" },
10033   { 10498, "MPL_D_ASID_SET_2" },
10034   { 10499, "MPL_D_ASID_SET_3" },
10035   { 10500, "MPL_D_ASID" },
10036   { 10501, "D_ASID" },
10037   { 10752, "MPL_DOUBLE_FAULT_SET_0" },
10038   { 10753, "MPL_DOUBLE_FAULT_SET_1" },
10039   { 10754, "MPL_DOUBLE_FAULT_SET_2" },
10040   { 10755, "MPL_DOUBLE_FAULT_SET_3" },
10041   { 10756, "MPL_DOUBLE_FAULT" },
10042   { 10757, "LAST_INTERRUPT_REASON" },
10043 };
10044 
10045 const int tilegx_num_sprs = 441;
10046 
10047 const char *
get_tilegx_spr_name(int num)10048 get_tilegx_spr_name (int num)
10049 {
10050   void *result;
10051   struct tilegx_spr key;
10052 
10053   key.number = num;
10054   result = bsearch((const void *) &key, (const void *) tilegx_sprs,
10055                    tilegx_num_sprs, sizeof (struct tilegx_spr),
10056                    tilegx_spr_compare);
10057 
10058   if (result == NULL)
10059   {
10060     return (NULL);
10061   }
10062   else
10063   {
10064     struct tilegx_spr *result_ptr = (struct tilegx_spr *) result;
10065     return (result_ptr->name);
10066   }
10067 }
10068 
10069 int
print_insn_tilegx(unsigned char * memaddr)10070 print_insn_tilegx (unsigned char * memaddr)
10071 {
10072   struct tilegx_decoded_instruction
10073     decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
10074   unsigned char opbuf[TILEGX_BUNDLE_SIZE_IN_BYTES];
10075   int i, num_instructions, num_printed;
10076   tilegx_mnemonic padding_mnemonic;
10077 
10078   memcpy((void *)opbuf, (void *)memaddr, TILEGX_BUNDLE_SIZE_IN_BYTES);
10079 
10080   /* Parse the instructions in the bundle. */
10081   num_instructions =
10082     parse_insn_tilegx (*(unsigned long long *)opbuf, (unsigned long long)memaddr, decoded);
10083 
10084   /* Print the instructions in the bundle. */
10085   printf("{ ");
10086   num_printed = 0;
10087 
10088   /* Determine which nop opcode is used for padding and should be skipped. */
10089   padding_mnemonic = TILEGX_OPC_FNOP;
10090   for (i = 0; i < num_instructions; i++)
10091   {
10092     if (!decoded[i].opcode->can_bundle)
10093     {
10094       /* Instructions that cannot be bundled are padded out with nops,
10095          rather than fnops. Displaying them is always clutter. */
10096       padding_mnemonic = TILEGX_OPC_NOP;
10097       break;
10098     }
10099   }
10100 
10101   for (i = 0; i < num_instructions; i++)
10102   {
10103     const struct tilegx_opcode *opcode = decoded[i].opcode;
10104     const char *name;
10105     int j;
10106 
10107     /* Do not print out fnops, unless everything is an fnop, in
10108        which case we will print out just the last one. */
10109     if (opcode->mnemonic == padding_mnemonic
10110         && (num_printed > 0 || i + 1 < num_instructions))
10111       continue;
10112 
10113     if (num_printed > 0)
10114       printf(" ; ");
10115     ++num_printed;
10116 
10117     name = opcode->name;
10118     if (name == NULL)
10119       name = "<invalid>";
10120     printf("%s", name);
10121 
10122     for (j = 0; j < opcode->num_operands; j++)
10123     {
10124       unsigned long long num;
10125       const struct tilegx_operand *op;
10126       const char *spr_name;
10127 
10128       if (j > 0)
10129         printf (",");
10130       printf (" ");
10131 
10132       num = decoded[i].operand_values[j];
10133 
10134       op = decoded[i].operands[j];
10135       switch (op->type)
10136       {
10137       case TILEGX_OP_TYPE_REGISTER:
10138         printf ("%s", tilegx_register_names[(int)num]);
10139         break;
10140       case TILEGX_OP_TYPE_SPR:
10141         spr_name = get_tilegx_spr_name(num);
10142         if (spr_name != NULL)
10143           printf ("%s", spr_name);
10144         else
10145           printf ("%d", (int)num);
10146         break;
10147       case TILEGX_OP_TYPE_IMMEDIATE:
10148         printf ("%d", (int)num);
10149         break;
10150       case TILEGX_OP_TYPE_ADDRESS:
10151         printf ("0x%016llx", num);
10152         break;
10153       default:
10154         abort ();
10155       }
10156     }
10157   }
10158   printf (" }\n");
10159 
10160   return TILEGX_BUNDLE_SIZE_IN_BYTES;
10161 }
10162