1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet 31 */ 32 33 #ifndef __SUNXI_EMAC_H__ 34 #define __SUNXI_EMAC_H__ 35 36 #define EMAC_BASIC_CTL_0 0x00 37 #define BASIC_CTL_SPEED (0x3 << 2) 38 #define BASIC_CTL_SPEED_SHIFT 2 39 #define BASIC_CTL_SPEED_1000 0 40 #define BASIC_CTL_SPEED_10 2 41 #define BASIC_CTL_SPEED_100 3 42 #define BASIC_CTL_LOOPBACK (1 << 1) 43 #define BASIC_CTL_DUPLEX (1 << 0) 44 #define EMAC_BASIC_CTL_1 0x04 45 #define BASIC_CTL_BURST_LEN (0x3f << 24) 46 #define BASIC_CTL_BURST_LEN_SHIFT 24 47 #define BASIC_CTL_RX_TX_PRI (1 << 1) 48 #define BASIC_CTL_SOFT_RST (1 << 0) 49 #define EMAC_INT_STA 0x08 50 #define RGMII_LINK_STA_INT (1 << 16) 51 #define RX_EARLY_INT (1 << 13) 52 #define RX_OVERFLOW_INT (1 << 12) 53 #define RX_TIMEOUT_INT (1 << 11) 54 #define RX_DMA_STOPPED_INT (1 << 10) 55 #define RX_BUF_UA_INT (1 << 9) 56 #define RX_INT (1 << 8) 57 #define TX_EARLY_INT (1 << 5) 58 #define TX_UNDERFLOW_INT (1 << 4) 59 #define TX_TIMEOUT_INT (1 << 3) 60 #define TX_BUF_UA_INT (1 << 2) 61 #define TX_DMA_STOPPED_INT (1 << 1) 62 #define TX_INT (1 << 0) 63 #define EMAC_INT_EN 0x0c 64 #define RX_EARLY_INT_EN (1 << 13) 65 #define RX_OVERFLOW_INT_EN (1 << 12) 66 #define RX_TIMEOUT_INT_EN (1 << 11) 67 #define RX_DMA_STOPPED_INT_EN (1 << 10) 68 #define RX_BUF_UA_INT_EN (1 << 9) 69 #define RX_INT_EN (1 << 8) 70 #define TX_EARLY_INT_EN (1 << 5) 71 #define TX_UNDERFLOW_INT_EN (1 << 4) 72 #define TX_TIMEOUT_INT_EN (1 << 3) 73 #define TX_BUF_UA_INT_EN (1 << 2) 74 #define TX_DMA_STOPPED_INT_EN (1 << 1) 75 #define TX_INT_EN (1 << 0) 76 #define EMAC_TX_CTL_0 0x10 77 #define TX_EN (1 << 31) 78 #define TX_FRM_LEN_CTL (1 << 30) 79 #define EMAC_TX_CTL_1 0x14 80 #define TX_DMA_START (1 << 31) 81 #define TX_DMA_EN (1 << 30) 82 #define TX_TH (0x7 << 8) 83 #define TX_NEXT_FRAME (1 << 2) 84 #define TX_MD (1 << 1) 85 #define FLUSH_TX_FIFO (1 << 0) 86 #define EMAC_TX_FLOW_CTL 0x1c 87 #define PAUSE_TIME (0xffff << 4) 88 #define PAUSE_TIME_SHIFT 4 89 #define TX_FLOW_CTL_EN (1 << 0) 90 #define EMAC_TX_DMA_LIST 0x20 91 #define EMAC_RX_CTL_0 0x24 92 #define RX_EN (1 << 31) 93 #define RX_FRM_LEN_CTL (1 << 30) 94 #define JUMBO_FRM_EN (1 << 29) 95 #define STRIP_FCS (1 << 28) 96 #define CHECK_CRC (1 << 27) 97 #define RX_PAUSE_FRM_MD (1 << 17) 98 #define RX_FLOW_CTL_EN (1 << 16) 99 #define EMAC_RX_CTL_1 0x28 100 #define RX_DMA_START (1 << 31) 101 #define RX_DMA_EN (1 << 30) 102 #define RX_FIFO_FLOW_CTL (1 << 24) 103 #define RX_FLOW_CTL_TH_DEACT (0x3 << 22) 104 #define RX_FLOW_CTL_TH_ACT (0x3 << 20) 105 #define RX_TH (0x3 << 4) 106 #define RX_ERR_FRM (1 << 3) 107 #define RX_RUNT_FRM (1 << 2) 108 #define RX_MD (1 << 1) 109 #define FLUSH_RX_FRM (1 << 0) 110 #define EMAC_RX_DMA_LIST 0x34 111 #define EMAC_RX_FRM_FLT 0x38 112 #define DIS_ADDR_FILTER (1 << 31) 113 #define DIS_BROADCAST (1 << 17) 114 #define RX_ALL_MULTICAST (1 << 16) 115 #define CTL_FRM_FILTER (0x3 << 12) 116 #define CTL_FRM_FILTER_SHIFT 12 117 #define HASH_MULTICAST (1 << 9) 118 #define HASH_UNICAST (1 << 8) 119 #define SA_FILTER_EN (1 << 6) 120 #define SA_INV_FILTER (1 << 5) 121 #define DA_INV_FILTER (1 << 4) 122 #define FLT_MD (1 << 1) 123 #define RX_ALL (1 << 0) 124 #define EMAC_RX_HASH_0 0x40 125 #define EMAC_RX_HASH_1 0x44 126 #define EMAC_MII_CMD 0x48 127 #define MDC_DIV_RATIO_M (0x7 << 20) 128 #define MDC_DIV_RATIO_M_16 0 129 #define MDC_DIV_RATIO_M_32 1 130 #define MDC_DIV_RATIO_M_64 2 131 #define MDC_DIV_RATIO_M_128 3 132 #define MDC_DIV_RATIO_M_SHIFT 20 133 #define PHY_ADDR (0x1f << 12) 134 #define PHY_ADDR_SHIFT 12 135 #define PHY_REG_ADDR (0x1f << 4) 136 #define PHY_REG_ADDR_SHIFT 4 137 #define MII_WR (1 << 1) 138 #define MII_BUSY (1 << 0) 139 #define EMAC_MII_DATA 0x4c 140 #define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8) 141 #define EMAC_ADDR_LOW(n) (0x54 + (n) * 8) 142 #define EMAC_TX_DMA_STA 0xb0 143 #define EMAC_TX_DMA_CUR_DESC 0xb4 144 #define EMAC_TX_DMA_CUR_BUF 0xb8 145 #define EMAC_RX_DMA_STA 0xc0 146 #define EMAC_RX_DMA_CUR_DESC 0xc4 147 #define EMAC_RX_DMA_CUR_BUF 0xc8 148 #define EMAC_RGMII_STA 0xd0 149 150 struct sunxi_emac_desc { 151 uint32_t status; 152 /* Transmit */ 153 #define TX_DESC_CTL (1 << 31) 154 #define TX_HEADER_ERR (1 << 16) 155 #define TX_LENGTH_ERR (1 << 14) 156 #define TX_PAYLOAD_ERR (1 << 12) 157 #define TX_CRS_ERR (1 << 10) 158 #define TX_COL_ERR_0 (1 << 9) 159 #define TX_COL_ERR_1 (1 << 8) 160 #define TX_COL_CNT (0xf << 3) 161 #define TX_COL_CNT_SHIFT 3 162 #define TX_DEFER_ERR (1 << 2) 163 #define TX_UNDERFLOW_ERR (1 << 1) 164 #define TX_DEFER (1 << 0) 165 /* Receive */ 166 #define RX_DESC_CTL (1 << 31) 167 #define RX_DAF_FAIL (1 << 30) 168 #define RX_FRM_LEN (0x3fff << 16) 169 #define RX_FRM_LEN_SHIFT 16 170 #define RX_NO_ENOUGH_BUF_ERR (1 << 14) 171 #define RX_SAF_FAIL (1 << 13) 172 #define RX_OVERFLOW_ERR (1 << 11) 173 #define RX_FIR_DESC (1 << 9) 174 #define RX_LAST_DESC (1 << 8) 175 #define RX_HEADER_ERR (1 << 7) 176 #define RX_COL_ERR (1 << 6) 177 #define RX_FRM_TYPE (1 << 5) 178 #define RX_LENGTH_ERR (1 << 4) 179 #define RX_PHY_ERR (1 << 3) 180 #define RX_CRC_ERR (1 << 1) 181 #define RX_PAYLOAD_ERR (1 << 0) 182 183 uint32_t size; 184 /* Transmit */ 185 #define TX_INT_CTL (1 << 31) 186 #define TX_LAST_DESC (1 << 30) 187 #define TX_FIR_DESC (1 << 29) 188 #define TX_CHECKSUM_CTL (0x3 << 27) 189 #define TX_CHECKSUM_CTL_IP 1 190 #define TX_CHECKSUM_CTL_NO_PSE 2 191 #define TX_CHECKSUM_CTL_FULL 3 192 #define TX_CHECKSUM_CTL_SHIFT 27 193 #define TX_CRC_CTL (1 << 26) 194 #define TX_CHAIN_DESC (1 << 24) 195 #define TX_BUF_SIZE (0x7ff << 0) 196 #define TX_BUF_SIZE_SHIFT 0 197 /* Receive */ 198 #define RX_INT_CTL (1 << 31) 199 #define RX_CHAIN_DESC (1 << 24) 200 #define RX_BUF_SIZE (0x7ff << 0) 201 #define RX_BUF_SIZE_SHIFT 0 202 203 uint32_t addr; 204 205 uint32_t next; 206 } __packed __aligned(64); 207 208 __CTASSERT(sizeof(struct sunxi_emac_desc) == 64); 209 210 #endif /* !__SUNXI_EMAC_H__ */ 211