| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 72 static const MCPhysReg ArgRegs[] = { CC_PPC32_SVR4_Custom_AlignArgRegs() local
97 static const MCPhysReg ArgRegs[] = { CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
122 static const MCPhysReg ArgRegs[] = { CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
[all...] |
| H A D | PPCFastISel.cpp | 1374 processCallArgs(SmallVectorImpl<Value * > & Args,SmallVectorImpl<unsigned> & ArgRegs,SmallVectorImpl<MVT> & ArgVTs,SmallVectorImpl<ISD::ArgFlagsTy> & ArgFlags,SmallVectorImpl<unsigned> & RegArgs,CallingConv::ID CC,unsigned & NumBytes,bool IsVarArg) processCallArgs() argument
1602 SmallVector<unsigned, 8> ArgRegs; fastLowerCall() local
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| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVCallLowering.h | 34 SmallVector<Register> ArgRegs; member
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1876 ProcessCallArgs(SmallVectorImpl<Value * > & Args,SmallVectorImpl<Register> & ArgRegs,SmallVectorImpl<MVT> & ArgVTs,SmallVectorImpl<ISD::ArgFlagsTy> & ArgFlags,SmallVectorImpl<Register> & RegArgs,CallingConv::ID CC,unsigned & NumBytes,bool isVarArg) ProcessCallArgs() argument
2224 SmallVector<Register, 8> ArgRegs; ARMEmitLibcall() local
2333 SmallVector<Register, 8> ArgRegs; SelectCall() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 445 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); saveVarArgRegisters() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 409 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in lowerFormalArguments() local
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| H A D | MipsISelLowering.cpp | 4444 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); passByValArg() local
4527 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); writeVarArgRegs() local
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| /llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 559 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 96 lowerCall(MachineIRBuilder & MIRBuilder,const CallBase & CB,ArrayRef<Register> ResRegs,ArrayRef<ArrayRef<Register>> ArgRegs,Register SwiftErrorVReg,std::optional<PtrAuthInfo> PAI,Register ConvergenceCtrlToken,std::function<unsigned ()> GetCalleeReg) const lowerCall() argument
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| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 371 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(GPRArgRegs); in LowerFormalArguments() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 752 passSpecialInputs(MachineIRBuilder & MIRBuilder,CCState & CCInfo,SmallVectorImpl<std::pair<MCRegister,Register>> & ArgRegs,CallLoweringInfo & Info) const passSpecialInputs() argument
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1252 static const MCPhysReg ArgRegs[] = { LowerCCCArguments() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3283 SmallVector<unsigned, 16> ArgRegs; fastLowerCall() local
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 584 static const MCPhysReg ArgRegs[] = { LowerFormalArguments_32() local
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4027 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(ArgGPRs); LowerFormalArguments() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 143 static const MCPhysReg ArgRegs[] = { CC_SkipOdd() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 19696 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); LowerFormalArguments() local
|