1 enum { /* Cr0 */ 2 Pe = 0x00000001, /* Protected Mode Enable */ 3 Mp = 0x00000002, /* Monitor Coprocessor */ 4 Em = 0x00000004, /* Emulate Coprocessor */ 5 Ts = 0x00000008, /* Task Switched */ 6 Et = 0x00000010, /* Extension Type */ 7 Ne = 0x00000020, /* Numeric Error */ 8 Wp = 0x00010000, /* Write Protect */ 9 Am = 0x00040000, /* Alignment Mask */ 10 Nw = 0x20000000, /* Not Writethrough */ 11 Cd = 0x40000000, /* Cache Disable */ 12 Pg = 0x80000000, /* Paging Enable */ 13 }; 14 15 enum { /* Cr3 */ 16 Pwt = 0x00000008, /* Page-Level Writethrough */ 17 Pcd = 0x00000010, /* Page-Level Cache Disable */ 18 }; 19 20 enum { /* Cr4 */ 21 Vme = 0x00000001, /* Virtual-8086 Mode Extensions */ 22 Pvi = 0x00000002, /* Protected Mode Virtual Interrupts */ 23 Tsd = 0x00000004, /* Time-Stamp Disable */ 24 De = 0x00000008, /* Debugging Extensions */ 25 Pse = 0x00000010, /* Page-Size Extensions */ 26 Pae = 0x00000020, /* Physical Address Extension */ 27 Mce = 0x00000040, /* Machine Check Enable */ 28 Pge = 0x00000080, /* Page-Global Enable */ 29 Pce = 0x00000100, /* Performance Monitoring Counter Enable */ 30 Osfxsr = 0x00000200, /* FXSAVE/FXRSTOR Support */ 31 Osxmmexcpt = 0x00000400, /* Unmasked Exception Support */ 32 }; 33 34 enum { /* Rflags */ 35 Cf = 0x00000001, /* Carry Flag */ 36 Pf = 0x00000004, /* Parity Flag */ 37 Af = 0x00000010, /* Auxiliary Flag */ 38 Zf = 0x00000040, /* Zero Flag */ 39 Sf = 0x00000080, /* Sign Flag */ 40 Tf = 0x00000100, /* Trap Flag */ 41 If = 0x00000200, /* Interrupt Flag */ 42 Df = 0x00000400, /* Direction Flag */ 43 Of = 0x00000800, /* Overflow Flag */ 44 Iopl0 = 0x00000000, /* I/O Privilege Level */ 45 Iopl1 = 0x00001000, 46 Iopl2 = 0x00002000, 47 Iopl3 = 0x00003000, 48 Nt = 0x00004000, /* Nested Task */ 49 Rf = 0x00010000, /* Resume Flag */ 50 Vm = 0x00020000, /* Virtual-8086 Mode */ 51 Ac = 0x00040000, /* Alignment Check */ 52 Vif = 0x00080000, /* Virtual Interrupt Flag */ 53 Vip = 0x00100000, /* Virtual Interrupt Pending */ 54 Id = 0x00200000, /* ID Flag */ 55 }; 56 57 enum { /* MSRs */ 58 Efer = 0xc0000080, /* Extended Feature Enable */ 59 Star = 0xc0000081, /* Legacy Target IP and [CS]S */ 60 Lstar = 0xc0000082, /* Long Mode Target IP */ 61 Cstar = 0xc0000083, /* Compatibility Target IP */ 62 Sfmask = 0xc0000084, /* SYSCALL Flags Mask */ 63 FSbase = 0xc0000100, /* 64-bit FS Base Address */ 64 GSbase = 0xc0000101, /* 64-bit GS Base Address */ 65 KernelGSbase = 0xc0000102, /* SWAPGS instruction */ 66 }; 67 68 enum { /* Efer */ 69 Sce = 0x00000001, /* System Call Extension */ 70 Lme = 0x00000100, /* Long Mode Enable */ 71 Lma = 0x00000400, /* Long Mode Active */ 72 Nxe = 0x00000800, /* No-Execute Enable */ 73 Svme = 0x00001000, /* SVM Extension Enable */ 74 Ffxsr = 0x00004000, /* Fast FXSAVE/FXRSTOR */ 75 }; 76 77 enum { /* PML4E/PDPE/PDE/PTE */ 78 PteP = 0x0000000000000001ull,/* Present */ 79 PteRW = 0x0000000000000002ull,/* Read/Write */ 80 PteU = 0x0000000000000004ull,/* User/Supervisor */ 81 PtePWT = 0x0000000000000008ull,/* Page-Level Write Through */ 82 PtePCD = 0x0000000000000010ull,/* Page Level Cache Disable */ 83 PteA = 0x0000000000000020ull,/* Accessed */ 84 PteD = 0x0000000000000040ull,/* Dirty */ 85 PtePS = 0x0000000000000080ull,/* Page Size */ 86 Pte4KPAT = PtePS, /* PTE PAT */ 87 PteG = 0x0000000000000100ull,/* Global */ 88 Pte2MPAT = 0x0000000000001000ull,/* PDE PAT */ 89 Pte1GPAT = Pte2MPAT, /* PDPE PAT */ 90 PteNX = 0x8000000000000000ull,/* No Execute */ 91 }; 92 93 enum { /* Exceptions */ 94 IdtDE = 0, /* Divide-by-Zero Error */ 95 IdtDB = 1, /* Debug */ 96 IdtNMI = 2, /* Non-Maskable-Interrupt */ 97 IdtBP = 3, /* Breakpoint */ 98 IdtOF = 4, /* Overflow */ 99 IdtBR = 5, /* Bound-Range */ 100 IdtUD = 6, /* Invalid-Opcode */ 101 IdtNM = 7, /* Device-Not-Available */ 102 IdtDF = 8, /* Double-Fault */ 103 Idt09 = 9, /* unsupported */ 104 IdtTS = 10, /* Invalid-TSS */ 105 IdtNP = 11, /* Segment-Not-Present */ 106 IdtSS = 12, /* Stack */ 107 IdtGP = 13, /* General-Protection */ 108 IdtPF = 14, /* Page-Fault */ 109 Idt0F = 15, /* reserved */ 110 IdtMF = 16, /* x87 FPE-Pending */ 111 IdtAC = 17, /* Alignment-Check */ 112 IdtMC = 18, /* Machine-Check */ 113 IdtXF = 19, /* SIMD Floating-Point */ 114 }; 115 116 /* 117 * Vestigial Segmented Virtual Memory. 118 */ 119 enum { /* Segment Descriptor */ 120 SdISTM = 0x0000000700000000ull,/* Interrupt Stack Table Mask */ 121 SdA = 0x0000010000000000ull,/* Accessed */ 122 SdR = 0x0000020000000000ull,/* Readable (Code) */ 123 SdW = 0x0000020000000000ull,/* Writeable (Data) */ 124 SdE = 0x0000040000000000ull,/* Expand Down */ 125 SdaTSS = 0x0000090000000000ull,/* Available TSS */ 126 SdbTSS = 0x00000b0000000000ull,/* Busy TSS */ 127 SdCG = 0x00000c0000000000ull,/* Call Gate */ 128 SdIG = 0x00000e0000000000ull,/* Interrupt Gate */ 129 SdTG = 0x00000f0000000000ull,/* Trap Gate */ 130 SdCODE = 0x0000080000000000ull,/* Code/Data */ 131 SdS = 0x0000100000000000ull,/* System/User */ 132 SdDPL0 = 0x0000000000000000ull,/* Descriptor Privilege Level */ 133 SdDPL1 = 0x0000200000000000ull, 134 SdDPL2 = 0x0000400000000000ull, 135 SdDPL3 = 0x0000600000000000ull, 136 SdP = 0x0000800000000000ull,/* Present */ 137 Sd4G = 0x000f00000000ffffull,/* 4G Limit */ 138 SdL = 0x0020000000000000ull,/* Long Attribute */ 139 SdD = 0x0040000000000000ull,/* Default Operand Size */ 140 SdG = 0x0080000000000000ull,/* Granularity */ 141 }; 142 143 enum { /* Segment Selector */ 144 SsRPL0 = 0x0000, /* Requestor Privilege Level */ 145 SsRPL1 = 0x0001, 146 SsRPL2 = 0x0002, 147 SsRPL3 = 0x0003, 148 SsTIGDT = 0x0000, /* GDT Table Indicator */ 149 SsTILDT = 0x0004, /* LDT Table Indicator */ 150 SsSIM = 0xfff8, /* Selector Index Mask */ 151 }; 152 153 #define SSEL(si, tirpl) (((si)<<3)|(tirpl)) /* Segment Selector */ 154 155 enum { 156 SiNULL = 0, /* NULL selector index */ 157 SiCS = 1, /* CS selector index */ 158 SiDS = 2, /* DS selector index */ 159 SiU32CS = 3, /* User CS selector index */ 160 SiUDS = 4, /* User DS selector index */ 161 SiUCS = 5, /* User CS selector index */ 162 SiFS = 6, /* FS selector index */ 163 SiGS = 7, /* GS selector index */ 164 SiTSS = 8, /* TSS selector index */ 165 }; 166 167 /* 168 * Extern registers. 169 */ 170 #define RMACH R15 /* m-> */ 171 #define RUSER R14 /* up-> */ 172