| /llvm-project/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 39 struct AddOp : public SetTheory::Operator { in apply() argument
38 struct AddOp : public SetTheory::Operator { global() struct
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| /llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanRecipes.cpp | 1209 Instruction::BinaryOps AddOp; execute() local
1329 Instruction::BinaryOps AddOp; execute() local
[all...] |
| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 577 SDValue AddOp; in isADDADDMUL() local
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| /llvm-project/mlir/lib/Dialect/Tosa/IR/ |
| H A D | TosaOps.cpp | 1373 NARY_SHAPE_INFER(tosa::AddOp) NARY_SHAPE_INFER() argument
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 1017 constexpr unsigned AddOp = FP ? Instruction::FAdd : Instruction::Add; matchesSquareSum() local
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| H A D | InstCombineSelect.cpp | 2030 Instruction *AddOp = nullptr, *SubOp = nullptr; foldAddSubSelect() local
[all...] |
| /llvm-project/clang/lib/Analysis/ |
| H A D | UnsafeBufferUsage.cpp | 1346 const BinaryOperator *AddOp = nullptr; global() member in DerefSimplePtrArithFixableGadget
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2056 const MachineOperand &AddOp = MI.getOperand(2); getIncrementValue() local
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| /llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 2798 if (MulOpSCEV == Ops[AddOp]) { in getAddExpr() local
3193 for (const SCEV *AddOp : Add->operands()) { getMulExpr() local
4662 for (const SCEV *&AddOp : Ops) { removePointerBase() local
4855 for (const SCEV *AddOp : Add->operands()) { getPointerBase() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1686 unsigned AddOp = AMDGPU::V_ADD_CO_U32_e32; SelectFlatOffsetImpl() local
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| H A D | AMDGPUISelLowering.cpp | 4292 SDValue AddOp = getAddOneOp(V.getNode()); performMulCombine() local
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| /llvm-project/mlir/lib/Target/LLVMIR/Dialect/OpenMP/ |
| H A D | OpenMPToLLVMIRTranslation.cpp | 1630 __anonf04bb8b11e02(LLVM::AddOp) convertBinOpToAtomic() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 852 __anon0ae814870702(const MachineInstr &Instr, Register &MulOp1, Register &MulOp2, Register &AddOp, bool &MulOp1KillFlag, bool &MulOp2KillFlag, bool &AddOpKillFlag) reassociateFMA() argument
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1096 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; PromoteIntRes_ADDSUBSHLSAT() local
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| H A D | DAGCombiner.cpp | 6335 SDValue AddOp = DAG.getNode(ISD::ADD, DL, OpVT, LHS0, foldAndOrOfSETCC() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 39816 auto AddOp = [&Ops](SDValue Input, int InsertionPoint) -> int { combineX86ShufflesRecursively() local
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