xref: /netbsd-src/sys/arch/arm/sunxi/sunxi_lradc.h (revision 6bdb7968c2a5f6966f7e79d3f23c23c92bb797a1)
1 /* $NetBSD: sunxi_lradc.h,v 1.1 2018/03/07 20:55:31 bouyer Exp $ */
2 
3 /*-
4  * Copyright (c) 2016 Manuel Bouyer
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #define AWIN_LRADC_CTRL_REG		0x00
30 #define AWIN_LRADC_CTRL_FIRSTCONV_MASK		__BITS(31,24)
31 #define AWIN_LRADC_CTRL_FIRSTCONV_SHIFT		24
32 #define AWIN_LRADC_CTRL_CHAN_MASK		__BITS(23,22)
33 #define AWIN_LRADC_CTRL_CHAN_SHIFT		22
34 #define AWIN_LRADC_CTRL_CONT_MASK		__BITS(19,16)
35 #define AWIN_LRADC_CTRL_CONT_SHIFT		16
36 #define AWIN_LRADC_CTRL_KMODE_MASK		__BITS(13,12)
37 #define AWIN_LRADC_CTRL_KMODE_NORMAL		(0 << 12)
38 #define AWIN_LRADC_CTRL_KMODE_SINGLE		(1 << 12)
39 #define AWIN_LRADC_CTRL_KMODE_CONTINUE		(2 << 12)
40 #define AWIN_LRADC_CTRL_LV_A_B_CNT_MASK		__BITS(11,8)
41 #define AWIN_LRADC_CTRL_LV_A_B_CNT_SHIFT	8
42 #define AWIN_LRADC_CTRL_HOLD_EN			__BIT(6)
43 #define AWIN_LRADC_CTRL_LEVEL_B_MASK		__BITS(5,4)
44 #define AWIN_LRADC_CTRL_LEVEL_B_3C		(0 << 4)
45 #define AWIN_LRADC_CTRL_LEVEL_B_39		(1 << 4)
46 #define AWIN_LRADC_CTRL_LEVEL_B_36		(2 << 4)
47 #define AWIN_LRADC_CTRL_LEVEL_B_33		(3 << 4)
48 #define AWIN_LRADC_CTRL_RATE_MASK		__BITS(3,2)
49 #define AWIN_LRADC_CTRL_RATE_250		(0 << 2)
50 #define AWIN_LRADC_CTRL_RATE_125		(1 << 2)
51 #define AWIN_LRADC_CTRL_RATE_62			(2 << 2)
52 #define AWIN_LRADC_CTRL_RATE_31			(3 << 2)
53 #define AWIN_LRADC_CTRL_EN			__BIT(0)
54 #define AWIN_LRADC_INTC_REG		0x04
55 #define AWIN_LRADC_INTS_REG		0x08
56 #define AWIN_LRADC_INT_KEYUP1		__BIT(12)
57 #define AWIN_LRADC_INT_ALREADYHOLD1	__BIT(11)
58 #define AWIN_LRADC_INT_HOLD1		__BIT(10)
59 #define AWIN_LRADC_INT_KEY1		__BIT(9)
60 #define AWIN_LRADC_INT_DATA1		__BIT(8)
61 #define AWIN_LRADC_INT_KEYUP0		__BIT(4)
62 #define AWIN_LRADC_INT_ALREADYHOLD0	__BIT(3)
63 #define AWIN_LRADC_INT_HOLD0		__BIT(2)
64 #define AWIN_LRADC_INT_KEY0		__BIT(1)
65 #define AWIN_LRADC_INT_DATA0		__BIT(0)
66 #define AWIN_LRADC_DATA0_REG		0x0c
67 #define AWIN_LRADC_DATA1_REG		0x10
68 
69