1 /* $NetBSD: atombios.h,v 1.5 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2006-2007 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 26 /****************************************************************************/ 27 /*Portion I: Definitions shared between VBIOS and Driver */ 28 /****************************************************************************/ 29 30 31 #ifndef _ATOMBIOS_H 32 #define _ATOMBIOS_H 33 34 #define ATOM_VERSION_MAJOR 0x00020000 35 #define ATOM_VERSION_MINOR 0x00000002 36 37 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 38 39 /* Endianness should be specified before inclusion, 40 * default to little endian 41 */ 42 #ifndef ATOM_BIG_ENDIAN 43 #error Endian not specified 44 #endif 45 46 #ifdef _H2INC 47 #ifndef ULONG 48 typedef unsigned long ULONG; 49 #endif 50 51 #ifndef UCHAR 52 typedef unsigned char UCHAR; 53 #endif 54 55 #ifndef USHORT 56 typedef unsigned short USHORT; 57 #endif 58 #endif 59 60 #define ATOM_DAC_A 0 61 #define ATOM_DAC_B 1 62 #define ATOM_EXT_DAC 2 63 64 #define ATOM_CRTC1 0 65 #define ATOM_CRTC2 1 66 #define ATOM_CRTC3 2 67 #define ATOM_CRTC4 3 68 #define ATOM_CRTC5 4 69 #define ATOM_CRTC6 5 70 #define ATOM_CRTC_INVALID 0xFF 71 72 #define ATOM_DIGA 0 73 #define ATOM_DIGB 1 74 75 #define ATOM_PPLL1 0 76 #define ATOM_PPLL2 1 77 #define ATOM_DCPLL 2 78 #define ATOM_PPLL0 2 79 #define ATOM_PPLL3 3 80 81 #define ATOM_EXT_PLL1 8 82 #define ATOM_EXT_PLL2 9 83 #define ATOM_EXT_CLOCK 10 84 #define ATOM_PPLL_INVALID 0xFF 85 86 #define ENCODER_REFCLK_SRC_P1PLL 0 87 #define ENCODER_REFCLK_SRC_P2PLL 1 88 #define ENCODER_REFCLK_SRC_DCPLL 2 89 #define ENCODER_REFCLK_SRC_EXTCLK 3 90 #define ENCODER_REFCLK_SRC_INVALID 0xFF 91 92 #define ATOM_SCALER1 0 93 #define ATOM_SCALER2 1 94 95 #define ATOM_SCALER_DISABLE 0 96 #define ATOM_SCALER_CENTER 1 97 #define ATOM_SCALER_EXPANSION 2 98 #define ATOM_SCALER_MULTI_EX 3 99 100 #define ATOM_DISABLE 0 101 #define ATOM_ENABLE 1 102 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 103 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 104 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 105 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 106 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 107 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 108 #define ATOM_INIT (ATOM_DISABLE+7) 109 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 110 111 #define ATOM_BLANKING 1 112 #define ATOM_BLANKING_OFF 0 113 114 #define ATOM_CURSOR1 0 115 #define ATOM_CURSOR2 1 116 117 #define ATOM_ICON1 0 118 #define ATOM_ICON2 1 119 120 #define ATOM_CRT1 0 121 #define ATOM_CRT2 1 122 123 #define ATOM_TV_NTSC 1 124 #define ATOM_TV_NTSCJ 2 125 #define ATOM_TV_PAL 3 126 #define ATOM_TV_PALM 4 127 #define ATOM_TV_PALCN 5 128 #define ATOM_TV_PALN 6 129 #define ATOM_TV_PAL60 7 130 #define ATOM_TV_SECAM 8 131 #define ATOM_TV_CV 16 132 133 #define ATOM_DAC1_PS2 1 134 #define ATOM_DAC1_CV 2 135 #define ATOM_DAC1_NTSC 3 136 #define ATOM_DAC1_PAL 4 137 138 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 139 #define ATOM_DAC2_CV ATOM_DAC1_CV 140 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 141 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 142 143 #define ATOM_PM_ON 0 144 #define ATOM_PM_STANDBY 1 145 #define ATOM_PM_SUSPEND 2 146 #define ATOM_PM_OFF 3 147 148 /* Bit0:{=0:single, =1:dual}, 149 Bit1 {=0:666RGB, =1:888RGB}, 150 Bit2:3:{Grey level} 151 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 152 153 #define ATOM_PANEL_MISC_DUAL 0x00000001 154 #define ATOM_PANEL_MISC_888RGB 0x00000002 155 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 156 #define ATOM_PANEL_MISC_FPDI 0x00000010 157 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 158 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 159 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 160 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 161 162 163 #define MEMTYPE_DDR1 "DDR1" 164 #define MEMTYPE_DDR2 "DDR2" 165 #define MEMTYPE_DDR3 "DDR3" 166 #define MEMTYPE_DDR4 "DDR4" 167 168 #define ASIC_BUS_TYPE_PCI "PCI" 169 #define ASIC_BUS_TYPE_AGP "AGP" 170 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 171 172 /* Maximum size of that FireGL flag string */ 173 174 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 175 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 176 177 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 178 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 179 180 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 181 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 182 183 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 184 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 185 186 #pragma pack(1) /* BIOS data must use byte alignment */ 187 188 /* Define offset to location of ROM header. */ 189 190 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 191 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 192 193 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 194 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 195 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 196 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 197 198 /* Common header for all ROM Data tables. 199 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 200 And the pointer actually points to this header. */ 201 202 typedef struct _ATOM_COMMON_TABLE_HEADER 203 { 204 USHORT usStructureSize; 205 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 206 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 207 /*Image can't be updated, while Driver needs to carry the new table! */ 208 }ATOM_COMMON_TABLE_HEADER; 209 210 /****************************************************************************/ 211 // Structure stores the ROM header. 212 /****************************************************************************/ 213 typedef struct _ATOM_ROM_HEADER 214 { 215 ATOM_COMMON_TABLE_HEADER sHeader; 216 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 217 atombios should init it as "ATOM", don't change the position */ 218 USHORT usBiosRuntimeSegmentAddress; 219 USHORT usProtectedModeInfoOffset; 220 USHORT usConfigFilenameOffset; 221 USHORT usCRC_BlockOffset; 222 USHORT usBIOS_BootupMessageOffset; 223 USHORT usInt10Offset; 224 USHORT usPciBusDevInitCode; 225 USHORT usIoBaseAddress; 226 USHORT usSubsystemVendorID; 227 USHORT usSubsystemID; 228 USHORT usPCI_InfoOffset; 229 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 230 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 231 UCHAR ucExtendedFunctionCode; 232 UCHAR ucReserved; 233 }ATOM_ROM_HEADER; 234 235 /*==============================Command Table Portion==================================== */ 236 237 #ifdef UEFI_BUILD 238 #define UTEMP USHORT 239 #define USHORT void* 240 #endif 241 242 /****************************************************************************/ 243 // Structures used in Command.mtb 244 /****************************************************************************/ 245 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 246 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 247 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 248 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 249 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 250 USHORT DIGxEncoderControl; //Only used by Bios 251 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 252 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 253 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 254 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 255 USHORT GPIOPinControl; //Atomic Table, only used by Bios 256 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 257 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 258 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 259 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 260 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 261 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 262 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 263 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 264 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 265 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 266 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 267 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 268 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 269 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 272 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 273 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 274 USHORT GetConditionalGoldenSetting; //Only used by Bios 275 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 276 USHORT PatchMCSetting; //only used by BIOS 277 USHORT MC_SEQ_Control; //only used by BIOS 278 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 279 USHORT EnableScaler; //Atomic Table, used only by Bios 280 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 281 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 282 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 283 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 284 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 285 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 286 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 287 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 288 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 289 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 290 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 291 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 292 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 293 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 294 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 295 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 296 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 297 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 298 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 299 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 300 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 301 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 302 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 303 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 304 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 305 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 306 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 307 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 308 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 309 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 310 USHORT MemoryTraining; //Atomic Table, used only by Bios 311 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 312 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 314 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 315 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 316 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 317 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 318 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 319 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 320 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 321 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 322 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 323 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 324 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 325 USHORT DPEncoderService; //Function Table,only used by Bios 326 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 327 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 328 329 // For backward compatible 330 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 331 #define DPTranslatorControl DIG2EncoderControl 332 #define UNIPHYTransmitterControl DIG1TransmitterControl 333 #define LVTMATransmitterControl DIG2TransmitterControl 334 #define SetCRTC_DPM_State GetConditionalGoldenSetting 335 #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 336 #define HPDInterruptService ReadHWAssistedI2CStatus 337 #define EnableVGA_Access GetSCLKOverMCLKRatio 338 #define EnableYUV GetDispObjectInfo 339 #define DynamicClockGating EnableDispPowerGating 340 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 341 342 #define TMDSAEncoderControl PatchMCSetting 343 #define LVDSEncoderControl MC_SEQ_Control 344 #define LCD1OutputControl HW_Misc_Operation 345 #define TV1OutputControl Gfx_Harvesting 346 347 typedef struct _ATOM_MASTER_COMMAND_TABLE 348 { 349 ATOM_COMMON_TABLE_HEADER sHeader; 350 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 351 }ATOM_MASTER_COMMAND_TABLE; 352 353 /****************************************************************************/ 354 // Structures used in every command table 355 /****************************************************************************/ 356 typedef struct _ATOM_TABLE_ATTRIBUTE 357 { 358 #if ATOM_BIG_ENDIAN 359 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 360 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 362 #else 363 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 364 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 365 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 366 #endif 367 }ATOM_TABLE_ATTRIBUTE; 368 369 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 370 { 371 ATOM_TABLE_ATTRIBUTE sbfAccess; 372 USHORT susAccess; 373 }ATOM_TABLE_ATTRIBUTE_ACCESS; 374 375 /****************************************************************************/ 376 // Common header for all command tables. 377 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 378 // And the pointer actually points to this header. 379 /****************************************************************************/ 380 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 381 { 382 ATOM_COMMON_TABLE_HEADER CommonHeader; 383 ATOM_TABLE_ATTRIBUTE TableAttribute; 384 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 385 386 /****************************************************************************/ 387 // Structures used by ComputeMemoryEnginePLLTable 388 /****************************************************************************/ 389 #define COMPUTE_MEMORY_PLL_PARAM 1 390 #define COMPUTE_ENGINE_PLL_PARAM 2 391 #define ADJUST_MC_SETTING_PARAM 3 392 393 /****************************************************************************/ 394 // Structures used by AdjustMemoryControllerTable 395 /****************************************************************************/ 396 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 397 { 398 #if ATOM_BIG_ENDIAN 399 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 400 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 401 ULONG ulClockFreq:24; 402 #else 403 ULONG ulClockFreq:24; 404 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 405 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 406 #endif 407 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 408 #define POINTER_RETURN_FLAG 0x80 409 410 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 411 { 412 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 413 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 414 UCHAR ucReserved; //may expand to return larger Fbdiv later 415 UCHAR ucFbDiv; //return value 416 UCHAR ucPostDiv; //return value 417 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 418 419 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 420 { 421 ULONG ulClock; //When return, [23:0] return real clock 422 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 423 USHORT usFbDiv; //return Feedback value to be written to register 424 UCHAR ucPostDiv; //return post div to be written to register 425 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 426 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 427 428 429 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 430 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 431 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 432 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 433 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 434 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 435 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 436 437 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 438 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 439 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 440 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 441 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 442 443 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 444 { 445 #if ATOM_BIG_ENDIAN 446 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 447 ULONG ulClockFreq:24; // in unit of 10kHz 448 #else 449 ULONG ulClockFreq:24; // in unit of 10kHz 450 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 451 #endif 452 }ATOM_COMPUTE_CLOCK_FREQ; 453 454 typedef struct _ATOM_S_MPLL_FB_DIVIDER 455 { 456 USHORT usFbDivFrac; 457 USHORT usFbDiv; 458 }ATOM_S_MPLL_FB_DIVIDER; 459 460 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 461 { 462 union 463 { 464 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 465 ULONG ulClockParams; //ULONG access for BE 466 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 467 }; 468 UCHAR ucRefDiv; //Output Parameter 469 UCHAR ucPostDiv; //Output Parameter 470 UCHAR ucCntlFlag; //Output Parameter 471 UCHAR ucReserved; 472 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 473 474 // ucCntlFlag 475 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 476 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 477 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 478 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 479 480 481 // V4 are only used for APU which PLL outside GPU 482 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 483 { 484 #if ATOM_BIG_ENDIAN 485 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 486 ULONG ulClock:24; //Input= target clock, output = actual clock 487 #else 488 ULONG ulClock:24; //Input= target clock, output = actual clock 489 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 490 #endif 491 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 492 493 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 494 { 495 union 496 { 497 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 498 ULONG ulClockParams; //ULONG access for BE 499 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 500 }; 501 UCHAR ucRefDiv; //Output Parameter 502 UCHAR ucPostDiv; //Output Parameter 503 union 504 { 505 UCHAR ucCntlFlag; //Output Flags 506 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 507 }; 508 UCHAR ucReserved; 509 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 510 511 512 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 513 { 514 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 515 ULONG ulReserved[2]; 516 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 517 518 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 519 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 520 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 521 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 522 523 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 524 { 525 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 526 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 527 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 528 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 529 UCHAR ucPllCntlFlag; //Output Flags: control flag 530 UCHAR ucReserved; 531 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 532 533 //ucPllCntlFlag 534 #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 535 536 537 // ucInputFlag 538 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 539 540 // use for ComputeMemoryClockParamTable 541 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 542 { 543 union 544 { 545 ULONG ulClock; 546 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 547 }; 548 UCHAR ucDllSpeed; //Output 549 UCHAR ucPostDiv; //Output 550 union{ 551 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 552 UCHAR ucPllCntlFlag; //Output: 553 }; 554 UCHAR ucBWCntl; 555 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 556 557 // definition of ucInputFlag 558 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 559 // definition of ucPllCntlFlag 560 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 561 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 562 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 563 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 564 565 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 566 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 567 568 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 569 { 570 ATOM_COMPUTE_CLOCK_FREQ ulClock; 571 ULONG ulReserved[2]; 572 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 573 574 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 575 { 576 ATOM_COMPUTE_CLOCK_FREQ ulClock; 577 ULONG ulMemoryClock; 578 ULONG ulReserved; 579 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 580 581 /****************************************************************************/ 582 // Structures used by SetEngineClockTable 583 /****************************************************************************/ 584 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 585 { 586 ULONG ulTargetEngineClock; //In 10Khz unit 587 }SET_ENGINE_CLOCK_PARAMETERS; 588 589 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 590 { 591 ULONG ulTargetEngineClock; //In 10Khz unit 592 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 593 }SET_ENGINE_CLOCK_PS_ALLOCATION; 594 595 /****************************************************************************/ 596 // Structures used by SetMemoryClockTable 597 /****************************************************************************/ 598 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 599 { 600 ULONG ulTargetMemoryClock; //In 10Khz unit 601 }SET_MEMORY_CLOCK_PARAMETERS; 602 603 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 604 { 605 ULONG ulTargetMemoryClock; //In 10Khz unit 606 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 607 }SET_MEMORY_CLOCK_PS_ALLOCATION; 608 609 /****************************************************************************/ 610 // Structures used by ASIC_Init.ctb 611 /****************************************************************************/ 612 typedef struct _ASIC_INIT_PARAMETERS 613 { 614 ULONG ulDefaultEngineClock; //In 10Khz unit 615 ULONG ulDefaultMemoryClock; //In 10Khz unit 616 }ASIC_INIT_PARAMETERS; 617 618 typedef struct _ASIC_INIT_PS_ALLOCATION 619 { 620 ASIC_INIT_PARAMETERS sASICInitClocks; 621 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 622 }ASIC_INIT_PS_ALLOCATION; 623 624 /****************************************************************************/ 625 // Structure used by DynamicClockGatingTable.ctb 626 /****************************************************************************/ 627 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 628 { 629 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 630 UCHAR ucPadding[3]; 631 }DYNAMIC_CLOCK_GATING_PARAMETERS; 632 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 633 634 /****************************************************************************/ 635 // Structure used by EnableDispPowerGatingTable.ctb 636 /****************************************************************************/ 637 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 638 { 639 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 640 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 641 UCHAR ucPadding[2]; 642 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 643 644 /****************************************************************************/ 645 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 646 /****************************************************************************/ 647 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 648 { 649 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 650 UCHAR ucPadding[3]; 651 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 652 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 653 654 /****************************************************************************/ 655 // Structures used by DAC_LoadDetectionTable.ctb 656 /****************************************************************************/ 657 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 658 { 659 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 660 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 661 UCHAR ucMisc; //Valid only when table revision =1.3 and above 662 }DAC_LOAD_DETECTION_PARAMETERS; 663 664 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 665 #define DAC_LOAD_MISC_YPrPb 0x01 666 667 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 668 { 669 DAC_LOAD_DETECTION_PARAMETERS sDacload; 670 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 671 }DAC_LOAD_DETECTION_PS_ALLOCATION; 672 673 /****************************************************************************/ 674 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 675 /****************************************************************************/ 676 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 677 { 678 USHORT usPixelClock; // in 10KHz; for bios convenient 679 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 680 UCHAR ucAction; // 0: turn off encoder 681 // 1: setup and turn on encoder 682 // 7: ATOM_ENCODER_INIT Initialize DAC 683 }DAC_ENCODER_CONTROL_PARAMETERS; 684 685 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 686 687 /****************************************************************************/ 688 // Structures used by DIG1EncoderControlTable 689 // DIG2EncoderControlTable 690 // ExternalEncoderControlTable 691 /****************************************************************************/ 692 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 693 { 694 USHORT usPixelClock; // in 10KHz; for bios convenient 695 UCHAR ucConfig; 696 // [2] Link Select: 697 // =0: PHY linkA if bfLane<3 698 // =1: PHY linkB if bfLanes<3 699 // =0: PHY linkA+B if bfLanes=3 700 // [3] Transmitter Sel 701 // =0: UNIPHY or PCIEPHY 702 // =1: LVTMA 703 UCHAR ucAction; // =0: turn off encoder 704 // =1: turn on encoder 705 UCHAR ucEncoderMode; 706 // =0: DP encoder 707 // =1: LVDS encoder 708 // =2: DVI encoder 709 // =3: HDMI encoder 710 // =4: SDVO encoder 711 UCHAR ucLaneNum; // how many lanes to enable 712 UCHAR ucReserved[2]; 713 }DIG_ENCODER_CONTROL_PARAMETERS; 714 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 715 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 716 717 //ucConfig 718 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 719 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 720 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 721 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 722 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 723 #define ATOM_ENCODER_CONFIG_LINKA 0x00 724 #define ATOM_ENCODER_CONFIG_LINKB 0x04 725 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 726 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 727 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 728 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 729 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 730 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 731 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 732 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 733 // ucAction 734 // ATOM_ENABLE: Enable Encoder 735 // ATOM_DISABLE: Disable Encoder 736 737 //ucEncoderMode 738 #define ATOM_ENCODER_MODE_DP 0 739 #define ATOM_ENCODER_MODE_LVDS 1 740 #define ATOM_ENCODER_MODE_DVI 2 741 #define ATOM_ENCODER_MODE_HDMI 3 742 #define ATOM_ENCODER_MODE_SDVO 4 743 #define ATOM_ENCODER_MODE_DP_AUDIO 5 744 #define ATOM_ENCODER_MODE_TV 13 745 #define ATOM_ENCODER_MODE_CV 14 746 #define ATOM_ENCODER_MODE_CRT 15 747 #define ATOM_ENCODER_MODE_DVO 16 748 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 749 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 750 751 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 752 { 753 #if ATOM_BIG_ENDIAN 754 UCHAR ucReserved1:2; 755 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 756 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 757 UCHAR ucReserved:1; 758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 759 #else 760 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 761 UCHAR ucReserved:1; 762 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 763 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 764 UCHAR ucReserved1:2; 765 #endif 766 }ATOM_DIG_ENCODER_CONFIG_V2; 767 768 769 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 770 { 771 USHORT usPixelClock; // in 10KHz; for bios convenient 772 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 773 UCHAR ucAction; 774 UCHAR ucEncoderMode; 775 // =0: DP encoder 776 // =1: LVDS encoder 777 // =2: DVI encoder 778 // =3: HDMI encoder 779 // =4: SDVO encoder 780 UCHAR ucLaneNum; // how many lanes to enable 781 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 782 UCHAR ucReserved; 783 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 784 785 //ucConfig 786 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 787 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 788 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 789 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 790 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 791 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 792 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 793 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 794 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 795 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 796 797 // ucAction: 798 // ATOM_DISABLE 799 // ATOM_ENABLE 800 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 801 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 802 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 803 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 804 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 805 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 806 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 807 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 808 #define ATOM_ENCODER_CMD_SETUP 0x0f 809 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 810 811 // ucStatus 812 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 813 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 814 815 //ucTableFormatRevision=1 816 //ucTableContentRevision=3 817 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 818 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 819 { 820 #if ATOM_BIG_ENDIAN 821 UCHAR ucReserved1:1; 822 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 823 UCHAR ucReserved:3; 824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 825 #else 826 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 827 UCHAR ucReserved:3; 828 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 829 UCHAR ucReserved1:1; 830 #endif 831 }ATOM_DIG_ENCODER_CONFIG_V3; 832 833 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 834 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 835 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 836 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 837 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 838 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 839 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 840 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 841 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 842 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 843 844 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 845 { 846 USHORT usPixelClock; // in 10KHz; for bios convenient 847 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 848 UCHAR ucAction; 849 union { 850 UCHAR ucEncoderMode; 851 // =0: DP encoder 852 // =1: LVDS encoder 853 // =2: DVI encoder 854 // =3: HDMI encoder 855 // =4: SDVO encoder 856 // =5: DP audio 857 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 858 // =0: external DP 859 // =1: internal DP2 860 // =0x11: internal DP1 for NutMeg/Travis DP translator 861 }; 862 UCHAR ucLaneNum; // how many lanes to enable 863 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 864 UCHAR ucReserved; 865 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 866 867 //ucTableFormatRevision=1 868 //ucTableContentRevision=4 869 // start from NI 870 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 871 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 872 { 873 #if ATOM_BIG_ENDIAN 874 UCHAR ucReserved1:1; 875 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 876 UCHAR ucReserved:2; 877 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 878 #else 879 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 880 UCHAR ucReserved:2; 881 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 882 UCHAR ucReserved1:1; 883 #endif 884 }ATOM_DIG_ENCODER_CONFIG_V4; 885 886 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 887 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 888 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 889 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 890 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 891 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 892 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 893 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 894 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 895 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 896 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 897 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 898 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 899 900 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 901 { 902 USHORT usPixelClock; // in 10KHz; for bios convenient 903 union{ 904 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 905 UCHAR ucConfig; 906 }; 907 UCHAR ucAction; 908 union { 909 UCHAR ucEncoderMode; 910 // =0: DP encoder 911 // =1: LVDS encoder 912 // =2: DVI encoder 913 // =3: HDMI encoder 914 // =4: SDVO encoder 915 // =5: DP audio 916 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 917 // =0: external DP 918 // =1: internal DP2 919 // =0x11: internal DP1 for NutMeg/Travis DP translator 920 }; 921 UCHAR ucLaneNum; // how many lanes to enable 922 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 923 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 924 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 925 926 // define ucBitPerColor: 927 #define PANEL_BPC_UNDEFINE 0x00 928 #define PANEL_6BIT_PER_COLOR 0x01 929 #define PANEL_8BIT_PER_COLOR 0x02 930 #define PANEL_10BIT_PER_COLOR 0x03 931 #define PANEL_12BIT_PER_COLOR 0x04 932 #define PANEL_16BIT_PER_COLOR 0x05 933 934 //define ucPanelMode 935 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 936 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 937 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 938 939 /****************************************************************************/ 940 // Structures used by UNIPHYTransmitterControlTable 941 // LVTMATransmitterControlTable 942 // DVOOutputControlTable 943 /****************************************************************************/ 944 typedef struct _ATOM_DP_VS_MODE 945 { 946 UCHAR ucLaneSel; 947 UCHAR ucLaneSet; 948 }ATOM_DP_VS_MODE; 949 950 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 951 { 952 union 953 { 954 USHORT usPixelClock; // in 10KHz; for bios convenient 955 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 956 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 957 }; 958 UCHAR ucConfig; 959 // [0]=0: 4 lane Link, 960 // =1: 8 lane Link ( Dual Links TMDS ) 961 // [1]=0: InCoherent mode 962 // =1: Coherent Mode 963 // [2] Link Select: 964 // =0: PHY linkA if bfLane<3 965 // =1: PHY linkB if bfLanes<3 966 // =0: PHY linkA+B if bfLanes=3 967 // [5:4]PCIE lane Sel 968 // =0: lane 0~3 or 0~7 969 // =1: lane 4~7 970 // =2: lane 8~11 or 8~15 971 // =3: lane 12~15 972 UCHAR ucAction; // =0: turn off encoder 973 // =1: turn on encoder 974 UCHAR ucReserved[4]; 975 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 976 977 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 978 979 //ucInitInfo 980 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 981 982 //ucConfig 983 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 984 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 985 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 986 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 987 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 988 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 989 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 990 991 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 992 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 993 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 994 995 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 996 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 997 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 998 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 999 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1000 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1001 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1002 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1003 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1004 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1005 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1006 1007 //ucAction 1008 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 1009 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 1010 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1011 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1012 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1013 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1014 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1015 #define ATOM_TRANSMITTER_ACTION_INIT 7 1016 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1017 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1018 #define ATOM_TRANSMITTER_ACTION_SETUP 10 1019 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1020 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1021 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1022 1023 // Following are used for DigTransmitterControlTable ver1.2 1024 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1025 { 1026 #if ATOM_BIG_ENDIAN 1027 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1028 // =1 Dig Transmitter 2 ( Uniphy CD ) 1029 // =2 Dig Transmitter 3 ( Uniphy EF ) 1030 UCHAR ucReserved:1; 1031 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1032 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1033 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1034 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1035 1036 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1038 #else 1039 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1040 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1041 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1042 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1043 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1044 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1045 UCHAR ucReserved:1; 1046 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1047 // =1 Dig Transmitter 2 ( Uniphy CD ) 1048 // =2 Dig Transmitter 3 ( Uniphy EF ) 1049 #endif 1050 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1051 1052 //ucConfig 1053 //Bit0 1054 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1055 1056 //Bit1 1057 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1058 1059 //Bit2 1060 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1061 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1062 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1063 1064 // Bit3 1065 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1066 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1067 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1068 1069 // Bit4 1070 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1071 1072 // Bit7:6 1073 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1074 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1075 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1076 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1077 1078 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1079 { 1080 union 1081 { 1082 USHORT usPixelClock; // in 10KHz; for bios convenient 1083 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1084 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1085 }; 1086 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1087 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1088 UCHAR ucReserved[4]; 1089 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1090 1091 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1092 { 1093 #if ATOM_BIG_ENDIAN 1094 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1095 // =1 Dig Transmitter 2 ( Uniphy CD ) 1096 // =2 Dig Transmitter 3 ( Uniphy EF ) 1097 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1098 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1099 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1100 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1101 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1103 #else 1104 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1105 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1106 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1107 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1108 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1109 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1110 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1111 // =1 Dig Transmitter 2 ( Uniphy CD ) 1112 // =2 Dig Transmitter 3 ( Uniphy EF ) 1113 #endif 1114 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1115 1116 1117 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1118 { 1119 union 1120 { 1121 USHORT usPixelClock; // in 10KHz; for bios convenient 1122 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1123 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1124 }; 1125 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1126 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1127 UCHAR ucLaneNum; 1128 UCHAR ucReserved[3]; 1129 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1130 1131 //ucConfig 1132 //Bit0 1133 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1134 1135 //Bit1 1136 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1137 1138 //Bit2 1139 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1140 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1141 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1142 1143 // Bit3 1144 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1145 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1146 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1147 1148 // Bit5:4 1149 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1150 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1151 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1152 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1153 1154 // Bit7:6 1155 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1156 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1157 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1158 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1159 1160 1161 /****************************************************************************/ 1162 // Structures used by UNIPHYTransmitterControlTable V1.4 1163 // ASIC Families: NI 1164 // ucTableFormatRevision=1 1165 // ucTableContentRevision=4 1166 /****************************************************************************/ 1167 typedef struct _ATOM_DP_VS_MODE_V4 1168 { 1169 UCHAR ucLaneSel; 1170 union 1171 { 1172 UCHAR ucLaneSet; 1173 struct { 1174 #if ATOM_BIG_ENDIAN 1175 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1176 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1178 #else 1179 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1180 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1181 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1182 #endif 1183 }; 1184 }; 1185 }ATOM_DP_VS_MODE_V4; 1186 1187 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1188 { 1189 #if ATOM_BIG_ENDIAN 1190 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1191 // =1 Dig Transmitter 2 ( Uniphy CD ) 1192 // =2 Dig Transmitter 3 ( Uniphy EF ) 1193 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1194 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1195 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1196 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1197 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1199 #else 1200 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1201 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1202 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1203 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1204 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1205 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1206 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1207 // =1 Dig Transmitter 2 ( Uniphy CD ) 1208 // =2 Dig Transmitter 3 ( Uniphy EF ) 1209 #endif 1210 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1211 1212 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1213 { 1214 union 1215 { 1216 USHORT usPixelClock; // in 10KHz; for bios convenient 1217 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1218 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1219 }; 1220 union 1221 { 1222 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1223 UCHAR ucConfig; 1224 }; 1225 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1226 UCHAR ucLaneNum; 1227 UCHAR ucReserved[3]; 1228 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1229 1230 //ucConfig 1231 //Bit0 1232 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1233 //Bit1 1234 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1235 //Bit2 1236 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1237 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1238 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1239 // Bit3 1240 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1241 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1242 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1243 // Bit5:4 1244 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1245 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1246 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1247 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1248 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1249 // Bit7:6 1250 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1251 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1252 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1253 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1254 1255 1256 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1257 { 1258 #if ATOM_BIG_ENDIAN 1259 UCHAR ucReservd1:1; 1260 UCHAR ucHPDSel:3; 1261 UCHAR ucPhyClkSrcId:2; 1262 UCHAR ucCoherentMode:1; 1263 UCHAR ucReserved:1; 1264 #else 1265 UCHAR ucReserved:1; 1266 UCHAR ucCoherentMode:1; 1267 UCHAR ucPhyClkSrcId:2; 1268 UCHAR ucHPDSel:3; 1269 UCHAR ucReservd1:1; 1270 #endif 1271 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1272 1273 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1274 { 1275 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1276 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1277 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1278 UCHAR ucLaneNum; // indicate lane number 1-8 1279 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1280 UCHAR ucDigMode; // indicate DIG mode 1281 union{ 1282 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1283 UCHAR ucConfig; 1284 }; 1285 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1286 UCHAR ucDPLaneSet; 1287 UCHAR ucReserved; 1288 UCHAR ucReserved1; 1289 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1290 1291 //ucPhyId 1292 #define ATOM_PHY_ID_UNIPHYA 0 1293 #define ATOM_PHY_ID_UNIPHYB 1 1294 #define ATOM_PHY_ID_UNIPHYC 2 1295 #define ATOM_PHY_ID_UNIPHYD 3 1296 #define ATOM_PHY_ID_UNIPHYE 4 1297 #define ATOM_PHY_ID_UNIPHYF 5 1298 #define ATOM_PHY_ID_UNIPHYG 6 1299 1300 // ucDigEncoderSel 1301 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1302 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1303 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1304 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1305 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1306 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1307 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1308 1309 // ucDigMode 1310 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1311 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1312 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1313 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1314 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1315 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1316 1317 // ucDPLaneSet 1318 #define DP_LANE_SET__0DB_0_4V 0x00 1319 #define DP_LANE_SET__0DB_0_6V 0x01 1320 #define DP_LANE_SET__0DB_0_8V 0x02 1321 #define DP_LANE_SET__0DB_1_2V 0x03 1322 #define DP_LANE_SET__3_5DB_0_4V 0x08 1323 #define DP_LANE_SET__3_5DB_0_6V 0x09 1324 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1325 #define DP_LANE_SET__6DB_0_4V 0x10 1326 #define DP_LANE_SET__6DB_0_6V 0x11 1327 #define DP_LANE_SET__9_5DB_0_4V 0x18 1328 1329 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1330 // Bit1 1331 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1332 1333 // Bit3:2 1334 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1335 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1336 1337 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1338 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1339 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1340 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1341 // Bit6:4 1342 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1343 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1344 1345 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1346 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1347 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1348 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1349 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1350 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1351 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1352 1353 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1354 1355 1356 /****************************************************************************/ 1357 // Structures used by ExternalEncoderControlTable V1.3 1358 // ASIC Families: Evergreen, Llano, NI 1359 // ucTableFormatRevision=1 1360 // ucTableContentRevision=3 1361 /****************************************************************************/ 1362 1363 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1364 { 1365 union{ 1366 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1367 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1368 }; 1369 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1370 UCHAR ucAction; // 1371 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1372 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1373 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1374 UCHAR ucReserved; 1375 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1376 1377 // ucAction 1378 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1379 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1380 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1381 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1382 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1383 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1384 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1385 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1386 1387 // ucConfig 1388 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1389 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1390 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1391 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1392 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1393 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1394 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1395 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1396 1397 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1398 { 1399 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1400 ULONG ulReserved[2]; 1401 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1402 1403 1404 /****************************************************************************/ 1405 // Structures used by DAC1OuputControlTable 1406 // DAC2OuputControlTable 1407 // LVTMAOutputControlTable (Before DEC30) 1408 // TMDSAOutputControlTable (Before DEC30) 1409 /****************************************************************************/ 1410 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1411 { 1412 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1413 // When the display is LCD, in addition to above: 1414 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1415 // ATOM_LCD_SELFTEST_STOP 1416 1417 UCHAR aucPadding[3]; // padding to DWORD aligned 1418 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1419 1420 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1421 1422 1423 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1424 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1425 1426 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1427 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1428 1429 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1430 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1431 1432 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1433 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1434 1435 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1436 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1437 1438 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1439 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1440 1441 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1442 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1443 1444 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1445 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1446 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1447 1448 /****************************************************************************/ 1449 // Structures used by BlankCRTCTable 1450 /****************************************************************************/ 1451 typedef struct _BLANK_CRTC_PARAMETERS 1452 { 1453 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1454 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1455 USHORT usBlackColorRCr; 1456 USHORT usBlackColorGY; 1457 USHORT usBlackColorBCb; 1458 }BLANK_CRTC_PARAMETERS; 1459 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1460 1461 /****************************************************************************/ 1462 // Structures used by EnableCRTCTable 1463 // EnableCRTCMemReqTable 1464 // UpdateCRTC_DoubleBufferRegistersTable 1465 /****************************************************************************/ 1466 typedef struct _ENABLE_CRTC_PARAMETERS 1467 { 1468 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1469 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1470 UCHAR ucPadding[2]; 1471 }ENABLE_CRTC_PARAMETERS; 1472 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1473 1474 /****************************************************************************/ 1475 // Structures used by SetCRTC_OverScanTable 1476 /****************************************************************************/ 1477 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1478 { 1479 USHORT usOverscanRight; // right 1480 USHORT usOverscanLeft; // left 1481 USHORT usOverscanBottom; // bottom 1482 USHORT usOverscanTop; // top 1483 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1484 UCHAR ucPadding[3]; 1485 }SET_CRTC_OVERSCAN_PARAMETERS; 1486 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1487 1488 /****************************************************************************/ 1489 // Structures used by SetCRTC_ReplicationTable 1490 /****************************************************************************/ 1491 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1492 { 1493 UCHAR ucH_Replication; // horizontal replication 1494 UCHAR ucV_Replication; // vertical replication 1495 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1496 UCHAR ucPadding; 1497 }SET_CRTC_REPLICATION_PARAMETERS; 1498 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1499 1500 /****************************************************************************/ 1501 // Structures used by SelectCRTC_SourceTable 1502 /****************************************************************************/ 1503 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1504 { 1505 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1506 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1507 UCHAR ucPadding[2]; 1508 }SELECT_CRTC_SOURCE_PARAMETERS; 1509 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1510 1511 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1512 { 1513 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1514 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1515 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1516 UCHAR ucPadding; 1517 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1518 1519 //ucEncoderID 1520 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1521 //#define ASIC_INT_TV_ENCODER_ID 0x02 1522 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1523 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1524 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1525 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1526 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1527 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1528 1529 //ucEncodeMode 1530 //#define ATOM_ENCODER_MODE_DP 0 1531 //#define ATOM_ENCODER_MODE_LVDS 1 1532 //#define ATOM_ENCODER_MODE_DVI 2 1533 //#define ATOM_ENCODER_MODE_HDMI 3 1534 //#define ATOM_ENCODER_MODE_SDVO 4 1535 //#define ATOM_ENCODER_MODE_TV 13 1536 //#define ATOM_ENCODER_MODE_CV 14 1537 //#define ATOM_ENCODER_MODE_CRT 15 1538 1539 /****************************************************************************/ 1540 // Structures used by SetPixelClockTable 1541 // GetPixelClockTable 1542 /****************************************************************************/ 1543 //Major revision=1., Minor revision=1 1544 typedef struct _PIXEL_CLOCK_PARAMETERS 1545 { 1546 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1547 // 0 means disable PPLL 1548 USHORT usRefDiv; // Reference divider 1549 USHORT usFbDiv; // feedback divider 1550 UCHAR ucPostDiv; // post divider 1551 UCHAR ucFracFbDiv; // fractional feedback divider 1552 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1553 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1554 UCHAR ucCRTC; // Which CRTC uses this Ppll 1555 UCHAR ucPadding; 1556 }PIXEL_CLOCK_PARAMETERS; 1557 1558 //Major revision=1., Minor revision=2, add ucMiscIfno 1559 //ucMiscInfo: 1560 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1561 #define MISC_DEVICE_INDEX_MASK 0xF0 1562 #define MISC_DEVICE_INDEX_SHIFT 4 1563 1564 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1565 { 1566 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1567 // 0 means disable PPLL 1568 USHORT usRefDiv; // Reference divider 1569 USHORT usFbDiv; // feedback divider 1570 UCHAR ucPostDiv; // post divider 1571 UCHAR ucFracFbDiv; // fractional feedback divider 1572 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1573 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1574 UCHAR ucCRTC; // Which CRTC uses this Ppll 1575 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1576 }PIXEL_CLOCK_PARAMETERS_V2; 1577 1578 //Major revision=1., Minor revision=3, structure/definition change 1579 //ucEncoderMode: 1580 //ATOM_ENCODER_MODE_DP 1581 //ATOM_ENOCDER_MODE_LVDS 1582 //ATOM_ENOCDER_MODE_DVI 1583 //ATOM_ENOCDER_MODE_HDMI 1584 //ATOM_ENOCDER_MODE_SDVO 1585 //ATOM_ENCODER_MODE_TV 13 1586 //ATOM_ENCODER_MODE_CV 14 1587 //ATOM_ENCODER_MODE_CRT 15 1588 1589 //ucDVOConfig 1590 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1591 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1592 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1593 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1594 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1595 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1596 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1597 1598 //ucMiscInfo: also changed, see below 1599 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1600 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1601 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1602 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1603 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1604 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1605 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1606 // V1.4 for RoadRunner 1607 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1608 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1609 1610 1611 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1612 { 1613 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1614 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1615 USHORT usRefDiv; // Reference divider 1616 USHORT usFbDiv; // feedback divider 1617 UCHAR ucPostDiv; // post divider 1618 UCHAR ucFracFbDiv; // fractional feedback divider 1619 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1620 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1621 union 1622 { 1623 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1624 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1625 }; 1626 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1627 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1628 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1629 }PIXEL_CLOCK_PARAMETERS_V3; 1630 1631 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1632 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1633 1634 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1635 { 1636 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1637 // drive the pixel clock. not used for DCPLL case. 1638 union{ 1639 UCHAR ucReserved; 1640 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1641 }; 1642 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1643 // 0 means disable PPLL/DCPLL. 1644 USHORT usFbDiv; // feedback divider integer part. 1645 UCHAR ucPostDiv; // post divider. 1646 UCHAR ucRefDiv; // Reference divider 1647 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1648 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1649 // indicate which graphic encoder will be used. 1650 UCHAR ucEncoderMode; // Encoder mode: 1651 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1652 // bit[1]= when VGA timing is used. 1653 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1654 // bit[4]= RefClock source for PPLL. 1655 // =0: XTLAIN( default mode ) 1656 // =1: other external clock source, which is pre-defined 1657 // by VBIOS depend on the feature required. 1658 // bit[7:5]: reserved. 1659 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1660 1661 }PIXEL_CLOCK_PARAMETERS_V5; 1662 1663 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1664 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1665 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1666 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1667 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1668 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1669 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1670 1671 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1672 { 1673 #if ATOM_BIG_ENDIAN 1674 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1675 // drive the pixel clock. not used for DCPLL case. 1676 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1677 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1678 #else 1679 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1680 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1681 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1682 // drive the pixel clock. not used for DCPLL case. 1683 #endif 1684 }CRTC_PIXEL_CLOCK_FREQ; 1685 1686 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1687 { 1688 union{ 1689 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1690 ULONG ulDispEngClkFreq; // dispclk frequency 1691 }; 1692 USHORT usFbDiv; // feedback divider integer part. 1693 UCHAR ucPostDiv; // post divider. 1694 UCHAR ucRefDiv; // Reference divider 1695 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1696 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1697 // indicate which graphic encoder will be used. 1698 UCHAR ucEncoderMode; // Encoder mode: 1699 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1700 // bit[1]= when VGA timing is used. 1701 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1702 // bit[4]= RefClock source for PPLL. 1703 // =0: XTLAIN( default mode ) 1704 // =1: other external clock source, which is pre-defined 1705 // by VBIOS depend on the feature required. 1706 // bit[7:5]: reserved. 1707 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1708 1709 }PIXEL_CLOCK_PARAMETERS_V6; 1710 1711 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1712 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1713 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1714 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1715 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1716 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1717 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1718 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1719 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1720 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1721 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1722 1723 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1724 { 1725 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1726 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1727 1728 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1729 { 1730 UCHAR ucStatus; 1731 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1732 UCHAR ucReserved[2]; 1733 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1734 1735 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1736 { 1737 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1738 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1739 1740 /****************************************************************************/ 1741 // Structures used by AdjustDisplayPllTable 1742 /****************************************************************************/ 1743 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1744 { 1745 USHORT usPixelClock; 1746 UCHAR ucTransmitterID; 1747 UCHAR ucEncodeMode; 1748 union 1749 { 1750 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1751 UCHAR ucConfig; //if none DVO, not defined yet 1752 }; 1753 UCHAR ucReserved[3]; 1754 }ADJUST_DISPLAY_PLL_PARAMETERS; 1755 1756 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1757 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1758 1759 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1760 { 1761 USHORT usPixelClock; // target pixel clock 1762 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1763 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1764 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1765 UCHAR ucExtTransmitterID; // external encoder id. 1766 UCHAR ucReserved[2]; 1767 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1768 1769 // usDispPllConfig v1.2 for RoadRunner 1770 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1771 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1772 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1773 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1774 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1775 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1776 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1777 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1778 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1779 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1780 1781 1782 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1783 { 1784 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1785 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1786 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1787 UCHAR ucReserved[2]; 1788 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1789 1790 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1791 { 1792 union 1793 { 1794 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1795 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1796 }; 1797 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1798 1799 /****************************************************************************/ 1800 // Structures used by EnableYUVTable 1801 /****************************************************************************/ 1802 typedef struct _ENABLE_YUV_PARAMETERS 1803 { 1804 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1805 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1806 UCHAR ucPadding[2]; 1807 }ENABLE_YUV_PARAMETERS; 1808 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1809 1810 /****************************************************************************/ 1811 // Structures used by GetMemoryClockTable 1812 /****************************************************************************/ 1813 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1814 { 1815 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1816 } GET_MEMORY_CLOCK_PARAMETERS; 1817 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1818 1819 /****************************************************************************/ 1820 // Structures used by GetEngineClockTable 1821 /****************************************************************************/ 1822 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1823 { 1824 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1825 } GET_ENGINE_CLOCK_PARAMETERS; 1826 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1827 1828 /****************************************************************************/ 1829 // Following Structures and constant may be obsolete 1830 /****************************************************************************/ 1831 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1832 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1833 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1834 { 1835 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1836 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1837 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1838 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1839 UCHAR ucSlaveAddr; //Read from which slave 1840 UCHAR ucLineNumber; //Read from which HW assisted line 1841 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1842 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1843 1844 1845 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1846 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1847 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1848 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1849 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1850 1851 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1852 { 1853 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1854 USHORT usByteOffset; //Write to which byte 1855 //Upper portion of usByteOffset is Format of data 1856 //1bytePS+offsetPS 1857 //2bytesPS+offsetPS 1858 //blockID+offsetPS 1859 //blockID+offsetID 1860 //blockID+counterID+offsetID 1861 UCHAR ucData; //PS data1 1862 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1863 UCHAR ucSlaveAddr; //Write to which slave 1864 UCHAR ucLineNumber; //Write from which HW assisted line 1865 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1866 1867 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1868 1869 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1870 { 1871 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1872 UCHAR ucSlaveAddr; //Write to which slave 1873 UCHAR ucLineNumber; //Write from which HW assisted line 1874 }SET_UP_HW_I2C_DATA_PARAMETERS; 1875 1876 1877 /**************************************************************************/ 1878 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1879 1880 1881 /****************************************************************************/ 1882 // Structures used by PowerConnectorDetectionTable 1883 /****************************************************************************/ 1884 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1885 { 1886 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1887 UCHAR ucPwrBehaviorId; 1888 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1889 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1890 1891 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1892 { 1893 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1894 UCHAR ucReserved; 1895 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1896 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1897 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1898 1899 /****************************LVDS SS Command Table Definitions**********************/ 1900 1901 /****************************************************************************/ 1902 // Structures used by EnableSpreadSpectrumOnPPLLTable 1903 /****************************************************************************/ 1904 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1905 { 1906 USHORT usSpreadSpectrumPercentage; 1907 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1908 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1909 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1910 UCHAR ucPadding[3]; 1911 }ENABLE_LVDS_SS_PARAMETERS; 1912 1913 //ucTableFormatRevision=1,ucTableContentRevision=2 1914 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1915 { 1916 USHORT usSpreadSpectrumPercentage; 1917 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1918 UCHAR ucSpreadSpectrumStep; // 1919 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1920 UCHAR ucSpreadSpectrumDelay; 1921 UCHAR ucSpreadSpectrumRange; 1922 UCHAR ucPadding; 1923 }ENABLE_LVDS_SS_PARAMETERS_V2; 1924 1925 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1926 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1927 { 1928 USHORT usSpreadSpectrumPercentage; 1929 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1930 UCHAR ucSpreadSpectrumStep; // 1931 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1932 UCHAR ucSpreadSpectrumDelay; 1933 UCHAR ucSpreadSpectrumRange; 1934 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1935 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1936 1937 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1938 { 1939 USHORT usSpreadSpectrumPercentage; 1940 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1941 // Bit[1]: 1-Ext. 0-Int. 1942 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1943 // Bits[7:4] reserved 1944 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1945 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1946 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1947 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1948 1949 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1950 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1951 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1952 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1953 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1954 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1955 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1956 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1957 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1958 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1959 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1960 1961 // Used by DCE5.0 1962 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1963 { 1964 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1965 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1966 // Bit[1]: 1-Ext. 0-Int. 1967 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1968 // Bits[7:4] reserved 1969 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1970 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1971 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1972 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1973 1974 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1975 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1976 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1977 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1978 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1979 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1980 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1981 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1982 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1983 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1984 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1985 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1986 1987 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1988 1989 /**************************************************************************/ 1990 1991 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1992 { 1993 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1994 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1995 }SET_PIXEL_CLOCK_PS_ALLOCATION; 1996 1997 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1998 1999 /****************************************************************************/ 2000 // Structures used by ### 2001 /****************************************************************************/ 2002 typedef struct _MEMORY_TRAINING_PARAMETERS 2003 { 2004 ULONG ulTargetMemoryClock; //In 10Khz unit 2005 }MEMORY_TRAINING_PARAMETERS; 2006 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2007 2008 2009 /****************************LVDS and other encoder command table definitions **********************/ 2010 2011 2012 /****************************************************************************/ 2013 // Structures used by LVDSEncoderControlTable (Before DCE30) 2014 // LVTMAEncoderControlTable (Before DCE30) 2015 // TMDSAEncoderControlTable (Before DCE30) 2016 /****************************************************************************/ 2017 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2018 { 2019 USHORT usPixelClock; // in 10KHz; for bios convenient 2020 UCHAR ucMisc; // bit0=0: Enable single link 2021 // =1: Enable dual link 2022 // Bit1=0: 666RGB 2023 // =1: 888RGB 2024 UCHAR ucAction; // 0: turn off encoder 2025 // 1: setup and turn on encoder 2026 }LVDS_ENCODER_CONTROL_PARAMETERS; 2027 2028 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2029 2030 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2031 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2032 2033 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2034 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2035 2036 2037 //ucTableFormatRevision=1,ucTableContentRevision=2 2038 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2039 { 2040 USHORT usPixelClock; // in 10KHz; for bios convenient 2041 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2042 UCHAR ucAction; // 0: turn off encoder 2043 // 1: setup and turn on encoder 2044 UCHAR ucTruncate; // bit0=0: Disable truncate 2045 // =1: Enable truncate 2046 // bit4=0: 666RGB 2047 // =1: 888RGB 2048 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2049 // =1: Enable spatial dithering 2050 // bit4=0: 666RGB 2051 // =1: 888RGB 2052 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2053 // =1: Enable temporal dithering 2054 // bit4=0: 666RGB 2055 // =1: 888RGB 2056 // bit5=0: Gray level 2 2057 // =1: Gray level 4 2058 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2059 // =1: 25FRC_SEL pattern F 2060 // bit6:5=0: 50FRC_SEL pattern A 2061 // =1: 50FRC_SEL pattern B 2062 // =2: 50FRC_SEL pattern C 2063 // =3: 50FRC_SEL pattern D 2064 // bit7=0: 75FRC_SEL pattern E 2065 // =1: 75FRC_SEL pattern F 2066 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2067 2068 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2069 2070 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2071 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2072 2073 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2074 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2075 2076 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2077 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2078 2079 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2080 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2081 2082 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2083 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2084 2085 /****************************************************************************/ 2086 // Structures used by ### 2087 /****************************************************************************/ 2088 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2089 { 2090 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2091 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2092 UCHAR ucPadding[2]; 2093 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2094 2095 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2096 { 2097 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2098 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2099 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2100 2101 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2102 2103 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2104 { 2105 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2106 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2107 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2108 2109 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2110 { 2111 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2112 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2113 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2114 2115 /****************************************************************************/ 2116 // Structures used by DVOEncoderControlTable 2117 /****************************************************************************/ 2118 //ucTableFormatRevision=1,ucTableContentRevision=3 2119 2120 //ucDVOConfig: 2121 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2122 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2123 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2124 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2125 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2126 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2127 #define DVO_ENCODER_CONFIG_24BIT 0x08 2128 2129 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2130 { 2131 USHORT usPixelClock; 2132 UCHAR ucDVOConfig; 2133 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2134 UCHAR ucReseved[4]; 2135 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2136 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2137 2138 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2139 { 2140 USHORT usPixelClock; 2141 UCHAR ucDVOConfig; 2142 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2143 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2144 UCHAR ucReseved[3]; 2145 }DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2146 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2147 2148 2149 //ucTableFormatRevision=1 2150 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2151 // bit1=0: non-coherent mode 2152 // =1: coherent mode 2153 2154 //========================================================================================== 2155 //Only change is here next time when changing encoder parameter definitions again! 2156 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2157 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2158 2159 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2160 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2161 2162 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2163 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2164 2165 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2166 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2167 2168 //========================================================================================== 2169 #define PANEL_ENCODER_MISC_DUAL 0x01 2170 #define PANEL_ENCODER_MISC_COHERENT 0x02 2171 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2172 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2173 2174 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2175 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2176 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2177 2178 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2179 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2180 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2181 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2182 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2183 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2184 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2185 #define PANEL_ENCODER_25FRC_MASK 0x10 2186 #define PANEL_ENCODER_25FRC_E 0x00 2187 #define PANEL_ENCODER_25FRC_F 0x10 2188 #define PANEL_ENCODER_50FRC_MASK 0x60 2189 #define PANEL_ENCODER_50FRC_A 0x00 2190 #define PANEL_ENCODER_50FRC_B 0x20 2191 #define PANEL_ENCODER_50FRC_C 0x40 2192 #define PANEL_ENCODER_50FRC_D 0x60 2193 #define PANEL_ENCODER_75FRC_MASK 0x80 2194 #define PANEL_ENCODER_75FRC_E 0x00 2195 #define PANEL_ENCODER_75FRC_F 0x80 2196 2197 /****************************************************************************/ 2198 // Structures used by SetVoltageTable 2199 /****************************************************************************/ 2200 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2201 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2202 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2203 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2204 #define SET_VOLTAGE_INIT_MODE 5 2205 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2206 2207 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2208 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2209 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2210 2211 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2212 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2213 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2214 2215 typedef struct _SET_VOLTAGE_PARAMETERS 2216 { 2217 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2218 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2219 UCHAR ucVoltageIndex; // An index to tell which voltage level 2220 UCHAR ucReserved; 2221 }SET_VOLTAGE_PARAMETERS; 2222 2223 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2224 { 2225 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2226 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2227 USHORT usVoltageLevel; // real voltage level 2228 }SET_VOLTAGE_PARAMETERS_V2; 2229 2230 // used by both SetVoltageTable v1.3 and v1.4 2231 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2232 { 2233 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2234 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2235 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2236 }SET_VOLTAGE_PARAMETERS_V1_3; 2237 2238 //ucVoltageType 2239 #define VOLTAGE_TYPE_VDDC 1 2240 #define VOLTAGE_TYPE_MVDDC 2 2241 #define VOLTAGE_TYPE_MVDDQ 3 2242 #define VOLTAGE_TYPE_VDDCI 4 2243 2244 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2245 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2246 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2247 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2248 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2249 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2250 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2251 2252 // define vitual voltage id in usVoltageLevel 2253 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2254 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2255 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2256 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2257 #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2258 #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2259 #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2260 #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2261 2262 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2263 { 2264 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2265 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2266 }SET_VOLTAGE_PS_ALLOCATION; 2267 2268 // New Added from SI for GetVoltageInfoTable, input parameter structure 2269 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2270 { 2271 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2272 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2273 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2274 ULONG ulReserved; 2275 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2276 2277 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2278 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2279 { 2280 ULONG ulVotlageGpioState; 2281 ULONG ulVoltageGPioMask; 2282 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2283 2284 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2285 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2286 { 2287 USHORT usVoltageLevel; 2288 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2289 ULONG ulReseved; 2290 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2291 2292 2293 // GetVoltageInfo v1.1 ucVoltageMode 2294 #define ATOM_GET_VOLTAGE_VID 0x00 2295 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2296 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2297 #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2298 2299 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2300 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2301 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2302 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2303 2304 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2305 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2306 2307 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2308 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2309 { 2310 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2311 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2312 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2313 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2314 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2315 2316 // New in GetVoltageInfo v1.2 ucVoltageMode 2317 #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2318 2319 // New Added from CI Hawaii for EVV feature 2320 typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2321 { 2322 USHORT usVoltageLevel; // real voltage level in unit of mv 2323 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2324 ULONG ulReseved; 2325 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2326 2327 /****************************************************************************/ 2328 // Structures used by TVEncoderControlTable 2329 /****************************************************************************/ 2330 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2331 { 2332 USHORT usPixelClock; // in 10KHz; for bios convenient 2333 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2334 UCHAR ucAction; // 0: turn off encoder 2335 // 1: setup and turn on encoder 2336 }TV_ENCODER_CONTROL_PARAMETERS; 2337 2338 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2339 { 2340 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2341 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2342 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2343 2344 //==============================Data Table Portion==================================== 2345 2346 /****************************************************************************/ 2347 // Structure used in Data.mtb 2348 /****************************************************************************/ 2349 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2350 { 2351 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2352 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2353 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2354 USHORT StandardVESA_Timing; // Only used by Bios 2355 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2356 USHORT PaletteData; // Only used by BIOS 2357 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2358 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2359 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2360 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2361 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2362 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2363 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2364 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2365 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2366 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2367 USHORT CompassionateData; // Will be obsolete from R600 2368 USHORT SaveRestoreInfo; // Only used by Bios 2369 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2370 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2371 USHORT XTMDS_Info; // Will be obsolete from R600 2372 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2373 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2374 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2375 USHORT MC_InitParameter; // Only used by command table 2376 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2377 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2378 USHORT TV_VideoMode; // Only used by command table 2379 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2380 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2381 USHORT IntegratedSystemInfo; // Shared by various SW components 2382 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2383 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2384 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2385 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2386 2387 typedef struct _ATOM_MASTER_DATA_TABLE 2388 { 2389 ATOM_COMMON_TABLE_HEADER sHeader; 2390 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2391 }ATOM_MASTER_DATA_TABLE; 2392 2393 // For backward compatible 2394 #define LVDS_Info LCD_Info 2395 #define DAC_Info PaletteData 2396 #define TMDS_Info DIGTransmitterInfo 2397 2398 /****************************************************************************/ 2399 // Structure used in MultimediaCapabilityInfoTable 2400 /****************************************************************************/ 2401 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2402 { 2403 ATOM_COMMON_TABLE_HEADER sHeader; 2404 ULONG ulSignature; // HW info table signature string "$ATI" 2405 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2406 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2407 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2408 UCHAR ucHostPortInfo; // Provides host port configuration information 2409 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2410 2411 /****************************************************************************/ 2412 // Structure used in MultimediaConfigInfoTable 2413 /****************************************************************************/ 2414 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2415 { 2416 ATOM_COMMON_TABLE_HEADER sHeader; 2417 ULONG ulSignature; // MM info table signature sting "$MMT" 2418 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2419 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2420 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2421 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2422 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2423 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2424 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2425 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2426 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2427 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2428 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2429 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2430 }ATOM_MULTIMEDIA_CONFIG_INFO; 2431 2432 2433 /****************************************************************************/ 2434 // Structures used in FirmwareInfoTable 2435 /****************************************************************************/ 2436 2437 // usBIOSCapability Definition: 2438 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2439 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2440 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2441 // Others: Reserved 2442 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2443 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2444 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2445 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2446 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2447 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2448 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2449 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2450 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2451 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2452 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2453 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2454 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2455 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2456 2457 #ifndef _H2INC 2458 2459 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2460 typedef struct _ATOM_FIRMWARE_CAPABILITY 2461 { 2462 #if ATOM_BIG_ENDIAN 2463 USHORT Reserved:1; 2464 USHORT SCL2Redefined:1; 2465 USHORT PostWithoutModeSet:1; 2466 USHORT HyperMemory_Size:4; 2467 USHORT HyperMemory_Support:1; 2468 USHORT PPMode_Assigned:1; 2469 USHORT WMI_SUPPORT:1; 2470 USHORT GPUControlsBL:1; 2471 USHORT EngineClockSS_Support:1; 2472 USHORT MemoryClockSS_Support:1; 2473 USHORT ExtendedDesktopSupport:1; 2474 USHORT DualCRTC_Support:1; 2475 USHORT FirmwarePosted:1; 2476 #else 2477 USHORT FirmwarePosted:1; 2478 USHORT DualCRTC_Support:1; 2479 USHORT ExtendedDesktopSupport:1; 2480 USHORT MemoryClockSS_Support:1; 2481 USHORT EngineClockSS_Support:1; 2482 USHORT GPUControlsBL:1; 2483 USHORT WMI_SUPPORT:1; 2484 USHORT PPMode_Assigned:1; 2485 USHORT HyperMemory_Support:1; 2486 USHORT HyperMemory_Size:4; 2487 USHORT PostWithoutModeSet:1; 2488 USHORT SCL2Redefined:1; 2489 USHORT Reserved:1; 2490 #endif 2491 }ATOM_FIRMWARE_CAPABILITY; 2492 2493 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2494 { 2495 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2496 USHORT susAccess; 2497 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2498 2499 #else 2500 2501 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2502 { 2503 USHORT susAccess; 2504 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2505 2506 #endif 2507 2508 typedef struct _ATOM_FIRMWARE_INFO 2509 { 2510 ATOM_COMMON_TABLE_HEADER sHeader; 2511 ULONG ulFirmwareRevision; 2512 ULONG ulDefaultEngineClock; //In 10Khz unit 2513 ULONG ulDefaultMemoryClock; //In 10Khz unit 2514 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2515 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2516 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2517 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2518 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2519 ULONG ulASICMaxEngineClock; //In 10Khz unit 2520 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2521 UCHAR ucASICMaxTemperature; 2522 UCHAR ucPadding[3]; //Don't use them 2523 ULONG aulReservedForBIOS[3]; //Don't use them 2524 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2525 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2526 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2527 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2528 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2529 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2530 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2531 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2532 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2533 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2534 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2535 USHORT usReferenceClock; //In 10Khz unit 2536 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2537 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2538 UCHAR ucDesign_ID; //Indicate what is the board design 2539 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2540 }ATOM_FIRMWARE_INFO; 2541 2542 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2543 { 2544 ATOM_COMMON_TABLE_HEADER sHeader; 2545 ULONG ulFirmwareRevision; 2546 ULONG ulDefaultEngineClock; //In 10Khz unit 2547 ULONG ulDefaultMemoryClock; //In 10Khz unit 2548 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2549 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2550 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2551 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2552 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2553 ULONG ulASICMaxEngineClock; //In 10Khz unit 2554 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2555 UCHAR ucASICMaxTemperature; 2556 UCHAR ucMinAllowedBL_Level; 2557 UCHAR ucPadding[2]; //Don't use them 2558 ULONG aulReservedForBIOS[2]; //Don't use them 2559 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2560 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2561 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2562 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2563 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2564 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2565 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2566 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2567 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2568 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2569 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2570 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2571 USHORT usReferenceClock; //In 10Khz unit 2572 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2573 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2574 UCHAR ucDesign_ID; //Indicate what is the board design 2575 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2576 }ATOM_FIRMWARE_INFO_V1_2; 2577 2578 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2579 { 2580 ATOM_COMMON_TABLE_HEADER sHeader; 2581 ULONG ulFirmwareRevision; 2582 ULONG ulDefaultEngineClock; //In 10Khz unit 2583 ULONG ulDefaultMemoryClock; //In 10Khz unit 2584 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2585 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2586 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2587 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2588 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2589 ULONG ulASICMaxEngineClock; //In 10Khz unit 2590 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2591 UCHAR ucASICMaxTemperature; 2592 UCHAR ucMinAllowedBL_Level; 2593 UCHAR ucPadding[2]; //Don't use them 2594 ULONG aulReservedForBIOS; //Don't use them 2595 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2596 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2597 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2598 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2599 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2600 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2601 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2602 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2603 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2604 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2605 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2606 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2607 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2608 USHORT usReferenceClock; //In 10Khz unit 2609 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2610 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2611 UCHAR ucDesign_ID; //Indicate what is the board design 2612 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2613 }ATOM_FIRMWARE_INFO_V1_3; 2614 2615 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2616 { 2617 ATOM_COMMON_TABLE_HEADER sHeader; 2618 ULONG ulFirmwareRevision; 2619 ULONG ulDefaultEngineClock; //In 10Khz unit 2620 ULONG ulDefaultMemoryClock; //In 10Khz unit 2621 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2622 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2623 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2624 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2625 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2626 ULONG ulASICMaxEngineClock; //In 10Khz unit 2627 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2628 UCHAR ucASICMaxTemperature; 2629 UCHAR ucMinAllowedBL_Level; 2630 USHORT usBootUpVDDCVoltage; //In MV unit 2631 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2632 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2633 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2634 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2635 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2636 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2637 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2638 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2639 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2640 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2641 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2642 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2643 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2644 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2645 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2646 USHORT usReferenceClock; //In 10Khz unit 2647 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2648 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2649 UCHAR ucDesign_ID; //Indicate what is the board design 2650 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2651 }ATOM_FIRMWARE_INFO_V1_4; 2652 2653 //the structure below to be used from Cypress 2654 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2655 { 2656 ATOM_COMMON_TABLE_HEADER sHeader; 2657 ULONG ulFirmwareRevision; 2658 ULONG ulDefaultEngineClock; //In 10Khz unit 2659 ULONG ulDefaultMemoryClock; //In 10Khz unit 2660 ULONG ulReserved1; 2661 ULONG ulReserved2; 2662 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2663 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2664 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2665 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2666 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2667 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2668 UCHAR ucMinAllowedBL_Level; 2669 USHORT usBootUpVDDCVoltage; //In MV unit 2670 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2671 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2672 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2673 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2674 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2675 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2676 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2677 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2678 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2679 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2680 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2681 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2682 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2683 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2684 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2685 USHORT usCoreReferenceClock; //In 10Khz unit 2686 USHORT usMemoryReferenceClock; //In 10Khz unit 2687 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2688 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2689 UCHAR ucReserved4[3]; 2690 }ATOM_FIRMWARE_INFO_V2_1; 2691 2692 //the structure below to be used from NI 2693 //ucTableFormatRevision=2 2694 //ucTableContentRevision=2 2695 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2696 { 2697 ATOM_COMMON_TABLE_HEADER sHeader; 2698 ULONG ulFirmwareRevision; 2699 ULONG ulDefaultEngineClock; //In 10Khz unit 2700 ULONG ulDefaultMemoryClock; //In 10Khz unit 2701 ULONG ulSPLL_OutputFreq; //In 10Khz unit 2702 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 2703 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2704 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2705 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2706 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2707 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2708 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2709 UCHAR ucMinAllowedBL_Level; 2710 USHORT usBootUpVDDCVoltage; //In MV unit 2711 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2712 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2713 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2714 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2715 UCHAR ucRemoteDisplayConfig; 2716 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2717 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2718 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2719 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2720 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2721 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2722 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2723 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2724 USHORT usCoreReferenceClock; //In 10Khz unit 2725 USHORT usMemoryReferenceClock; //In 10Khz unit 2726 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2727 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2728 UCHAR ucReserved9[3]; 2729 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2730 USHORT usReserved12; 2731 ULONG ulReserved10[3]; // New added comparing to previous version 2732 }ATOM_FIRMWARE_INFO_V2_2; 2733 2734 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2735 2736 2737 // definition of ucRemoteDisplayConfig 2738 #define REMOTE_DISPLAY_DISABLE 0x00 2739 #define REMOTE_DISPLAY_ENABLE 0x01 2740 2741 /****************************************************************************/ 2742 // Structures used in IntegratedSystemInfoTable 2743 /****************************************************************************/ 2744 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2745 #define IGP_CAP_FLAG_AC_CARD 0x4 2746 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2747 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2748 2749 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2750 { 2751 ATOM_COMMON_TABLE_HEADER sHeader; 2752 ULONG ulBootUpEngineClock; //in 10kHz unit 2753 ULONG ulBootUpMemoryClock; //in 10kHz unit 2754 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2755 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2756 UCHAR ucNumberOfCyclesInPeriodHi; 2757 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2758 USHORT usReserved1; 2759 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2760 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2761 ULONG ulReserved[2]; 2762 2763 USHORT usFSBClock; //In MHz unit 2764 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2765 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2766 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2767 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2768 USHORT usK8MemoryClock; //in MHz unit 2769 USHORT usK8SyncStartDelay; //in 0.01 us unit 2770 USHORT usK8DataReturnTime; //in 0.01 us unit 2771 UCHAR ucMaxNBVoltage; 2772 UCHAR ucMinNBVoltage; 2773 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2774 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2775 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2776 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2777 UCHAR ucMaxNBVoltageHigh; 2778 UCHAR ucMinNBVoltageHigh; 2779 }ATOM_INTEGRATED_SYSTEM_INFO; 2780 2781 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2782 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2783 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2784 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2785 For AMD IGP,for now this can be 0 2786 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2787 For AMD IGP,for now this can be 0 2788 2789 usFSBClock: For Intel IGP,it's FSB Freq 2790 For AMD IGP,it's HT Link Speed 2791 2792 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2793 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2794 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2795 2796 VC:Voltage Control 2797 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2798 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2799 2800 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2801 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2802 2803 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2804 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2805 2806 2807 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2808 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2809 */ 2810 2811 2812 /* 2813 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2814 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2815 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2816 2817 SW components can access the IGP system infor structure in the same way as before 2818 */ 2819 2820 2821 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2822 { 2823 ATOM_COMMON_TABLE_HEADER sHeader; 2824 ULONG ulBootUpEngineClock; //in 10kHz unit 2825 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2826 ULONG ulBootUpUMAClock; //in 10kHz unit 2827 ULONG ulBootUpSidePortClock; //in 10kHz unit 2828 ULONG ulMinSidePortClock; //in 10kHz unit 2829 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2830 ULONG ulSystemConfig; //see explanation below 2831 ULONG ulBootUpReqDisplayVector; 2832 ULONG ulOtherDisplayMisc; 2833 ULONG ulDDISlot1Config; 2834 ULONG ulDDISlot2Config; 2835 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2836 UCHAR ucUMAChannelNumber; 2837 UCHAR ucDockingPinBit; 2838 UCHAR ucDockingPinPolarity; 2839 ULONG ulDockingPinCFGInfo; 2840 ULONG ulCPUCapInfo; 2841 USHORT usNumberOfCyclesInPeriod; 2842 USHORT usMaxNBVoltage; 2843 USHORT usMinNBVoltage; 2844 USHORT usBootUpNBVoltage; 2845 ULONG ulHTLinkFreq; //in 10Khz 2846 USHORT usMinHTLinkWidth; 2847 USHORT usMaxHTLinkWidth; 2848 USHORT usUMASyncStartDelay; 2849 USHORT usUMADataReturnTime; 2850 USHORT usLinkStatusZeroTime; 2851 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2852 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2853 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2854 USHORT usMaxUpStreamHTLinkWidth; 2855 USHORT usMaxDownStreamHTLinkWidth; 2856 USHORT usMinUpStreamHTLinkWidth; 2857 USHORT usMinDownStreamHTLinkWidth; 2858 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2859 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2860 ULONG ulReserved3[96]; //must be 0x0 2861 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2862 2863 /* 2864 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2865 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2866 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2867 2868 ulSystemConfig: 2869 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2870 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2871 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2872 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2873 Bit[3]=1: Only one power state(Performance) will be supported. 2874 =0: Multiple power states supported from PowerPlay table. 2875 Bit[4]=1: CLMC is supported and enabled on current system. 2876 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2877 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2878 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2879 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2880 =0: Voltage settings is determined by powerplay table. 2881 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2882 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2883 Bit[8]=1: CDLF is supported and enabled on current system. 2884 =0: CDLF is not supported or enabled on current system. 2885 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2886 =0: DLL Shut Down feature is not enabled or supported on current system. 2887 2888 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2889 2890 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2891 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2892 2893 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2894 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2895 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2896 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2897 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2898 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2899 2900 [15:8] - Lane configuration attribute; 2901 [23:16]- Connector type, possible value: 2902 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2903 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2904 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2905 CONNECTOR_OBJECT_ID_DISPLAYPORT 2906 CONNECTOR_OBJECT_ID_eDP 2907 [31:24]- Reserved 2908 2909 ulDDISlot2Config: Same as Slot1. 2910 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2911 For IGP, Hypermemory is the only memory type showed in CCC. 2912 2913 ucUMAChannelNumber: how many channels for the UMA; 2914 2915 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2916 ucDockingPinBit: which bit in this register to read the pin status; 2917 ucDockingPinPolarity:Polarity of the pin when docked; 2918 2919 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2920 2921 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2922 2923 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2924 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2925 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2926 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2927 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2928 2929 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2930 2931 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2932 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2933 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2934 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2935 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2936 2937 usUMASyncStartDelay: Memory access latency, required for watermark calculation 2938 usUMADataReturnTime: Memory access latency, required for watermark calculation 2939 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2940 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2941 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2942 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2943 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2944 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2945 2946 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2947 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2948 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2949 This must be less than or equal to ulHighVoltageHTLinkFreq. 2950 2951 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2952 usMaxDownStreamHTLinkWidth: same as above. 2953 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2954 usMinDownStreamHTLinkWidth: same as above. 2955 */ 2956 2957 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2958 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2959 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2960 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2961 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2962 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2963 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2964 2965 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2966 2967 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2968 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2969 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2970 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2971 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2972 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2973 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2974 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2975 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2976 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2977 2978 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2979 2980 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2981 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2982 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2983 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2984 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2985 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2986 2987 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2988 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2989 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2990 2991 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2992 2993 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2994 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2995 { 2996 ATOM_COMMON_TABLE_HEADER sHeader; 2997 ULONG ulBootUpEngineClock; //in 10kHz unit 2998 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2999 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3000 ULONG ulBootUpUMAClock; //in 10kHz unit 3001 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3002 ULONG ulBootUpReqDisplayVector; 3003 ULONG ulOtherDisplayMisc; 3004 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3005 ULONG ulSystemConfig; //TBD 3006 ULONG ulCPUCapInfo; //TBD 3007 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3008 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3009 USHORT usBootUpNBVoltage; //boot up NB voltage 3010 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3011 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3012 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3013 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3014 ULONG ulDDISlot2Config; 3015 ULONG ulDDISlot3Config; 3016 ULONG ulDDISlot4Config; 3017 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3018 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3019 UCHAR ucUMAChannelNumber; 3020 USHORT usReserved; 3021 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3022 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3023 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3024 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3025 ULONG ulReserved6[61]; //must be 0x0 3026 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 3027 3028 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3029 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3030 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3031 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3032 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3033 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3034 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3035 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3036 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3037 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3038 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3039 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3040 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3041 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3042 3043 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3044 #define ASIC_INT_DAC1_ENCODER_ID 0x00 3045 #define ASIC_INT_TV_ENCODER_ID 0x02 3046 #define ASIC_INT_DIG1_ENCODER_ID 0x03 3047 #define ASIC_INT_DAC2_ENCODER_ID 0x04 3048 #define ASIC_EXT_TV_ENCODER_ID 0x06 3049 #define ASIC_INT_DVO_ENCODER_ID 0x07 3050 #define ASIC_INT_DIG2_ENCODER_ID 0x09 3051 #define ASIC_EXT_DIG_ENCODER_ID 0x05 3052 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 3053 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 3054 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 3055 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 3056 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 3057 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 3058 3059 //define Encoder attribute 3060 #define ATOM_ANALOG_ENCODER 0 3061 #define ATOM_DIGITAL_ENCODER 1 3062 #define ATOM_DP_ENCODER 2 3063 3064 #define ATOM_ENCODER_ENUM_MASK 0x70 3065 #define ATOM_ENCODER_ENUM_ID1 0x00 3066 #define ATOM_ENCODER_ENUM_ID2 0x10 3067 #define ATOM_ENCODER_ENUM_ID3 0x20 3068 #define ATOM_ENCODER_ENUM_ID4 0x30 3069 #define ATOM_ENCODER_ENUM_ID5 0x40 3070 #define ATOM_ENCODER_ENUM_ID6 0x50 3071 3072 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3073 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3074 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3075 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3076 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3077 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3078 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3079 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3080 #define ATOM_DEVICE_CV_INDEX 0x00000008 3081 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3082 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3083 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3084 3085 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3086 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3087 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3088 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3089 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3090 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3091 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3092 3093 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3094 3095 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3096 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3097 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3098 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3099 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3100 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3101 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3102 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3103 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3104 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3105 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3106 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3107 3108 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3109 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3110 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3111 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3112 3113 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3114 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3115 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3116 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3117 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3118 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3119 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3120 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3121 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3122 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3123 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3124 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3125 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3126 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3127 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3128 3129 3130 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3131 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3132 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3133 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3134 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3135 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3136 3137 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3138 3139 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3140 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3141 3142 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3143 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3144 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3145 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3146 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3147 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3148 3149 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3150 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3151 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3152 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3153 3154 // usDeviceSupport: 3155 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3156 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3157 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3158 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3159 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3160 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3161 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3162 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3163 // Bit 8 = 0 - no CV support= 1- CV is supported 3164 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3165 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3166 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3167 // 3168 // 3169 3170 /****************************************************************************/ 3171 /* Structure used in MclkSS_InfoTable */ 3172 /****************************************************************************/ 3173 // ucI2C_ConfigID 3174 // [7:0] - I2C LINE Associate ID 3175 // = 0 - no I2C 3176 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3177 // = 0, [6:0]=SW assisted I2C ID 3178 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3179 // = 2, HW engine for Multimedia use 3180 // = 3-7 Reserved for future I2C engines 3181 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3182 3183 typedef struct _ATOM_I2C_ID_CONFIG 3184 { 3185 #if ATOM_BIG_ENDIAN 3186 UCHAR bfHW_Capable:1; 3187 UCHAR bfHW_EngineID:3; 3188 UCHAR bfI2C_LineMux:4; 3189 #else 3190 UCHAR bfI2C_LineMux:4; 3191 UCHAR bfHW_EngineID:3; 3192 UCHAR bfHW_Capable:1; 3193 #endif 3194 }ATOM_I2C_ID_CONFIG; 3195 3196 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3197 { 3198 ATOM_I2C_ID_CONFIG sbfAccess; 3199 UCHAR ucAccess; 3200 }ATOM_I2C_ID_CONFIG_ACCESS; 3201 3202 3203 /****************************************************************************/ 3204 // Structure used in GPIO_I2C_InfoTable 3205 /****************************************************************************/ 3206 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3207 { 3208 USHORT usClkMaskRegisterIndex; 3209 USHORT usClkEnRegisterIndex; 3210 USHORT usClkY_RegisterIndex; 3211 USHORT usClkA_RegisterIndex; 3212 USHORT usDataMaskRegisterIndex; 3213 USHORT usDataEnRegisterIndex; 3214 USHORT usDataY_RegisterIndex; 3215 USHORT usDataA_RegisterIndex; 3216 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3217 UCHAR ucClkMaskShift; 3218 UCHAR ucClkEnShift; 3219 UCHAR ucClkY_Shift; 3220 UCHAR ucClkA_Shift; 3221 UCHAR ucDataMaskShift; 3222 UCHAR ucDataEnShift; 3223 UCHAR ucDataY_Shift; 3224 UCHAR ucDataA_Shift; 3225 UCHAR ucReserved1; 3226 UCHAR ucReserved2; 3227 }ATOM_GPIO_I2C_ASSIGMENT; 3228 3229 typedef struct _ATOM_GPIO_I2C_INFO 3230 { 3231 ATOM_COMMON_TABLE_HEADER sHeader; 3232 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3233 }ATOM_GPIO_I2C_INFO; 3234 3235 /****************************************************************************/ 3236 // Common Structure used in other structures 3237 /****************************************************************************/ 3238 3239 #ifndef _H2INC 3240 3241 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3242 typedef struct _ATOM_MODE_MISC_INFO 3243 { 3244 #if ATOM_BIG_ENDIAN 3245 USHORT Reserved:6; 3246 USHORT RGB888:1; 3247 USHORT DoubleClock:1; 3248 USHORT Interlace:1; 3249 USHORT CompositeSync:1; 3250 USHORT V_ReplicationBy2:1; 3251 USHORT H_ReplicationBy2:1; 3252 USHORT VerticalCutOff:1; 3253 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3254 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3255 USHORT HorizontalCutOff:1; 3256 #else 3257 USHORT HorizontalCutOff:1; 3258 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3259 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3260 USHORT VerticalCutOff:1; 3261 USHORT H_ReplicationBy2:1; 3262 USHORT V_ReplicationBy2:1; 3263 USHORT CompositeSync:1; 3264 USHORT Interlace:1; 3265 USHORT DoubleClock:1; 3266 USHORT RGB888:1; 3267 USHORT Reserved:6; 3268 #endif 3269 }ATOM_MODE_MISC_INFO; 3270 3271 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3272 { 3273 ATOM_MODE_MISC_INFO sbfAccess; 3274 USHORT usAccess; 3275 }ATOM_MODE_MISC_INFO_ACCESS; 3276 3277 #else 3278 3279 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3280 { 3281 USHORT usAccess; 3282 }ATOM_MODE_MISC_INFO_ACCESS; 3283 3284 #endif 3285 3286 // usModeMiscInfo- 3287 #define ATOM_H_CUTOFF 0x01 3288 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3289 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3290 #define ATOM_V_CUTOFF 0x08 3291 #define ATOM_H_REPLICATIONBY2 0x10 3292 #define ATOM_V_REPLICATIONBY2 0x20 3293 #define ATOM_COMPOSITESYNC 0x40 3294 #define ATOM_INTERLACE 0x80 3295 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3296 #define ATOM_RGB888_MODE 0x200 3297 3298 //usRefreshRate- 3299 #define ATOM_REFRESH_43 43 3300 #define ATOM_REFRESH_47 47 3301 #define ATOM_REFRESH_56 56 3302 #define ATOM_REFRESH_60 60 3303 #define ATOM_REFRESH_65 65 3304 #define ATOM_REFRESH_70 70 3305 #define ATOM_REFRESH_72 72 3306 #define ATOM_REFRESH_75 75 3307 #define ATOM_REFRESH_85 85 3308 3309 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3310 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3311 // 3312 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3313 // = EDID_HA + EDID_HBL 3314 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3315 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3316 // = EDID_HA + EDID_HSO 3317 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3318 // VESA_BORDER = EDID_BORDER 3319 3320 /****************************************************************************/ 3321 // Structure used in SetCRTC_UsingDTDTimingTable 3322 /****************************************************************************/ 3323 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3324 { 3325 USHORT usH_Size; 3326 USHORT usH_Blanking_Time; 3327 USHORT usV_Size; 3328 USHORT usV_Blanking_Time; 3329 USHORT usH_SyncOffset; 3330 USHORT usH_SyncWidth; 3331 USHORT usV_SyncOffset; 3332 USHORT usV_SyncWidth; 3333 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3334 UCHAR ucH_Border; // From DFP EDID 3335 UCHAR ucV_Border; 3336 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3337 UCHAR ucPadding[3]; 3338 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3339 3340 /****************************************************************************/ 3341 // Structure used in SetCRTC_TimingTable 3342 /****************************************************************************/ 3343 typedef struct _SET_CRTC_TIMING_PARAMETERS 3344 { 3345 USHORT usH_Total; // horizontal total 3346 USHORT usH_Disp; // horizontal display 3347 USHORT usH_SyncStart; // horozontal Sync start 3348 USHORT usH_SyncWidth; // horizontal Sync width 3349 USHORT usV_Total; // vertical total 3350 USHORT usV_Disp; // vertical display 3351 USHORT usV_SyncStart; // vertical Sync start 3352 USHORT usV_SyncWidth; // vertical Sync width 3353 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3354 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3355 UCHAR ucOverscanRight; // right 3356 UCHAR ucOverscanLeft; // left 3357 UCHAR ucOverscanBottom; // bottom 3358 UCHAR ucOverscanTop; // top 3359 UCHAR ucReserved; 3360 }SET_CRTC_TIMING_PARAMETERS; 3361 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3362 3363 /****************************************************************************/ 3364 // Structure used in StandardVESA_TimingTable 3365 // AnalogTV_InfoTable 3366 // ComponentVideoInfoTable 3367 /****************************************************************************/ 3368 typedef struct _ATOM_MODE_TIMING 3369 { 3370 USHORT usCRTC_H_Total; 3371 USHORT usCRTC_H_Disp; 3372 USHORT usCRTC_H_SyncStart; 3373 USHORT usCRTC_H_SyncWidth; 3374 USHORT usCRTC_V_Total; 3375 USHORT usCRTC_V_Disp; 3376 USHORT usCRTC_V_SyncStart; 3377 USHORT usCRTC_V_SyncWidth; 3378 USHORT usPixelClock; //in 10Khz unit 3379 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3380 USHORT usCRTC_OverscanRight; 3381 USHORT usCRTC_OverscanLeft; 3382 USHORT usCRTC_OverscanBottom; 3383 USHORT usCRTC_OverscanTop; 3384 USHORT usReserve; 3385 UCHAR ucInternalModeNumber; 3386 UCHAR ucRefreshRate; 3387 }ATOM_MODE_TIMING; 3388 3389 typedef struct _ATOM_DTD_FORMAT 3390 { 3391 USHORT usPixClk; 3392 USHORT usHActive; 3393 USHORT usHBlanking_Time; 3394 USHORT usVActive; 3395 USHORT usVBlanking_Time; 3396 USHORT usHSyncOffset; 3397 USHORT usHSyncWidth; 3398 USHORT usVSyncOffset; 3399 USHORT usVSyncWidth; 3400 USHORT usImageHSize; 3401 USHORT usImageVSize; 3402 UCHAR ucHBorder; 3403 UCHAR ucVBorder; 3404 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3405 UCHAR ucInternalModeNumber; 3406 UCHAR ucRefreshRate; 3407 }ATOM_DTD_FORMAT; 3408 3409 /****************************************************************************/ 3410 // Structure used in LVDS_InfoTable 3411 // * Need a document to describe this table 3412 /****************************************************************************/ 3413 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3414 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3415 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3416 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3417 3418 //ucTableFormatRevision=1 3419 //ucTableContentRevision=1 3420 typedef struct _ATOM_LVDS_INFO 3421 { 3422 ATOM_COMMON_TABLE_HEADER sHeader; 3423 ATOM_DTD_FORMAT sLCDTiming; 3424 USHORT usModePatchTableOffset; 3425 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3426 USHORT usOffDelayInMs; 3427 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3428 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3429 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3430 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3431 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3432 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3433 UCHAR ucPanelDefaultRefreshRate; 3434 UCHAR ucPanelIdentification; 3435 UCHAR ucSS_Id; 3436 }ATOM_LVDS_INFO; 3437 3438 //ucTableFormatRevision=1 3439 //ucTableContentRevision=2 3440 typedef struct _ATOM_LVDS_INFO_V12 3441 { 3442 ATOM_COMMON_TABLE_HEADER sHeader; 3443 ATOM_DTD_FORMAT sLCDTiming; 3444 USHORT usExtInfoTableOffset; 3445 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3446 USHORT usOffDelayInMs; 3447 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3448 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3449 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3450 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3451 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3452 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3453 UCHAR ucPanelDefaultRefreshRate; 3454 UCHAR ucPanelIdentification; 3455 UCHAR ucSS_Id; 3456 USHORT usLCDVenderID; 3457 USHORT usLCDProductID; 3458 UCHAR ucLCDPanel_SpecialHandlingCap; 3459 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3460 UCHAR ucReserved[2]; 3461 }ATOM_LVDS_INFO_V12; 3462 3463 //Definitions for ucLCDPanel_SpecialHandlingCap: 3464 3465 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3466 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3467 #define LCDPANEL_CAP_READ_EDID 0x1 3468 3469 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3470 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3471 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3472 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3473 3474 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3475 #define LCDPANEL_CAP_eDP 0x4 3476 3477 3478 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3479 //Bit 6 5 4 3480 // 0 0 0 - Color bit depth is undefined 3481 // 0 0 1 - 6 Bits per Primary Color 3482 // 0 1 0 - 8 Bits per Primary Color 3483 // 0 1 1 - 10 Bits per Primary Color 3484 // 1 0 0 - 12 Bits per Primary Color 3485 // 1 0 1 - 14 Bits per Primary Color 3486 // 1 1 0 - 16 Bits per Primary Color 3487 // 1 1 1 - Reserved 3488 3489 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3490 3491 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3492 #define PANEL_RANDOM_DITHER 0x80 3493 #define PANEL_RANDOM_DITHER_MASK 0x80 3494 3495 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3496 3497 /****************************************************************************/ 3498 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3499 // ASIC Families: NI 3500 // ucTableFormatRevision=1 3501 // ucTableContentRevision=3 3502 /****************************************************************************/ 3503 typedef struct _ATOM_LCD_INFO_V13 3504 { 3505 ATOM_COMMON_TABLE_HEADER sHeader; 3506 ATOM_DTD_FORMAT sLCDTiming; 3507 USHORT usExtInfoTableOffset; 3508 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3509 ULONG ulReserved0; 3510 UCHAR ucLCD_Misc; // Reorganized in V13 3511 // Bit0: {=0:single, =1:dual}, 3512 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3513 // Bit3:2: {Grey level} 3514 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3515 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3516 UCHAR ucPanelDefaultRefreshRate; 3517 UCHAR ucPanelIdentification; 3518 UCHAR ucSS_Id; 3519 USHORT usLCDVenderID; 3520 USHORT usLCDProductID; 3521 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3522 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3523 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3524 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3525 // Bit7-3: Reserved 3526 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3527 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3528 3529 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3530 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3531 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3532 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3533 3534 UCHAR ucOffDelay_in4Ms; 3535 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3536 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3537 UCHAR ucReserved1; 3538 3539 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3540 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3541 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3542 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3543 3544 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3545 UCHAR uceDPToLVDSRxId; 3546 UCHAR ucLcdReservd; 3547 ULONG ulReserved[2]; 3548 }ATOM_LCD_INFO_V13; 3549 3550 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3551 3552 //Definitions for ucLCD_Misc 3553 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3554 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3555 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3556 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3557 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3558 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3559 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3560 3561 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3562 //Bit 6 5 4 3563 // 0 0 0 - Color bit depth is undefined 3564 // 0 0 1 - 6 Bits per Primary Color 3565 // 0 1 0 - 8 Bits per Primary Color 3566 // 0 1 1 - 10 Bits per Primary Color 3567 // 1 0 0 - 12 Bits per Primary Color 3568 // 1 0 1 - 14 Bits per Primary Color 3569 // 1 1 0 - 16 Bits per Primary Color 3570 // 1 1 1 - Reserved 3571 3572 //Definitions for ucLCDPanel_SpecialHandlingCap: 3573 3574 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3575 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3576 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3577 3578 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3579 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3580 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3581 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3582 3583 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3584 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3585 3586 //uceDPToLVDSRxId 3587 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3588 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3589 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3590 3591 typedef struct _ATOM_PATCH_RECORD_MODE 3592 { 3593 UCHAR ucRecordType; 3594 USHORT usHDisp; 3595 USHORT usVDisp; 3596 }ATOM_PATCH_RECORD_MODE; 3597 3598 typedef struct _ATOM_LCD_RTS_RECORD 3599 { 3600 UCHAR ucRecordType; 3601 UCHAR ucRTSValue; 3602 }ATOM_LCD_RTS_RECORD; 3603 3604 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3605 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3606 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3607 { 3608 UCHAR ucRecordType; 3609 USHORT usLCDCap; 3610 }ATOM_LCD_MODE_CONTROL_CAP; 3611 3612 #define LCD_MODE_CAP_BL_OFF 1 3613 #define LCD_MODE_CAP_CRTC_OFF 2 3614 #define LCD_MODE_CAP_PANEL_OFF 4 3615 3616 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3617 { 3618 UCHAR ucRecordType; 3619 UCHAR ucFakeEDIDLength; 3620 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3621 } ATOM_FAKE_EDID_PATCH_RECORD; 3622 3623 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3624 { 3625 UCHAR ucRecordType; 3626 USHORT usHSize; 3627 USHORT usVSize; 3628 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3629 3630 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3631 #define LCD_RTS_RECORD_TYPE 2 3632 #define LCD_CAP_RECORD_TYPE 3 3633 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3634 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3635 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3636 #define ATOM_RECORD_END_TYPE 0xFF 3637 3638 /****************************Spread Spectrum Info Table Definitions **********************/ 3639 3640 //ucTableFormatRevision=1 3641 //ucTableContentRevision=2 3642 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3643 { 3644 USHORT usSpreadSpectrumPercentage; 3645 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3646 UCHAR ucSS_Step; 3647 UCHAR ucSS_Delay; 3648 UCHAR ucSS_Id; 3649 UCHAR ucRecommendedRef_Div; 3650 UCHAR ucSS_Range; //it was reserved for V11 3651 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3652 3653 #define ATOM_MAX_SS_ENTRY 16 3654 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3655 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3656 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3657 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3658 3659 3660 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3661 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3662 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3663 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3664 #define ATOM_INTERNAL_SS_MASK 0x00000000 3665 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3666 #define EXEC_SS_STEP_SIZE_SHIFT 2 3667 #define EXEC_SS_DELAY_SHIFT 4 3668 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3669 3670 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3671 { 3672 ATOM_COMMON_TABLE_HEADER sHeader; 3673 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3674 }ATOM_SPREAD_SPECTRUM_INFO; 3675 3676 /****************************************************************************/ 3677 // Structure used in AnalogTV_InfoTable (Top level) 3678 /****************************************************************************/ 3679 //ucTVBootUpDefaultStd definition: 3680 3681 //ATOM_TV_NTSC 1 3682 //ATOM_TV_NTSCJ 2 3683 //ATOM_TV_PAL 3 3684 //ATOM_TV_PALM 4 3685 //ATOM_TV_PALCN 5 3686 //ATOM_TV_PALN 6 3687 //ATOM_TV_PAL60 7 3688 //ATOM_TV_SECAM 8 3689 3690 //ucTVSupportedStd definition: 3691 #define NTSC_SUPPORT 0x1 3692 #define NTSCJ_SUPPORT 0x2 3693 3694 #define PAL_SUPPORT 0x4 3695 #define PALM_SUPPORT 0x8 3696 #define PALCN_SUPPORT 0x10 3697 #define PALN_SUPPORT 0x20 3698 #define PAL60_SUPPORT 0x40 3699 #define SECAM_SUPPORT 0x80 3700 3701 #define MAX_SUPPORTED_TV_TIMING 2 3702 3703 typedef struct _ATOM_ANALOG_TV_INFO 3704 { 3705 ATOM_COMMON_TABLE_HEADER sHeader; 3706 UCHAR ucTV_SupportedStandard; 3707 UCHAR ucTV_BootUpDefaultStandard; 3708 UCHAR ucExt_TV_ASIC_ID; 3709 UCHAR ucExt_TV_ASIC_SlaveAddr; 3710 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3711 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3712 }ATOM_ANALOG_TV_INFO; 3713 3714 #define MAX_SUPPORTED_TV_TIMING_V1_2 3 3715 3716 typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3717 { 3718 ATOM_COMMON_TABLE_HEADER sHeader; 3719 UCHAR ucTV_SupportedStandard; 3720 UCHAR ucTV_BootUpDefaultStandard; 3721 UCHAR ucExt_TV_ASIC_ID; 3722 UCHAR ucExt_TV_ASIC_SlaveAddr; 3723 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3724 }ATOM_ANALOG_TV_INFO_V1_2; 3725 3726 typedef struct _ATOM_DPCD_INFO 3727 { 3728 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3729 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3730 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3731 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3732 }ATOM_DPCD_INFO; 3733 3734 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3735 3736 /**************************************************************************/ 3737 // VRAM usage and their defintions 3738 3739 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3740 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3741 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3742 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3743 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3744 3745 #ifndef VESA_MEMORY_IN_64K_BLOCK 3746 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3747 #endif 3748 3749 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3750 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3751 #define ATOM_HWICON_INFOTABLE_SIZE 32 3752 #define MAX_DTD_MODE_IN_VRAM 6 3753 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3754 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3755 //20 bytes for Encoder Type and DPCD in STD EDID area 3756 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3757 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3758 3759 #define ATOM_HWICON1_SURFACE_ADDR 0 3760 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3761 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3762 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3763 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3764 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3765 3766 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3767 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3768 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3769 3770 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3771 3772 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3773 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3774 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3775 3776 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3777 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3778 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3779 3780 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3781 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3782 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3783 3784 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3785 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3786 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3787 3788 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3789 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3790 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3791 3792 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3793 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3794 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3795 3796 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3797 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3798 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3799 3800 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3801 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3802 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3803 3804 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3805 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3806 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3807 3808 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3809 3810 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3811 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3812 3813 //The size below is in Kb! 3814 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3815 3816 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3817 3818 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3819 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3820 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3821 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3822 3823 /***********************************************************************************/ 3824 // Structure used in VRAM_UsageByFirmwareTable 3825 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3826 // at running time. 3827 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3828 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3829 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3830 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3831 /***********************************************************************************/ 3832 // Note3: 3833 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3834 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3835 3836 If (ulStartAddrUsedByFirmware!=0) 3837 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3838 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3839 else //Non VGA case 3840 if (FB_Size<=2Gb) 3841 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3842 else 3843 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3844 3845 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3846 3847 /***********************************************************************************/ 3848 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3849 3850 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3851 { 3852 ULONG ulStartAddrUsedByFirmware; 3853 USHORT usFirmwareUseInKb; 3854 USHORT usReserved; 3855 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3856 3857 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3858 { 3859 ATOM_COMMON_TABLE_HEADER sHeader; 3860 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3861 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3862 3863 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3864 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3865 { 3866 ULONG ulStartAddrUsedByFirmware; 3867 USHORT usFirmwareUseInKb; 3868 USHORT usFBUsedByDrvInKb; 3869 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3870 3871 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3872 { 3873 ATOM_COMMON_TABLE_HEADER sHeader; 3874 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3875 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3876 3877 /****************************************************************************/ 3878 // Structure used in GPIO_Pin_LUTTable 3879 /****************************************************************************/ 3880 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3881 { 3882 USHORT usGpioPin_AIndex; 3883 UCHAR ucGpioPinBitShift; 3884 UCHAR ucGPIO_ID; 3885 }ATOM_GPIO_PIN_ASSIGNMENT; 3886 3887 //ucGPIO_ID pre-define id for multiple usage 3888 //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 3889 #define PP_AC_DC_SWITCH_GPIO_PINID 60 3890 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 3891 #define VDDC_VRHOT_GPIO_PINID 61 3892 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 3893 #define VDDC_PCC_GPIO_PINID 62 3894 3895 typedef struct _ATOM_GPIO_PIN_LUT 3896 { 3897 ATOM_COMMON_TABLE_HEADER sHeader; 3898 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3899 }ATOM_GPIO_PIN_LUT; 3900 3901 /****************************************************************************/ 3902 // Structure used in ComponentVideoInfoTable 3903 /****************************************************************************/ 3904 #define GPIO_PIN_ACTIVE_HIGH 0x1 3905 3906 #define MAX_SUPPORTED_CV_STANDARDS 5 3907 3908 // definitions for ATOM_D_INFO.ucSettings 3909 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3910 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3911 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3912 3913 typedef struct _ATOM_GPIO_INFO 3914 { 3915 USHORT usAOffset; 3916 UCHAR ucSettings; 3917 UCHAR ucReserved; 3918 }ATOM_GPIO_INFO; 3919 3920 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3921 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3922 3923 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3924 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3925 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3926 3927 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3928 //Line 3 out put 5V. 3929 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3930 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3931 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3932 3933 //Line 3 out put 2.2V 3934 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3935 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3936 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3937 3938 //Line 3 out put 0V 3939 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3940 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3941 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3942 3943 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3944 3945 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3946 3947 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3948 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3949 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3950 3951 3952 typedef struct _ATOM_COMPONENT_VIDEO_INFO 3953 { 3954 ATOM_COMMON_TABLE_HEADER sHeader; 3955 USHORT usMask_PinRegisterIndex; 3956 USHORT usEN_PinRegisterIndex; 3957 USHORT usY_PinRegisterIndex; 3958 USHORT usA_PinRegisterIndex; 3959 UCHAR ucBitShift; 3960 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3961 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3962 UCHAR ucMiscInfo; 3963 UCHAR uc480i; 3964 UCHAR uc480p; 3965 UCHAR uc720p; 3966 UCHAR uc1080i; 3967 UCHAR ucLetterBoxMode; 3968 UCHAR ucReserved[3]; 3969 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3970 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3971 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3972 }ATOM_COMPONENT_VIDEO_INFO; 3973 3974 //ucTableFormatRevision=2 3975 //ucTableContentRevision=1 3976 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3977 { 3978 ATOM_COMMON_TABLE_HEADER sHeader; 3979 UCHAR ucMiscInfo; 3980 UCHAR uc480i; 3981 UCHAR uc480p; 3982 UCHAR uc720p; 3983 UCHAR uc1080i; 3984 UCHAR ucReserved; 3985 UCHAR ucLetterBoxMode; 3986 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3987 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3988 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3989 }ATOM_COMPONENT_VIDEO_INFO_V21; 3990 3991 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3992 3993 /****************************************************************************/ 3994 // Structure used in object_InfoTable 3995 /****************************************************************************/ 3996 typedef struct _ATOM_OBJECT_HEADER 3997 { 3998 ATOM_COMMON_TABLE_HEADER sHeader; 3999 USHORT usDeviceSupport; 4000 USHORT usConnectorObjectTableOffset; 4001 USHORT usRouterObjectTableOffset; 4002 USHORT usEncoderObjectTableOffset; 4003 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4004 USHORT usDisplayPathTableOffset; 4005 }ATOM_OBJECT_HEADER; 4006 4007 typedef struct _ATOM_OBJECT_HEADER_V3 4008 { 4009 ATOM_COMMON_TABLE_HEADER sHeader; 4010 USHORT usDeviceSupport; 4011 USHORT usConnectorObjectTableOffset; 4012 USHORT usRouterObjectTableOffset; 4013 USHORT usEncoderObjectTableOffset; 4014 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4015 USHORT usDisplayPathTableOffset; 4016 USHORT usMiscObjectTableOffset; 4017 }ATOM_OBJECT_HEADER_V3; 4018 4019 typedef struct _ATOM_DISPLAY_OBJECT_PATH 4020 { 4021 USHORT usDeviceTag; //supported device 4022 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4023 USHORT usConnObjectId; //Connector Object ID 4024 USHORT usGPUObjectId; //GPU ID 4025 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4026 }ATOM_DISPLAY_OBJECT_PATH; 4027 4028 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4029 { 4030 USHORT usDeviceTag; //supported device 4031 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4032 USHORT usConnObjectId; //Connector Object ID 4033 USHORT usGPUObjectId; //GPU ID 4034 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4035 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4036 4037 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4038 { 4039 UCHAR ucNumOfDispPath; 4040 UCHAR ucVersion; 4041 UCHAR ucPadding[2]; 4042 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4043 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 4044 4045 4046 typedef struct _ATOM_OBJECT //each object has this structure 4047 { 4048 USHORT usObjectID; 4049 USHORT usSrcDstTableOffset; 4050 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4051 USHORT usReserved; 4052 }ATOM_OBJECT; 4053 4054 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4055 { 4056 UCHAR ucNumberOfObjects; 4057 UCHAR ucPadding[3]; 4058 ATOM_OBJECT asObjects[1]; 4059 }ATOM_OBJECT_TABLE; 4060 4061 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4062 { 4063 UCHAR ucNumberOfSrc; 4064 USHORT usSrcObjectID[1]; 4065 UCHAR ucNumberOfDst; 4066 USHORT usDstObjectID[1]; 4067 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4068 4069 4070 //Two definitions below are for OPM on MXM module designs 4071 4072 #define EXT_HPDPIN_LUTINDEX_0 0 4073 #define EXT_HPDPIN_LUTINDEX_1 1 4074 #define EXT_HPDPIN_LUTINDEX_2 2 4075 #define EXT_HPDPIN_LUTINDEX_3 3 4076 #define EXT_HPDPIN_LUTINDEX_4 4 4077 #define EXT_HPDPIN_LUTINDEX_5 5 4078 #define EXT_HPDPIN_LUTINDEX_6 6 4079 #define EXT_HPDPIN_LUTINDEX_7 7 4080 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4081 4082 #define EXT_AUXDDC_LUTINDEX_0 0 4083 #define EXT_AUXDDC_LUTINDEX_1 1 4084 #define EXT_AUXDDC_LUTINDEX_2 2 4085 #define EXT_AUXDDC_LUTINDEX_3 3 4086 #define EXT_AUXDDC_LUTINDEX_4 4 4087 #define EXT_AUXDDC_LUTINDEX_5 5 4088 #define EXT_AUXDDC_LUTINDEX_6 6 4089 #define EXT_AUXDDC_LUTINDEX_7 7 4090 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4091 4092 //ucChannelMapping are defined as following 4093 //for DP connector, eDP, DP to VGA/LVDS 4094 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4095 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4096 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4097 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4098 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4099 { 4100 #if ATOM_BIG_ENDIAN 4101 UCHAR ucDP_Lane3_Source:2; 4102 UCHAR ucDP_Lane2_Source:2; 4103 UCHAR ucDP_Lane1_Source:2; 4104 UCHAR ucDP_Lane0_Source:2; 4105 #else 4106 UCHAR ucDP_Lane0_Source:2; 4107 UCHAR ucDP_Lane1_Source:2; 4108 UCHAR ucDP_Lane2_Source:2; 4109 UCHAR ucDP_Lane3_Source:2; 4110 #endif 4111 }ATOM_DP_CONN_CHANNEL_MAPPING; 4112 4113 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4114 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4115 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4116 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4117 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4118 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4119 { 4120 #if ATOM_BIG_ENDIAN 4121 UCHAR ucDVI_CLK_Source:2; 4122 UCHAR ucDVI_DATA0_Source:2; 4123 UCHAR ucDVI_DATA1_Source:2; 4124 UCHAR ucDVI_DATA2_Source:2; 4125 #else 4126 UCHAR ucDVI_DATA2_Source:2; 4127 UCHAR ucDVI_DATA1_Source:2; 4128 UCHAR ucDVI_DATA0_Source:2; 4129 UCHAR ucDVI_CLK_Source:2; 4130 #endif 4131 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4132 4133 typedef struct _EXT_DISPLAY_PATH 4134 { 4135 USHORT usDeviceTag; //A bit vector to show what devices are supported 4136 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4137 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4138 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4139 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4140 USHORT usExtEncoderObjId; //external encoder object id 4141 union{ 4142 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4143 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4144 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4145 }; 4146 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4147 USHORT usCaps; 4148 USHORT usReserved; 4149 }EXT_DISPLAY_PATH; 4150 4151 #define NUMBER_OF_UCHAR_FOR_GUID 16 4152 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4153 4154 //usCaps 4155 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4156 #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 4157 4158 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4159 { 4160 ATOM_COMMON_TABLE_HEADER sHeader; 4161 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4162 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4163 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4164 UCHAR uc3DStereoPinId; // use for eDP panel 4165 UCHAR ucRemoteDisplayConfig; 4166 UCHAR uceDPToLVDSRxId; 4167 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4168 UCHAR Reserved[3]; // for potential expansion 4169 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4170 4171 //Related definitions, all records are different but they have a commond header 4172 typedef struct _ATOM_COMMON_RECORD_HEADER 4173 { 4174 UCHAR ucRecordType; //An emun to indicate the record type 4175 UCHAR ucRecordSize; //The size of the whole record in byte 4176 }ATOM_COMMON_RECORD_HEADER; 4177 4178 4179 #define ATOM_I2C_RECORD_TYPE 1 4180 #define ATOM_HPD_INT_RECORD_TYPE 2 4181 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4182 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4183 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4184 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4185 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4186 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4187 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4188 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4189 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4190 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4191 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4192 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4193 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4194 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4195 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4196 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4197 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4198 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4199 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4200 4201 //Must be updated when new record type is added,equal to that record definition! 4202 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE 4203 4204 typedef struct _ATOM_I2C_RECORD 4205 { 4206 ATOM_COMMON_RECORD_HEADER sheader; 4207 ATOM_I2C_ID_CONFIG sucI2cId; 4208 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4209 }ATOM_I2C_RECORD; 4210 4211 typedef struct _ATOM_HPD_INT_RECORD 4212 { 4213 ATOM_COMMON_RECORD_HEADER sheader; 4214 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4215 UCHAR ucPlugged_PinState; 4216 }ATOM_HPD_INT_RECORD; 4217 4218 4219 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4220 { 4221 ATOM_COMMON_RECORD_HEADER sheader; 4222 UCHAR ucProtectionFlag; 4223 UCHAR ucReserved; 4224 }ATOM_OUTPUT_PROTECTION_RECORD; 4225 4226 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4227 { 4228 ULONG ulACPIDeviceEnum; //Reserved for now 4229 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4230 USHORT usPadding; 4231 }ATOM_CONNECTOR_DEVICE_TAG; 4232 4233 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4234 { 4235 ATOM_COMMON_RECORD_HEADER sheader; 4236 UCHAR ucNumberOfDevice; 4237 UCHAR ucReserved; 4238 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4239 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4240 4241 4242 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4243 { 4244 ATOM_COMMON_RECORD_HEADER sheader; 4245 UCHAR ucConfigGPIOID; 4246 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4247 UCHAR ucFlowinGPIPID; 4248 UCHAR ucExtInGPIPID; 4249 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4250 4251 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4252 { 4253 ATOM_COMMON_RECORD_HEADER sheader; 4254 UCHAR ucCTL1GPIO_ID; 4255 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4256 UCHAR ucCTL2GPIO_ID; 4257 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4258 UCHAR ucCTL3GPIO_ID; 4259 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4260 UCHAR ucCTLFPGA_IN_ID; 4261 UCHAR ucPadding[3]; 4262 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4263 4264 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4265 { 4266 ATOM_COMMON_RECORD_HEADER sheader; 4267 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4268 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4269 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4270 4271 typedef struct _ATOM_JTAG_RECORD 4272 { 4273 ATOM_COMMON_RECORD_HEADER sheader; 4274 UCHAR ucTMSGPIO_ID; 4275 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4276 UCHAR ucTCKGPIO_ID; 4277 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4278 UCHAR ucTDOGPIO_ID; 4279 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4280 UCHAR ucTDIGPIO_ID; 4281 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4282 UCHAR ucPadding[2]; 4283 }ATOM_JTAG_RECORD; 4284 4285 4286 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4287 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4288 { 4289 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4290 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4291 }ATOM_GPIO_PIN_CONTROL_PAIR; 4292 4293 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4294 { 4295 ATOM_COMMON_RECORD_HEADER sheader; 4296 UCHAR ucFlags; // Future expnadibility 4297 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4298 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4299 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4300 4301 //Definitions for GPIO pin state 4302 #define GPIO_PIN_TYPE_INPUT 0x00 4303 #define GPIO_PIN_TYPE_OUTPUT 0x10 4304 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4305 4306 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4307 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4308 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4309 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4310 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4311 4312 // Indexes to GPIO array in GLSync record 4313 // GLSync record is for Frame Lock/Gen Lock feature. 4314 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4315 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4316 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4317 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4318 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4319 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4320 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4321 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4322 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4323 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4324 4325 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4326 { 4327 ATOM_COMMON_RECORD_HEADER sheader; 4328 ULONG ulStrengthControl; // DVOA strength control for CF 4329 UCHAR ucPadding[2]; 4330 }ATOM_ENCODER_DVO_CF_RECORD; 4331 4332 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4333 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4334 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4335 4336 typedef struct _ATOM_ENCODER_CAP_RECORD 4337 { 4338 ATOM_COMMON_RECORD_HEADER sheader; 4339 union { 4340 USHORT usEncoderCap; 4341 struct { 4342 #if ATOM_BIG_ENDIAN 4343 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4344 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4345 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4346 #else 4347 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4348 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4349 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4350 #endif 4351 }; 4352 }; 4353 }ATOM_ENCODER_CAP_RECORD; 4354 4355 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4356 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4357 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4358 4359 typedef struct _ATOM_CONNECTOR_CF_RECORD 4360 { 4361 ATOM_COMMON_RECORD_HEADER sheader; 4362 USHORT usMaxPixClk; 4363 UCHAR ucFlowCntlGpioId; 4364 UCHAR ucSwapCntlGpioId; 4365 UCHAR ucConnectedDvoBundle; 4366 UCHAR ucPadding; 4367 }ATOM_CONNECTOR_CF_RECORD; 4368 4369 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4370 { 4371 ATOM_COMMON_RECORD_HEADER sheader; 4372 ATOM_DTD_FORMAT asTiming; 4373 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4374 4375 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4376 { 4377 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4378 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4379 UCHAR ucReserved; 4380 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4381 4382 4383 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4384 { 4385 ATOM_COMMON_RECORD_HEADER sheader; 4386 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4387 UCHAR ucMuxControlPin; 4388 UCHAR ucMuxState[2]; //for alligment purpose 4389 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4390 4391 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4392 { 4393 ATOM_COMMON_RECORD_HEADER sheader; 4394 UCHAR ucMuxType; 4395 UCHAR ucMuxControlPin; 4396 UCHAR ucMuxState[2]; //for alligment purpose 4397 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4398 4399 // define ucMuxType 4400 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4401 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4402 4403 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4404 { 4405 ATOM_COMMON_RECORD_HEADER sheader; 4406 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4407 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4408 4409 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4410 { 4411 ATOM_COMMON_RECORD_HEADER sheader; 4412 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4413 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4414 4415 typedef struct _ATOM_OBJECT_LINK_RECORD 4416 { 4417 ATOM_COMMON_RECORD_HEADER sheader; 4418 USHORT usObjectID; //could be connector, encorder or other object in object.h 4419 }ATOM_OBJECT_LINK_RECORD; 4420 4421 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4422 { 4423 ATOM_COMMON_RECORD_HEADER sheader; 4424 USHORT usReserved; 4425 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4426 4427 typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4428 { 4429 USHORT usConnectorObjectId; 4430 UCHAR ucConnectorType; 4431 UCHAR ucPosition; 4432 }ATOM_CONNECTOR_LAYOUT_INFO; 4433 4434 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4435 #define CONNECTOR_TYPE_DVI_D 1 4436 #define CONNECTOR_TYPE_DVI_I 2 4437 #define CONNECTOR_TYPE_VGA 3 4438 #define CONNECTOR_TYPE_HDMI 4 4439 #define CONNECTOR_TYPE_DISPLAY_PORT 5 4440 #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4441 4442 typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4443 { 4444 ATOM_COMMON_RECORD_HEADER sheader; 4445 UCHAR ucLength; 4446 UCHAR ucWidth; 4447 UCHAR ucConnNum; 4448 UCHAR ucReserved; 4449 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4450 }ATOM_BRACKET_LAYOUT_RECORD; 4451 4452 /****************************************************************************/ 4453 // ASIC voltage data table 4454 /****************************************************************************/ 4455 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4456 { 4457 USHORT usVDDCBaseLevel; //In number of 50mv unit 4458 USHORT usReserved; //For possible extension table offset 4459 UCHAR ucNumOfVoltageEntries; 4460 UCHAR ucBytesPerVoltageEntry; 4461 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4462 UCHAR ucDefaultVoltageEntry; 4463 UCHAR ucVoltageControlI2cLine; 4464 UCHAR ucVoltageControlAddress; 4465 UCHAR ucVoltageControlOffset; 4466 }ATOM_VOLTAGE_INFO_HEADER; 4467 4468 typedef struct _ATOM_VOLTAGE_INFO 4469 { 4470 ATOM_COMMON_TABLE_HEADER sHeader; 4471 ATOM_VOLTAGE_INFO_HEADER viHeader; 4472 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4473 }ATOM_VOLTAGE_INFO; 4474 4475 4476 typedef struct _ATOM_VOLTAGE_FORMULA 4477 { 4478 USHORT usVoltageBaseLevel; // In number of 1mv unit 4479 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4480 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4481 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4482 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4483 UCHAR ucReserved; 4484 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4485 }ATOM_VOLTAGE_FORMULA; 4486 4487 typedef struct _VOLTAGE_LUT_ENTRY 4488 { 4489 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4490 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4491 }VOLTAGE_LUT_ENTRY; 4492 4493 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4494 { 4495 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4496 UCHAR ucReserved[3]; 4497 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4498 }ATOM_VOLTAGE_FORMULA_V2; 4499 4500 typedef struct _ATOM_VOLTAGE_CONTROL 4501 { 4502 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4503 UCHAR ucVoltageControlI2cLine; 4504 UCHAR ucVoltageControlAddress; 4505 UCHAR ucVoltageControlOffset; 4506 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4507 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4508 UCHAR ucReserved; 4509 }ATOM_VOLTAGE_CONTROL; 4510 4511 // Define ucVoltageControlId 4512 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4513 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4514 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4515 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4516 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4517 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4518 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4519 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4520 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4521 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4522 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4523 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4524 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 4525 #define VOLTAGE_CONTROL_ID_CHL8214 0x0B 4526 #define VOLTAGE_CONTROL_ID_UP1801 0x0C 4527 #define VOLTAGE_CONTROL_ID_ST6788A 0x0D 4528 #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 4529 #define VOLTAGE_CONTROL_ID_AD527x 0x0F 4530 #define VOLTAGE_CONTROL_ID_NCP81022 0x10 4531 #define VOLTAGE_CONTROL_ID_LTC2635 0x11 4532 4533 typedef struct _ATOM_VOLTAGE_OBJECT 4534 { 4535 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4536 UCHAR ucSize; //Size of Object 4537 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4538 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4539 }ATOM_VOLTAGE_OBJECT; 4540 4541 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4542 { 4543 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4544 UCHAR ucSize; //Size of Object 4545 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4546 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4547 }ATOM_VOLTAGE_OBJECT_V2; 4548 4549 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4550 { 4551 ATOM_COMMON_TABLE_HEADER sHeader; 4552 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4553 }ATOM_VOLTAGE_OBJECT_INFO; 4554 4555 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4556 { 4557 ATOM_COMMON_TABLE_HEADER sHeader; 4558 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4559 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4560 4561 typedef struct _ATOM_LEAKID_VOLTAGE 4562 { 4563 UCHAR ucLeakageId; 4564 UCHAR ucReserved; 4565 USHORT usVoltage; 4566 }ATOM_LEAKID_VOLTAGE; 4567 4568 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4569 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4570 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4571 USHORT usSize; //Size of Object 4572 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 4573 4574 // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 4575 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4576 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4577 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4578 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4579 #define VOLTAGE_OBJ_EVV 8 4580 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4581 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4582 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4583 4584 typedef struct _VOLTAGE_LUT_ENTRY_V2 4585 { 4586 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4587 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4588 }VOLTAGE_LUT_ENTRY_V2; 4589 4590 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4591 { 4592 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4593 USHORT usVoltageId; 4594 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4595 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4596 4597 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4598 { 4599 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 4600 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4601 UCHAR ucVoltageControlI2cLine; 4602 UCHAR ucVoltageControlAddress; 4603 UCHAR ucVoltageControlOffset; 4604 ULONG ulReserved; 4605 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4606 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4607 4608 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 4609 #define VOLTAGE_DATA_ONE_BYTE 0 4610 #define VOLTAGE_DATA_TWO_BYTE 1 4611 4612 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4613 { 4614 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4615 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4616 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4617 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4618 UCHAR ucReserved; 4619 ULONG ulGpioMaskVal; // GPIO Mask value 4620 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4621 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 4622 4623 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4624 { 4625 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 4626 UCHAR ucLeakageCntlId; // default is 0 4627 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4628 UCHAR ucReserved[2]; 4629 ULONG ulMaxVoltageLevel; 4630 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4631 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4632 4633 4634 typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 4635 { 4636 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 4637 // 14:7 – PSI0_VID 4638 // 6 – PSI0_EN 4639 // 5 – PSI1 4640 // 4:2 – load line slope trim. 4641 // 1:0 – offset trim, 4642 USHORT usLoadLine_PSI; 4643 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4644 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 4645 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 4646 ULONG ulReserved; 4647 }ATOM_SVID2_VOLTAGE_OBJECT_V3; 4648 4649 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4650 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4651 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4652 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4653 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 4654 }ATOM_VOLTAGE_OBJECT_V3; 4655 4656 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4657 { 4658 ATOM_COMMON_TABLE_HEADER sHeader; 4659 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4660 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4661 4662 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4663 { 4664 UCHAR ucProfileId; 4665 UCHAR ucReserved; 4666 USHORT usSize; 4667 USHORT usEfuseSpareStartAddr; 4668 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4669 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4670 }ATOM_ASIC_PROFILE_VOLTAGE; 4671 4672 //ucProfileId 4673 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4674 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4675 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4676 4677 typedef struct _ATOM_ASIC_PROFILING_INFO 4678 { 4679 ATOM_COMMON_TABLE_HEADER asHeader; 4680 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4681 }ATOM_ASIC_PROFILING_INFO; 4682 4683 typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 4684 { 4685 ATOM_COMMON_TABLE_HEADER asHeader; 4686 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 4687 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 4688 4689 UCHAR ucElbVDDC_Num; 4690 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 4691 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4692 4693 UCHAR ucElbVDDCI_Num; 4694 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4695 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4696 }ATOM_ASIC_PROFILING_INFO_V2_1; 4697 4698 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 4699 { 4700 ATOM_COMMON_TABLE_HEADER asHeader; 4701 ULONG ulEvvDerateTdp; 4702 ULONG ulEvvDerateTdc; 4703 ULONG ulBoardCoreTemp; 4704 ULONG ulMaxVddc; 4705 ULONG ulMinVddc; 4706 ULONG ulLoadLineSlop; 4707 ULONG ulLeakageTemp; 4708 ULONG ulLeakageVoltage; 4709 ULONG ulCACmEncodeRange; 4710 ULONG ulCACmEncodeAverage; 4711 ULONG ulCACbEncodeRange; 4712 ULONG ulCACbEncodeAverage; 4713 ULONG ulKt_bEncodeRange; 4714 ULONG ulKt_bEncodeAverage; 4715 ULONG ulKv_mEncodeRange; 4716 ULONG ulKv_mEncodeAverage; 4717 ULONG ulKv_bEncodeRange; 4718 ULONG ulKv_bEncodeAverage; 4719 ULONG ulLkgEncodeLn_MaxDivMin; 4720 ULONG ulLkgEncodeMin; 4721 ULONG ulEfuseLogisticAlpha; 4722 USHORT usPowerDpm0; 4723 USHORT usCurrentDpm0; 4724 USHORT usPowerDpm1; 4725 USHORT usCurrentDpm1; 4726 USHORT usPowerDpm2; 4727 USHORT usCurrentDpm2; 4728 USHORT usPowerDpm3; 4729 USHORT usCurrentDpm3; 4730 USHORT usPowerDpm4; 4731 USHORT usCurrentDpm4; 4732 USHORT usPowerDpm5; 4733 USHORT usCurrentDpm5; 4734 USHORT usPowerDpm6; 4735 USHORT usCurrentDpm6; 4736 USHORT usPowerDpm7; 4737 USHORT usCurrentDpm7; 4738 }ATOM_ASIC_PROFILING_INFO_V3_1; 4739 4740 4741 typedef struct _ATOM_POWER_SOURCE_OBJECT 4742 { 4743 UCHAR ucPwrSrcId; // Power source 4744 UCHAR ucPwrSensorType; // GPIO, I2C or none 4745 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4746 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4747 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4748 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4749 UCHAR ucPwrSensActiveState; // high active or low active 4750 UCHAR ucReserve[3]; // reserve 4751 USHORT usSensPwr; // in unit of watt 4752 }ATOM_POWER_SOURCE_OBJECT; 4753 4754 typedef struct _ATOM_POWER_SOURCE_INFO 4755 { 4756 ATOM_COMMON_TABLE_HEADER asHeader; 4757 UCHAR asPwrbehave[16]; 4758 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4759 }ATOM_POWER_SOURCE_INFO; 4760 4761 4762 //Define ucPwrSrcId 4763 #define POWERSOURCE_PCIE_ID1 0x00 4764 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4765 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4766 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4767 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4768 4769 //define ucPwrSensorId 4770 #define POWER_SENSOR_ALWAYS 0x00 4771 #define POWER_SENSOR_GPIO 0x01 4772 #define POWER_SENSOR_I2C 0x02 4773 4774 typedef struct _ATOM_CLK_VOLT_CAPABILITY 4775 { 4776 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4777 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4778 }ATOM_CLK_VOLT_CAPABILITY; 4779 4780 typedef struct _ATOM_AVAILABLE_SCLK_LIST 4781 { 4782 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4783 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4784 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4785 }ATOM_AVAILABLE_SCLK_LIST; 4786 4787 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4788 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4789 4790 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 4791 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4792 { 4793 ATOM_COMMON_TABLE_HEADER sHeader; 4794 ULONG ulBootUpEngineClock; 4795 ULONG ulDentistVCOFreq; 4796 ULONG ulBootUpUMAClock; 4797 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4798 ULONG ulBootUpReqDisplayVector; 4799 ULONG ulOtherDisplayMisc; 4800 ULONG ulGPUCapInfo; 4801 ULONG ulSB_MMIO_Base_Addr; 4802 USHORT usRequestedPWMFreqInHz; 4803 UCHAR ucHtcTmpLmt; 4804 UCHAR ucHtcHystLmt; 4805 ULONG ulMinEngineClock; 4806 ULONG ulSystemConfig; 4807 ULONG ulCPUCapInfo; 4808 USHORT usNBP0Voltage; 4809 USHORT usNBP1Voltage; 4810 USHORT usBootUpNBVoltage; 4811 USHORT usExtDispConnInfoOffset; 4812 USHORT usPanelRefreshRateRange; 4813 UCHAR ucMemoryType; 4814 UCHAR ucUMAChannelNumber; 4815 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4816 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4817 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4818 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4819 ULONG ulGMCRestoreResetTime; 4820 ULONG ulMinimumNClk; 4821 ULONG ulIdleNClk; 4822 ULONG ulDDR_DLL_PowerUpTime; 4823 ULONG ulDDR_PLL_PowerUpTime; 4824 USHORT usPCIEClkSSPercentage; 4825 USHORT usPCIEClkSSType; 4826 USHORT usLvdsSSPercentage; 4827 USHORT usLvdsSSpreadRateIn10Hz; 4828 USHORT usHDMISSPercentage; 4829 USHORT usHDMISSpreadRateIn10Hz; 4830 USHORT usDVISSPercentage; 4831 USHORT usDVISSpreadRateIn10Hz; 4832 ULONG SclkDpmBoostMargin; 4833 ULONG SclkDpmThrottleMargin; 4834 USHORT SclkDpmTdpLimitPG; 4835 USHORT SclkDpmTdpLimitBoost; 4836 ULONG ulBoostEngineCLock; 4837 UCHAR ulBoostVid_2bit; 4838 UCHAR EnableBoost; 4839 USHORT GnbTdpLimit; 4840 USHORT usMaxLVDSPclkFreqInSingleLink; 4841 UCHAR ucLvdsMisc; 4842 UCHAR ucLVDSReserved; 4843 ULONG ulReserved3[15]; 4844 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4845 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 4846 4847 // ulGPUCapInfo 4848 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4849 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4850 4851 //ucLVDSMisc: 4852 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4853 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4854 #define SYS_INFO_LVDSMISC__888_BPC 0x04 4855 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4856 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4857 // new since Trinity 4858 #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 4859 4860 // not used any more 4861 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4862 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4863 4864 /********************************************************************************************************************** 4865 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4866 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4867 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4868 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4869 sDISPCLK_Voltage: Report Display clock voltage requirement. 4870 4871 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4872 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4873 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4874 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4875 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4876 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4877 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4878 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4879 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4880 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4881 ulOtherDisplayMisc: Other display related flags, not defined yet. 4882 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4883 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4884 bit[3]=0: Enable HW AUX mode detection logic 4885 =1: Disable HW AUX mode dettion logic 4886 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4887 4888 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4889 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4890 4891 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4892 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4893 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4894 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4895 and enabling VariBri under the driver environment from PP table is optional. 4896 4897 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4898 that BL control from GPU is expected. 4899 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4900 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4901 it's per platform 4902 and enabling VariBri under the driver environment from PP table is optional. 4903 4904 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4905 Threshold on value to enter HTC_active state. 4906 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4907 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4908 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4909 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4910 =1: PCIE Power Gating Enabled 4911 Bit[1]=0: DDR-DLL shut-down feature disabled. 4912 1: DDR-DLL shut-down feature enabled. 4913 Bit[2]=0: DDR-PLL Power down feature disabled. 4914 1: DDR-PLL Power down feature enabled. 4915 ulCPUCapInfo: TBD 4916 usNBP0Voltage: VID for voltage on NB P0 State 4917 usNBP1Voltage: VID for voltage on NB P1 State 4918 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4919 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4920 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4921 to indicate a range. 4922 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4923 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4924 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4925 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4926 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4927 ucUMAChannelNumber: System memory channel numbers. 4928 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4929 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4930 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4931 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4932 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4933 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4934 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4935 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4936 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4937 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4938 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4939 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4940 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4941 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4942 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4943 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4944 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4945 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4946 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4947 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4948 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4949 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4950 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4951 **********************************************************************************************************************/ 4952 4953 // this Table is used for Liano/Ontario APU 4954 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4955 { 4956 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4957 ULONG ulPowerplayTable[128]; 4958 }ATOM_FUSION_SYSTEM_INFO_V1; 4959 4960 4961 typedef struct _ATOM_TDP_CONFIG_BITS 4962 { 4963 #if ATOM_BIG_ENDIAN 4964 ULONG uReserved:2; 4965 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4966 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4967 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4968 #else 4969 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4970 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4971 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4972 ULONG uReserved:2; 4973 #endif 4974 }ATOM_TDP_CONFIG_BITS; 4975 4976 typedef union _ATOM_TDP_CONFIG 4977 { 4978 ATOM_TDP_CONFIG_BITS TDP_config; 4979 ULONG TDP_config_all; 4980 }ATOM_TDP_CONFIG; 4981 4982 /********************************************************************************************************************** 4983 ATOM_FUSION_SYSTEM_INFO_V1 Description 4984 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4985 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4986 **********************************************************************************************************************/ 4987 4988 // this IntegrateSystemInfoTable is used for Trinity APU 4989 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4990 { 4991 ATOM_COMMON_TABLE_HEADER sHeader; 4992 ULONG ulBootUpEngineClock; 4993 ULONG ulDentistVCOFreq; 4994 ULONG ulBootUpUMAClock; 4995 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4996 ULONG ulBootUpReqDisplayVector; 4997 ULONG ulOtherDisplayMisc; 4998 ULONG ulGPUCapInfo; 4999 ULONG ulSB_MMIO_Base_Addr; 5000 USHORT usRequestedPWMFreqInHz; 5001 UCHAR ucHtcTmpLmt; 5002 UCHAR ucHtcHystLmt; 5003 ULONG ulMinEngineClock; 5004 ULONG ulSystemConfig; 5005 ULONG ulCPUCapInfo; 5006 USHORT usNBP0Voltage; 5007 USHORT usNBP1Voltage; 5008 USHORT usBootUpNBVoltage; 5009 USHORT usExtDispConnInfoOffset; 5010 USHORT usPanelRefreshRateRange; 5011 UCHAR ucMemoryType; 5012 UCHAR ucUMAChannelNumber; 5013 UCHAR strVBIOSMsg[40]; 5014 ATOM_TDP_CONFIG asTdpConfig; 5015 ULONG ulReserved[19]; 5016 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5017 ULONG ulGMCRestoreResetTime; 5018 ULONG ulMinimumNClk; 5019 ULONG ulIdleNClk; 5020 ULONG ulDDR_DLL_PowerUpTime; 5021 ULONG ulDDR_PLL_PowerUpTime; 5022 USHORT usPCIEClkSSPercentage; 5023 USHORT usPCIEClkSSType; 5024 USHORT usLvdsSSPercentage; 5025 USHORT usLvdsSSpreadRateIn10Hz; 5026 USHORT usHDMISSPercentage; 5027 USHORT usHDMISSpreadRateIn10Hz; 5028 USHORT usDVISSPercentage; 5029 USHORT usDVISSpreadRateIn10Hz; 5030 ULONG SclkDpmBoostMargin; 5031 ULONG SclkDpmThrottleMargin; 5032 USHORT SclkDpmTdpLimitPG; 5033 USHORT SclkDpmTdpLimitBoost; 5034 ULONG ulBoostEngineCLock; 5035 UCHAR ulBoostVid_2bit; 5036 UCHAR EnableBoost; 5037 USHORT GnbTdpLimit; 5038 USHORT usMaxLVDSPclkFreqInSingleLink; 5039 UCHAR ucLvdsMisc; 5040 UCHAR ucTravisLVDSVolAdjust; 5041 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5042 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5043 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5044 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5045 UCHAR ucLVDSOffToOnDelay_in4Ms; 5046 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5047 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5048 UCHAR ucMinAllowedBL_Level; 5049 ULONG ulLCDBitDepthControlVal; 5050 ULONG ulNbpStateMemclkFreq[4]; 5051 USHORT usNBP2Voltage; 5052 USHORT usNBP3Voltage; 5053 ULONG ulNbpStateNClkFreq[4]; 5054 UCHAR ucNBDPMEnable; 5055 UCHAR ucReserved[3]; 5056 UCHAR ucDPMState0VclkFid; 5057 UCHAR ucDPMState0DclkFid; 5058 UCHAR ucDPMState1VclkFid; 5059 UCHAR ucDPMState1DclkFid; 5060 UCHAR ucDPMState2VclkFid; 5061 UCHAR ucDPMState2DclkFid; 5062 UCHAR ucDPMState3VclkFid; 5063 UCHAR ucDPMState3DclkFid; 5064 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5065 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5066 5067 // ulOtherDisplayMisc 5068 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5069 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5070 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5071 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5072 5073 // ulGPUCapInfo 5074 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5075 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 5076 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 5077 #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 5078 5079 /********************************************************************************************************************** 5080 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 5081 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5082 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5083 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5084 sDISPCLK_Voltage: Report Display clock voltage requirement. 5085 5086 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5087 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5088 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5089 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5090 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5091 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5092 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5093 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5094 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5095 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5096 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5097 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5098 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5099 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5100 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5101 bit[3]=0: VBIOS fast boot is disable 5102 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5103 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5104 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5105 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 5106 =1: DP mode use single PLL mode 5107 bit[3]=0: Enable AUX HW mode detection logic 5108 =1: Disable AUX HW mode detection logic 5109 5110 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5111 5112 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5113 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5114 5115 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5116 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5117 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5118 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5119 and enabling VariBri under the driver environment from PP table is optional. 5120 5121 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5122 that BL control from GPU is expected. 5123 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5124 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5125 it's per platform 5126 and enabling VariBri under the driver environment from PP table is optional. 5127 5128 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5129 Threshold on value to enter HTC_active state. 5130 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5131 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5132 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5133 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5134 =1: PCIE Power Gating Enabled 5135 Bit[1]=0: DDR-DLL shut-down feature disabled. 5136 1: DDR-DLL shut-down feature enabled. 5137 Bit[2]=0: DDR-PLL Power down feature disabled. 5138 1: DDR-PLL Power down feature enabled. 5139 ulCPUCapInfo: TBD 5140 usNBP0Voltage: VID for voltage on NB P0 State 5141 usNBP1Voltage: VID for voltage on NB P1 State 5142 usNBP2Voltage: VID for voltage on NB P2 State 5143 usNBP3Voltage: VID for voltage on NB P3 State 5144 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5145 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5146 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5147 to indicate a range. 5148 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5149 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5150 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5151 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5152 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5153 ucUMAChannelNumber: System memory channel numbers. 5154 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5155 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5156 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5157 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5158 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5159 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5160 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5161 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5162 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5163 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5164 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5165 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5166 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5167 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5168 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5169 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5170 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5171 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5172 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5173 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5174 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5175 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5176 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5177 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5178 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5179 value to program Travis register LVDS_CTRL_4 5180 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5181 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5182 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5183 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5184 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5185 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5186 5187 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5188 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5189 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5190 5191 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5192 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5193 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5194 5195 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5196 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5197 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5198 5199 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5200 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5201 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5202 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5203 5204 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5205 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5206 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5207 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5208 5209 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5210 5211 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 5212 5213 **********************************************************************************************************************/ 5214 5215 // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 5216 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 5217 { 5218 ATOM_COMMON_TABLE_HEADER sHeader; 5219 ULONG ulBootUpEngineClock; 5220 ULONG ulDentistVCOFreq; 5221 ULONG ulBootUpUMAClock; 5222 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5223 ULONG ulBootUpReqDisplayVector; 5224 ULONG ulVBIOSMisc; 5225 ULONG ulGPUCapInfo; 5226 ULONG ulDISP_CLK2Freq; 5227 USHORT usRequestedPWMFreqInHz; 5228 UCHAR ucHtcTmpLmt; 5229 UCHAR ucHtcHystLmt; 5230 ULONG ulReserved2; 5231 ULONG ulSystemConfig; 5232 ULONG ulCPUCapInfo; 5233 ULONG ulReserved3; 5234 USHORT usGPUReservedSysMemSize; 5235 USHORT usExtDispConnInfoOffset; 5236 USHORT usPanelRefreshRateRange; 5237 UCHAR ucMemoryType; 5238 UCHAR ucUMAChannelNumber; 5239 UCHAR strVBIOSMsg[40]; 5240 ATOM_TDP_CONFIG asTdpConfig; 5241 ULONG ulReserved[19]; 5242 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5243 ULONG ulGMCRestoreResetTime; 5244 ULONG ulReserved4; 5245 ULONG ulIdleNClk; 5246 ULONG ulDDR_DLL_PowerUpTime; 5247 ULONG ulDDR_PLL_PowerUpTime; 5248 USHORT usPCIEClkSSPercentage; 5249 USHORT usPCIEClkSSType; 5250 USHORT usLvdsSSPercentage; 5251 USHORT usLvdsSSpreadRateIn10Hz; 5252 USHORT usHDMISSPercentage; 5253 USHORT usHDMISSpreadRateIn10Hz; 5254 USHORT usDVISSPercentage; 5255 USHORT usDVISSpreadRateIn10Hz; 5256 ULONG ulGPUReservedSysMemBaseAddrLo; 5257 ULONG ulGPUReservedSysMemBaseAddrHi; 5258 ULONG ulReserved5[3]; 5259 USHORT usMaxLVDSPclkFreqInSingleLink; 5260 UCHAR ucLvdsMisc; 5261 UCHAR ucTravisLVDSVolAdjust; 5262 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5263 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5264 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5265 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5266 UCHAR ucLVDSOffToOnDelay_in4Ms; 5267 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5268 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5269 UCHAR ucMinAllowedBL_Level; 5270 ULONG ulLCDBitDepthControlVal; 5271 ULONG ulNbpStateMemclkFreq[4]; 5272 ULONG ulReserved6; 5273 ULONG ulNbpStateNClkFreq[4]; 5274 USHORT usNBPStateVoltage[4]; 5275 USHORT usBootUpNBVoltage; 5276 USHORT usReserved2; 5277 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5278 }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 5279 5280 /********************************************************************************************************************** 5281 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 5282 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5283 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5284 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5285 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 5286 5287 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5288 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5289 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5290 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5291 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5292 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5293 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5294 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5295 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5296 5297 ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 5298 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5299 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5300 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5301 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5302 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5303 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5304 bit[3]=0: VBIOS fast boot is disable 5305 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5306 5307 ulGPUCapInfo: bit[0~2]= Reserved 5308 bit[3]=0: Enable AUX HW mode detection logic 5309 =1: Disable AUX HW mode detection logic 5310 bit[4]=0: Disable DFS bypass feature 5311 =1: Enable DFS bypass feature 5312 5313 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5314 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5315 5316 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5317 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5318 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5319 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5320 and enabling VariBri under the driver environment from PP table is optional. 5321 5322 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5323 that BL control from GPU is expected. 5324 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5325 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5326 it's per platform 5327 and enabling VariBri under the driver environment from PP table is optional. 5328 5329 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 5330 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5331 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5332 5333 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5334 =1: PCIE Power Gating Enabled 5335 Bit[1]=0: DDR-DLL shut-down feature disabled. 5336 1: DDR-DLL shut-down feature enabled. 5337 Bit[2]=0: DDR-PLL Power down feature disabled. 5338 1: DDR-PLL Power down feature enabled. 5339 Bit[3]=0: GNB DPM is disabled 5340 =1: GNB DPM is enabled 5341 ulCPUCapInfo: TBD 5342 5343 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5344 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5345 to indicate a range. 5346 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5347 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5348 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5349 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5350 5351 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 5352 ucUMAChannelNumber: System memory channel numbers. 5353 5354 strVBIOSMsg[40]: VBIOS boot up customized message string 5355 5356 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5357 5358 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5359 ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 5360 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5361 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5362 5363 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5364 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5365 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5366 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5367 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5368 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5369 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5370 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5371 5372 usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 5373 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 5374 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 5375 5376 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5377 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5378 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5379 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5380 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5381 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5382 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5383 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5384 value to program Travis register LVDS_CTRL_4 5385 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 5386 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5387 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5388 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5389 ucLVDSPwrOnDEtoVARY_BL_in4Ms: 5390 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5391 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5392 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5393 ucLVDSPwrOffVARY_BLtoDE_in4Ms: 5394 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5395 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5396 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5397 ucLVDSPwrOffDEtoDIGON_in4Ms: 5398 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5399 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5400 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5401 ucLVDSOffToOnDelay_in4Ms: 5402 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5403 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5404 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5405 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5406 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5407 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5408 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5409 5410 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5411 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5412 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5413 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5414 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5415 5416 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 5417 5418 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 5419 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 5420 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 5421 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 5422 sExtDispConnInfo: Display connector information table provided to VBIOS 5423 5424 **********************************************************************************************************************/ 5425 5426 // this Table is used for Kaveri/Kabini APU 5427 typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 5428 { 5429 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 5430 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 5431 }ATOM_FUSION_SYSTEM_INFO_V2; 5432 5433 5434 /**************************************************************************/ 5435 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 5436 //Memory SS Info Table 5437 //Define Memory Clock SS chip ID 5438 #define ICS91719 1 5439 #define ICS91720 2 5440 5441 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 5442 typedef struct _ATOM_I2C_DATA_RECORD 5443 { 5444 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 5445 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 5446 }ATOM_I2C_DATA_RECORD; 5447 5448 5449 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 5450 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 5451 { 5452 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 5453 UCHAR ucSSChipID; //SS chip being used 5454 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5455 UCHAR ucNumOfI2CDataRecords; //number of data block 5456 ATOM_I2C_DATA_RECORD asI2CData[1]; 5457 }ATOM_I2C_DEVICE_SETUP_INFO; 5458 5459 //========================================================================================== 5460 typedef struct _ATOM_ASIC_MVDD_INFO 5461 { 5462 ATOM_COMMON_TABLE_HEADER sHeader; 5463 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5464 }ATOM_ASIC_MVDD_INFO; 5465 5466 //========================================================================================== 5467 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5468 5469 //========================================================================================== 5470 /**************************************************************************/ 5471 5472 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5473 { 5474 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5475 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5476 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5477 UCHAR ucClockIndication; //Indicate which clock source needs SS 5478 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5479 UCHAR ucReserved[2]; 5480 }ATOM_ASIC_SS_ASSIGNMENT; 5481 5482 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5483 //SS is not required or enabled if a match is not found. 5484 #define ASIC_INTERNAL_MEMORY_SS 1 5485 #define ASIC_INTERNAL_ENGINE_SS 2 5486 #define ASIC_INTERNAL_UVD_SS 3 5487 #define ASIC_INTERNAL_SS_ON_TMDS 4 5488 #define ASIC_INTERNAL_SS_ON_HDMI 5 5489 #define ASIC_INTERNAL_SS_ON_LVDS 6 5490 #define ASIC_INTERNAL_SS_ON_DP 7 5491 #define ASIC_INTERNAL_SS_ON_DCPLL 8 5492 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5493 #define ASIC_INTERNAL_VCE_SS 10 5494 #define ASIC_INTERNAL_GPUPLL_SS 11 5495 5496 5497 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5498 { 5499 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5500 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5501 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 5502 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5503 UCHAR ucClockIndication; //Indicate which clock source needs SS 5504 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5505 UCHAR ucReserved[2]; 5506 }ATOM_ASIC_SS_ASSIGNMENT_V2; 5507 5508 //ucSpreadSpectrumMode 5509 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5510 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5511 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5512 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5513 //#define ATOM_INTERNAL_SS_MASK 0x00000000 5514 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 5515 5516 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5517 { 5518 ATOM_COMMON_TABLE_HEADER sHeader; 5519 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5520 }ATOM_ASIC_INTERNAL_SS_INFO; 5521 5522 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5523 { 5524 ATOM_COMMON_TABLE_HEADER sHeader; 5525 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5526 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 5527 5528 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5529 { 5530 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5531 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5532 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5533 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5534 UCHAR ucClockIndication; //Indicate which clock source needs SS 5535 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5536 UCHAR ucReserved[2]; 5537 }ATOM_ASIC_SS_ASSIGNMENT_V3; 5538 5539 //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 5540 #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 5541 #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 5542 #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 5543 5544 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5545 { 5546 ATOM_COMMON_TABLE_HEADER sHeader; 5547 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5548 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 5549 5550 5551 //==============================Scratch Pad Definition Portion=============================== 5552 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 5553 #define ATOM_ROM_LOCATION_DEF 1 5554 #define ATOM_TV_STANDARD_DEF 2 5555 #define ATOM_ACTIVE_INFO_DEF 3 5556 #define ATOM_LCD_INFO_DEF 4 5557 #define ATOM_DOS_REQ_INFO_DEF 5 5558 #define ATOM_ACC_CHANGE_INFO_DEF 6 5559 #define ATOM_DOS_MODE_INFO_DEF 7 5560 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 5561 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5562 #define ATOM_INTERNAL_TIMER_DEF 10 5563 5564 // BIOS_0_SCRATCH Definition 5565 #define ATOM_S0_CRT1_MONO 0x00000001L 5566 #define ATOM_S0_CRT1_COLOR 0x00000002L 5567 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5568 5569 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5570 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5571 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5572 5573 #define ATOM_S0_CV_A 0x00000010L 5574 #define ATOM_S0_CV_DIN_A 0x00000020L 5575 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5576 5577 5578 #define ATOM_S0_CRT2_MONO 0x00000100L 5579 #define ATOM_S0_CRT2_COLOR 0x00000200L 5580 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5581 5582 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 5583 #define ATOM_S0_TV1_SVIDEO 0x00000800L 5584 #define ATOM_S0_TV1_SCART 0x00004000L 5585 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5586 5587 #define ATOM_S0_CV 0x00001000L 5588 #define ATOM_S0_CV_DIN 0x00002000L 5589 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5590 5591 #define ATOM_S0_DFP1 0x00010000L 5592 #define ATOM_S0_DFP2 0x00020000L 5593 #define ATOM_S0_LCD1 0x00040000L 5594 #define ATOM_S0_LCD2 0x00080000L 5595 #define ATOM_S0_DFP6 0x00100000L 5596 #define ATOM_S0_DFP3 0x00200000L 5597 #define ATOM_S0_DFP4 0x00400000L 5598 #define ATOM_S0_DFP5 0x00800000L 5599 5600 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5601 5602 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5603 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5604 5605 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5606 #define ATOM_S0_THERMAL_STATE_SHIFT 26 5607 5608 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5609 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5610 5611 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5612 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5613 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5614 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5615 5616 //Byte aligned definition for BIOS usage 5617 #define ATOM_S0_CRT1_MONOb0 0x01 5618 #define ATOM_S0_CRT1_COLORb0 0x02 5619 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5620 5621 #define ATOM_S0_TV1_COMPOSITEb0 0x04 5622 #define ATOM_S0_TV1_SVIDEOb0 0x08 5623 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5624 5625 #define ATOM_S0_CVb0 0x10 5626 #define ATOM_S0_CV_DINb0 0x20 5627 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5628 5629 #define ATOM_S0_CRT2_MONOb1 0x01 5630 #define ATOM_S0_CRT2_COLORb1 0x02 5631 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5632 5633 #define ATOM_S0_TV1_COMPOSITEb1 0x04 5634 #define ATOM_S0_TV1_SVIDEOb1 0x08 5635 #define ATOM_S0_TV1_SCARTb1 0x40 5636 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5637 5638 #define ATOM_S0_CVb1 0x10 5639 #define ATOM_S0_CV_DINb1 0x20 5640 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5641 5642 #define ATOM_S0_DFP1b2 0x01 5643 #define ATOM_S0_DFP2b2 0x02 5644 #define ATOM_S0_LCD1b2 0x04 5645 #define ATOM_S0_LCD2b2 0x08 5646 #define ATOM_S0_DFP6b2 0x10 5647 #define ATOM_S0_DFP3b2 0x20 5648 #define ATOM_S0_DFP4b2 0x40 5649 #define ATOM_S0_DFP5b2 0x80 5650 5651 5652 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5653 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5654 5655 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5656 #define ATOM_S0_LCD1_SHIFT 18 5657 5658 // BIOS_1_SCRATCH Definition 5659 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5660 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5661 5662 // BIOS_2_SCRATCH Definition 5663 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5664 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5665 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5666 5667 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5668 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5669 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5670 5671 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5672 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5673 5674 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5675 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5676 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5677 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5678 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5679 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5680 5681 5682 //Byte aligned definition for BIOS usage 5683 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5684 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5685 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5686 5687 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5688 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5689 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5690 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5691 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5692 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5693 5694 5695 // BIOS_3_SCRATCH Definition 5696 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 5697 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 5698 #define ATOM_S3_TV1_ACTIVE 0x00000004L 5699 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 5700 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 5701 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 5702 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 5703 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 5704 #define ATOM_S3_CV_ACTIVE 0x00000100L 5705 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 5706 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 5707 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 5708 5709 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5710 5711 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5712 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5713 5714 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5715 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5716 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5717 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5718 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5719 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5720 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5721 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5722 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5723 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5724 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5725 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5726 5727 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5728 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5729 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 5730 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5731 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5732 5733 //Byte aligned definition for BIOS usage 5734 #define ATOM_S3_CRT1_ACTIVEb0 0x01 5735 #define ATOM_S3_LCD1_ACTIVEb0 0x02 5736 #define ATOM_S3_TV1_ACTIVEb0 0x04 5737 #define ATOM_S3_DFP1_ACTIVEb0 0x08 5738 #define ATOM_S3_CRT2_ACTIVEb0 0x10 5739 #define ATOM_S3_LCD2_ACTIVEb0 0x20 5740 #define ATOM_S3_DFP6_ACTIVEb0 0x40 5741 #define ATOM_S3_DFP2_ACTIVEb0 0x80 5742 #define ATOM_S3_CV_ACTIVEb1 0x01 5743 #define ATOM_S3_DFP3_ACTIVEb1 0x02 5744 #define ATOM_S3_DFP4_ACTIVEb1 0x04 5745 #define ATOM_S3_DFP5_ACTIVEb1 0x08 5746 5747 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5748 5749 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5750 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5751 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5752 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5753 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5754 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5755 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5756 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5757 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5758 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5759 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5760 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5761 5762 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5763 5764 // BIOS_4_SCRATCH Definition 5765 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5766 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5767 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 5768 5769 //Byte aligned definition for BIOS usage 5770 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5771 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5772 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5773 5774 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5775 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 5776 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 5777 #define ATOM_S5_DOS_REQ_TV1b0 0x04 5778 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 5779 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 5780 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 5781 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 5782 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 5783 #define ATOM_S5_DOS_REQ_CVb1 0x01 5784 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 5785 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 5786 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 5787 5788 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5789 5790 #define ATOM_S5_DOS_REQ_CRT1 0x0001 5791 #define ATOM_S5_DOS_REQ_LCD1 0x0002 5792 #define ATOM_S5_DOS_REQ_TV1 0x0004 5793 #define ATOM_S5_DOS_REQ_DFP1 0x0008 5794 #define ATOM_S5_DOS_REQ_CRT2 0x0010 5795 #define ATOM_S5_DOS_REQ_LCD2 0x0020 5796 #define ATOM_S5_DOS_REQ_DFP6 0x0040 5797 #define ATOM_S5_DOS_REQ_DFP2 0x0080 5798 #define ATOM_S5_DOS_REQ_CV 0x0100 5799 #define ATOM_S5_DOS_REQ_DFP3 0x0200 5800 #define ATOM_S5_DOS_REQ_DFP4 0x0400 5801 #define ATOM_S5_DOS_REQ_DFP5 0x0800 5802 5803 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5804 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5805 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5806 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5807 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5808 (ATOM_S5_DOS_FORCE_CVb3<<8)) 5809 5810 // BIOS_6_SCRATCH Definition 5811 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 5812 #define ATOM_S6_SCALER_CHANGE 0x00000002L 5813 #define ATOM_S6_LID_CHANGE 0x00000004L 5814 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 5815 #define ATOM_S6_ACC_MODE 0x00000010L 5816 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5817 #define ATOM_S6_LID_STATE 0x00000040L 5818 #define ATOM_S6_DOCK_STATE 0x00000080L 5819 #define ATOM_S6_CRITICAL_STATE 0x00000100L 5820 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5821 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5822 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5823 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5824 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5825 5826 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5827 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5828 5829 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5830 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5831 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 5832 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5833 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5834 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5835 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5836 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5837 #define ATOM_S6_ACC_REQ_CV 0x01000000L 5838 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5839 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5840 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5841 5842 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5843 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5844 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5845 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5846 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5847 5848 //Byte aligned definition for BIOS usage 5849 #define ATOM_S6_DEVICE_CHANGEb0 0x01 5850 #define ATOM_S6_SCALER_CHANGEb0 0x02 5851 #define ATOM_S6_LID_CHANGEb0 0x04 5852 #define ATOM_S6_DOCKING_CHANGEb0 0x08 5853 #define ATOM_S6_ACC_MODEb0 0x10 5854 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5855 #define ATOM_S6_LID_STATEb0 0x40 5856 #define ATOM_S6_DOCK_STATEb0 0x80 5857 #define ATOM_S6_CRITICAL_STATEb1 0x01 5858 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5859 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5860 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5861 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5862 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5863 5864 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 5865 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 5866 #define ATOM_S6_ACC_REQ_TV1b2 0x04 5867 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 5868 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 5869 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 5870 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 5871 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 5872 #define ATOM_S6_ACC_REQ_CVb3 0x01 5873 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 5874 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 5875 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 5876 5877 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5878 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5879 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5880 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5881 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5882 5883 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5884 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 5885 #define ATOM_S6_LID_CHANGE_SHIFT 2 5886 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5887 #define ATOM_S6_ACC_MODE_SHIFT 4 5888 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5889 #define ATOM_S6_LID_STATE_SHIFT 6 5890 #define ATOM_S6_DOCK_STATE_SHIFT 7 5891 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 5892 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5893 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5894 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5895 #define ATOM_S6_REQ_SCALER_SHIFT 12 5896 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5897 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5898 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5899 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5900 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5901 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5902 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5903 5904 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5905 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 5906 #define ATOM_S7_DOS_MODE_VGAb0 0x00 5907 #define ATOM_S7_DOS_MODE_VESAb0 0x01 5908 #define ATOM_S7_DOS_MODE_EXTb0 0x02 5909 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5910 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5911 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5912 #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 5913 #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 5914 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5915 5916 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5917 5918 // BIOS_8_SCRATCH Definition 5919 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5920 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5921 5922 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5923 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5924 5925 // BIOS_9_SCRATCH Definition 5926 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5927 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5928 #endif 5929 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5930 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5931 #endif 5932 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5933 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5934 #endif 5935 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5936 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5937 #endif 5938 5939 5940 #define ATOM_FLAG_SET 0x20 5941 #define ATOM_FLAG_CLEAR 0 5942 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5943 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5944 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5945 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5946 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5947 5948 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5949 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5950 5951 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5952 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5953 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5954 5955 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5956 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5957 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5958 5959 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5960 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5961 5962 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5963 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5964 5965 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5966 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5967 5968 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5969 5970 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5971 5972 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5973 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5974 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5975 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5976 5977 /****************************************************************************/ 5978 //Portion II: Definitinos only used in Driver 5979 /****************************************************************************/ 5980 5981 // Macros used by driver 5982 #ifdef __cplusplus 5983 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5984 5985 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5986 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5987 #else // not __cplusplus 5988 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 5989 5990 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5991 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5992 #endif // __cplusplus 5993 5994 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5995 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5996 5997 /****************************************************************************/ 5998 //Portion III: Definitinos only used in VBIOS 5999 /****************************************************************************/ 6000 #define ATOM_DAC_SRC 0x80 6001 #define ATOM_SRC_DAC1 0 6002 #define ATOM_SRC_DAC2 0x80 6003 6004 typedef struct _MEMORY_PLLINIT_PARAMETERS 6005 { 6006 ULONG ulTargetMemoryClock; //In 10Khz unit 6007 UCHAR ucAction; //not define yet 6008 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 6009 UCHAR ucFbDiv; //FB value 6010 UCHAR ucPostDiv; //Post div 6011 }MEMORY_PLLINIT_PARAMETERS; 6012 6013 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 6014 6015 6016 #define GPIO_PIN_WRITE 0x01 6017 #define GPIO_PIN_READ 0x00 6018 6019 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 6020 { 6021 UCHAR ucGPIO_ID; //return value, read from GPIO pins 6022 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 6023 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 6024 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 6025 }GPIO_PIN_CONTROL_PARAMETERS; 6026 6027 typedef struct _ENABLE_SCALER_PARAMETERS 6028 { 6029 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 6030 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 6031 UCHAR ucTVStandard; // 6032 UCHAR ucPadding[1]; 6033 }ENABLE_SCALER_PARAMETERS; 6034 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 6035 6036 //ucEnable: 6037 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 6038 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 6039 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 6040 #define SCALER_ENABLE_MULTITAP_MODE 3 6041 6042 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 6043 { 6044 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 6045 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 6046 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 6047 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 6048 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6049 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 6050 6051 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 6052 { 6053 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 6054 ENABLE_CRTC_PARAMETERS sReserved; 6055 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 6056 6057 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 6058 { 6059 USHORT usHight; // Image Hight 6060 USHORT usWidth; // Image Width 6061 UCHAR ucSurface; // Surface 1 or 2 6062 UCHAR ucPadding[3]; 6063 }ENABLE_GRAPH_SURFACE_PARAMETERS; 6064 6065 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 6066 { 6067 USHORT usHight; // Image Hight 6068 USHORT usWidth; // Image Width 6069 UCHAR ucSurface; // Surface 1 or 2 6070 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6071 UCHAR ucPadding[2]; 6072 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 6073 6074 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 6075 { 6076 USHORT usHight; // Image Hight 6077 USHORT usWidth; // Image Width 6078 UCHAR ucSurface; // Surface 1 or 2 6079 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6080 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 6081 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 6082 6083 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 6084 { 6085 USHORT usHight; // Image Hight 6086 USHORT usWidth; // Image Width 6087 USHORT usGraphPitch; 6088 UCHAR ucColorDepth; 6089 UCHAR ucPixelFormat; 6090 UCHAR ucSurface; // Surface 1 or 2 6091 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6092 UCHAR ucModeType; 6093 UCHAR ucReserved; 6094 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 6095 6096 // ucEnable 6097 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 6098 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 6099 6100 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 6101 { 6102 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 6103 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 6104 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 6105 6106 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 6107 { 6108 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 6109 USHORT usMemorySize; //8Kb blocks aligned 6110 }MEMORY_CLEAN_UP_PARAMETERS; 6111 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 6112 6113 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 6114 { 6115 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6116 USHORT usY_Size; 6117 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 6118 6119 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 6120 { 6121 union{ 6122 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6123 USHORT usSurface; 6124 }; 6125 USHORT usY_Size; 6126 USHORT usDispXStart; 6127 USHORT usDispYStart; 6128 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 6129 6130 6131 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 6132 { 6133 UCHAR ucLutId; 6134 UCHAR ucAction; 6135 USHORT usLutStartIndex; 6136 USHORT usLutLength; 6137 USHORT usLutOffsetInVram; 6138 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 6139 6140 // ucAction: 6141 #define PALETTE_DATA_AUTO_FILL 1 6142 #define PALETTE_DATA_READ 2 6143 #define PALETTE_DATA_WRITE 3 6144 6145 6146 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 6147 { 6148 UCHAR ucInterruptId; 6149 UCHAR ucServiceId; 6150 UCHAR ucStatus; 6151 UCHAR ucReserved; 6152 }INTERRUPT_SERVICE_PARAMETER_V2; 6153 6154 // ucInterruptId 6155 #define HDP1_INTERRUPT_ID 1 6156 #define HDP2_INTERRUPT_ID 2 6157 #define HDP3_INTERRUPT_ID 3 6158 #define HDP4_INTERRUPT_ID 4 6159 #define HDP5_INTERRUPT_ID 5 6160 #define HDP6_INTERRUPT_ID 6 6161 #define SW_INTERRUPT_ID 11 6162 6163 // ucAction 6164 #define INTERRUPT_SERVICE_GEN_SW_INT 1 6165 #define INTERRUPT_SERVICE_GET_STATUS 2 6166 6167 // ucStatus 6168 #define INTERRUPT_STATUS__INT_TRIGGER 1 6169 #define INTERRUPT_STATUS__HPD_HIGH 2 6170 6171 typedef struct _INDIRECT_IO_ACCESS 6172 { 6173 ATOM_COMMON_TABLE_HEADER sHeader; 6174 UCHAR IOAccessSequence[256]; 6175 } INDIRECT_IO_ACCESS; 6176 6177 #define INDIRECT_READ 0x00 6178 #define INDIRECT_WRITE 0x80 6179 6180 #define INDIRECT_IO_MM 0 6181 #define INDIRECT_IO_PLL 1 6182 #define INDIRECT_IO_MC 2 6183 #define INDIRECT_IO_PCIE 3 6184 #define INDIRECT_IO_PCIEP 4 6185 #define INDIRECT_IO_NBMISC 5 6186 #define INDIRECT_IO_SMU 5 6187 6188 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 6189 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 6190 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 6191 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 6192 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 6193 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 6194 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 6195 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 6196 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 6197 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 6198 #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 6199 #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 6200 6201 typedef struct _ATOM_OEM_INFO 6202 { 6203 ATOM_COMMON_TABLE_HEADER sHeader; 6204 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6205 }ATOM_OEM_INFO; 6206 6207 typedef struct _ATOM_TV_MODE 6208 { 6209 UCHAR ucVMode_Num; //Video mode number 6210 UCHAR ucTV_Mode_Num; //Internal TV mode number 6211 }ATOM_TV_MODE; 6212 6213 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 6214 { 6215 ATOM_COMMON_TABLE_HEADER sHeader; 6216 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 6217 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 6218 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 6219 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6220 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6221 }ATOM_BIOS_INT_TVSTD_MODE; 6222 6223 6224 typedef struct _ATOM_TV_MODE_SCALER_PTR 6225 { 6226 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 6227 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 6228 UCHAR ucTV_Mode_Num; 6229 }ATOM_TV_MODE_SCALER_PTR; 6230 6231 typedef struct _ATOM_STANDARD_VESA_TIMING 6232 { 6233 ATOM_COMMON_TABLE_HEADER sHeader; 6234 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 6235 }ATOM_STANDARD_VESA_TIMING; 6236 6237 6238 typedef struct _ATOM_STD_FORMAT 6239 { 6240 USHORT usSTD_HDisp; 6241 USHORT usSTD_VDisp; 6242 USHORT usSTD_RefreshRate; 6243 USHORT usReserved; 6244 }ATOM_STD_FORMAT; 6245 6246 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 6247 { 6248 USHORT usVESA_ModeNumber; 6249 USHORT usExtendedModeNumber; 6250 }ATOM_VESA_TO_EXTENDED_MODE; 6251 6252 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 6253 { 6254 ATOM_COMMON_TABLE_HEADER sHeader; 6255 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 6256 }ATOM_VESA_TO_INTENAL_MODE_LUT; 6257 6258 /*************** ATOM Memory Related Data Structure ***********************/ 6259 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 6260 UCHAR ucMemoryType; 6261 UCHAR ucMemoryVendor; 6262 UCHAR ucAdjMCId; 6263 UCHAR ucDynClkId; 6264 ULONG ulDllResetClkRange; 6265 }ATOM_MEMORY_VENDOR_BLOCK; 6266 6267 6268 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 6269 #if ATOM_BIG_ENDIAN 6270 ULONG ucMemBlkId:8; 6271 ULONG ulMemClockRange:24; 6272 #else 6273 ULONG ulMemClockRange:24; 6274 ULONG ucMemBlkId:8; 6275 #endif 6276 }ATOM_MEMORY_SETTING_ID_CONFIG; 6277 6278 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 6279 { 6280 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 6281 ULONG ulAccess; 6282 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 6283 6284 6285 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 6286 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 6287 ULONG aulMemData[1]; 6288 }ATOM_MEMORY_SETTING_DATA_BLOCK; 6289 6290 6291 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 6292 USHORT usRegIndex; // MC register index 6293 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 6294 }ATOM_INIT_REG_INDEX_FORMAT; 6295 6296 6297 typedef struct _ATOM_INIT_REG_BLOCK{ 6298 USHORT usRegIndexTblSize; //size of asRegIndexBuf 6299 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 6300 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 6301 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 6302 }ATOM_INIT_REG_BLOCK; 6303 6304 #define END_OF_REG_INDEX_BLOCK 0x0ffff 6305 #define END_OF_REG_DATA_BLOCK 0x00000000 6306 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 6307 #define CLOCK_RANGE_HIGHEST 0x00ffffff 6308 6309 #define VALUE_DWORD SIZEOF ULONG 6310 #define VALUE_SAME_AS_ABOVE 0 6311 #define VALUE_MASK_DWORD 0x84 6312 6313 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 6314 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 6315 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 6316 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 6317 #define ACCESS_PLACEHOLDER 0x80 6318 6319 typedef struct _ATOM_MC_INIT_PARAM_TABLE 6320 { 6321 ATOM_COMMON_TABLE_HEADER sHeader; 6322 USHORT usAdjustARB_SEQDataOffset; 6323 USHORT usMCInitMemTypeTblOffset; 6324 USHORT usMCInitCommonTblOffset; 6325 USHORT usMCInitPowerDownTblOffset; 6326 ULONG ulARB_SEQDataBuf[32]; 6327 ATOM_INIT_REG_BLOCK asMCInitMemType; 6328 ATOM_INIT_REG_BLOCK asMCInitCommon; 6329 }ATOM_MC_INIT_PARAM_TABLE; 6330 6331 6332 #define _4Mx16 0x2 6333 #define _4Mx32 0x3 6334 #define _8Mx16 0x12 6335 #define _8Mx32 0x13 6336 #define _16Mx16 0x22 6337 #define _16Mx32 0x23 6338 #define _32Mx16 0x32 6339 #define _32Mx32 0x33 6340 #define _64Mx8 0x41 6341 #define _64Mx16 0x42 6342 #define _64Mx32 0x43 6343 #define _128Mx8 0x51 6344 #define _128Mx16 0x52 6345 #define _128Mx32 0x53 6346 #define _256Mx8 0x61 6347 #define _256Mx16 0x62 6348 #define _512Mx8 0x71 6349 6350 #define SAMSUNG 0x1 6351 #define INFINEON 0x2 6352 #define ELPIDA 0x3 6353 #define ETRON 0x4 6354 #define NANYA 0x5 6355 #define HYNIX 0x6 6356 #define MOSEL 0x7 6357 #define WINBOND 0x8 6358 #define ESMT 0x9 6359 #define MICRON 0xF 6360 6361 #define QIMONDA INFINEON 6362 #define PROMOS MOSEL 6363 #define KRETON INFINEON 6364 #define ELIXIR NANYA 6365 #define MEZZA ELPIDA 6366 6367 6368 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 6369 6370 #define UCODE_ROM_START_ADDRESS 0x1b800 6371 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 6372 6373 //uCode block header for reference 6374 6375 typedef struct _MCuCodeHeader 6376 { 6377 ULONG ulSignature; 6378 UCHAR ucRevision; 6379 UCHAR ucChecksum; 6380 UCHAR ucReserved1; 6381 UCHAR ucReserved2; 6382 USHORT usParametersLength; 6383 USHORT usUCodeLength; 6384 USHORT usReserved1; 6385 USHORT usReserved2; 6386 } MCuCodeHeader; 6387 6388 ////////////////////////////////////////////////////////////////////////////////// 6389 6390 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 6391 6392 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 6393 typedef struct _ATOM_VRAM_MODULE_V1 6394 { 6395 ULONG ulReserved; 6396 USHORT usEMRSValue; 6397 USHORT usMRSValue; 6398 USHORT usReserved; 6399 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6400 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 6401 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 6402 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6403 UCHAR ucRow; // Number of Row,in power of 2; 6404 UCHAR ucColumn; // Number of Column,in power of 2; 6405 UCHAR ucBank; // Nunber of Bank; 6406 UCHAR ucRank; // Number of Rank, in power of 2 6407 UCHAR ucChannelNum; // Number of channel; 6408 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6409 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6410 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6411 UCHAR ucReserved[2]; 6412 }ATOM_VRAM_MODULE_V1; 6413 6414 6415 typedef struct _ATOM_VRAM_MODULE_V2 6416 { 6417 ULONG ulReserved; 6418 ULONG ulFlags; // To enable/disable functionalities based on memory type 6419 ULONG ulEngineClock; // Override of default engine clock for particular memory type 6420 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 6421 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6422 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6423 USHORT usEMRSValue; 6424 USHORT usMRSValue; 6425 USHORT usReserved; 6426 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6427 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6428 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6429 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6430 UCHAR ucRow; // Number of Row,in power of 2; 6431 UCHAR ucColumn; // Number of Column,in power of 2; 6432 UCHAR ucBank; // Nunber of Bank; 6433 UCHAR ucRank; // Number of Rank, in power of 2 6434 UCHAR ucChannelNum; // Number of channel; 6435 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6436 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6437 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6438 UCHAR ucRefreshRateFactor; 6439 UCHAR ucReserved[3]; 6440 }ATOM_VRAM_MODULE_V2; 6441 6442 6443 typedef struct _ATOM_MEMORY_TIMING_FORMAT 6444 { 6445 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6446 union{ 6447 USHORT usMRS; // mode register 6448 USHORT usDDR3_MR0; 6449 }; 6450 union{ 6451 USHORT usEMRS; // extended mode register 6452 USHORT usDDR3_MR1; 6453 }; 6454 UCHAR ucCL; // CAS latency 6455 UCHAR ucWL; // WRITE Latency 6456 UCHAR uctRAS; // tRAS 6457 UCHAR uctRC; // tRC 6458 UCHAR uctRFC; // tRFC 6459 UCHAR uctRCDR; // tRCDR 6460 UCHAR uctRCDW; // tRCDW 6461 UCHAR uctRP; // tRP 6462 UCHAR uctRRD; // tRRD 6463 UCHAR uctWR; // tWR 6464 UCHAR uctWTR; // tWTR 6465 UCHAR uctPDIX; // tPDIX 6466 UCHAR uctFAW; // tFAW 6467 UCHAR uctAOND; // tAOND 6468 union 6469 { 6470 struct { 6471 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6472 UCHAR ucReserved; 6473 }; 6474 USHORT usDDR3_MR2; 6475 }; 6476 }ATOM_MEMORY_TIMING_FORMAT; 6477 6478 6479 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6480 { 6481 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6482 USHORT usMRS; // mode register 6483 USHORT usEMRS; // extended mode register 6484 UCHAR ucCL; // CAS latency 6485 UCHAR ucWL; // WRITE Latency 6486 UCHAR uctRAS; // tRAS 6487 UCHAR uctRC; // tRC 6488 UCHAR uctRFC; // tRFC 6489 UCHAR uctRCDR; // tRCDR 6490 UCHAR uctRCDW; // tRCDW 6491 UCHAR uctRP; // tRP 6492 UCHAR uctRRD; // tRRD 6493 UCHAR uctWR; // tWR 6494 UCHAR uctWTR; // tWTR 6495 UCHAR uctPDIX; // tPDIX 6496 UCHAR uctFAW; // tFAW 6497 UCHAR uctAOND; // tAOND 6498 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6499 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6500 UCHAR uctCCDL; // 6501 UCHAR uctCRCRL; // 6502 UCHAR uctCRCWL; // 6503 UCHAR uctCKE; // 6504 UCHAR uctCKRSE; // 6505 UCHAR uctCKRSX; // 6506 UCHAR uctFAW32; // 6507 UCHAR ucMR5lo; // 6508 UCHAR ucMR5hi; // 6509 UCHAR ucTerminator; 6510 }ATOM_MEMORY_TIMING_FORMAT_V1; 6511 6512 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6513 { 6514 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6515 USHORT usMRS; // mode register 6516 USHORT usEMRS; // extended mode register 6517 UCHAR ucCL; // CAS latency 6518 UCHAR ucWL; // WRITE Latency 6519 UCHAR uctRAS; // tRAS 6520 UCHAR uctRC; // tRC 6521 UCHAR uctRFC; // tRFC 6522 UCHAR uctRCDR; // tRCDR 6523 UCHAR uctRCDW; // tRCDW 6524 UCHAR uctRP; // tRP 6525 UCHAR uctRRD; // tRRD 6526 UCHAR uctWR; // tWR 6527 UCHAR uctWTR; // tWTR 6528 UCHAR uctPDIX; // tPDIX 6529 UCHAR uctFAW; // tFAW 6530 UCHAR uctAOND; // tAOND 6531 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6532 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6533 UCHAR uctCCDL; // 6534 UCHAR uctCRCRL; // 6535 UCHAR uctCRCWL; // 6536 UCHAR uctCKE; // 6537 UCHAR uctCKRSE; // 6538 UCHAR uctCKRSX; // 6539 UCHAR uctFAW32; // 6540 UCHAR ucMR4lo; // 6541 UCHAR ucMR4hi; // 6542 UCHAR ucMR5lo; // 6543 UCHAR ucMR5hi; // 6544 UCHAR ucTerminator; 6545 UCHAR ucReserved; 6546 }ATOM_MEMORY_TIMING_FORMAT_V2; 6547 6548 typedef struct _ATOM_MEMORY_FORMAT 6549 { 6550 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6551 union{ 6552 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6553 USHORT usDDR3_Reserved; // Not used for DDR3 memory 6554 }; 6555 union{ 6556 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6557 USHORT usDDR3_MR3; // Used for DDR3 memory 6558 }; 6559 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6560 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6561 UCHAR ucRow; // Number of Row,in power of 2; 6562 UCHAR ucColumn; // Number of Column,in power of 2; 6563 UCHAR ucBank; // Nunber of Bank; 6564 UCHAR ucRank; // Number of Rank, in power of 2 6565 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6566 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6567 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6568 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6569 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6570 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6571 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6572 }ATOM_MEMORY_FORMAT; 6573 6574 6575 typedef struct _ATOM_VRAM_MODULE_V3 6576 { 6577 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6578 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6579 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6580 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6581 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6582 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6583 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6584 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6585 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6586 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6587 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6588 }ATOM_VRAM_MODULE_V3; 6589 6590 6591 //ATOM_VRAM_MODULE_V3.ucNPL_RT 6592 #define NPL_RT_MASK 0x0f 6593 #define BATTERY_ODT_MASK 0xc0 6594 6595 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6596 6597 typedef struct _ATOM_VRAM_MODULE_V4 6598 { 6599 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6600 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6601 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6602 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6603 USHORT usReserved; 6604 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6605 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6606 UCHAR ucChannelNum; // Number of channels present in this module config 6607 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6608 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6609 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6610 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6611 UCHAR ucVREFI; // board dependent parameter 6612 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6613 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6614 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6615 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6616 UCHAR ucReserved[3]; 6617 6618 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6619 union{ 6620 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6621 USHORT usDDR3_Reserved; 6622 }; 6623 union{ 6624 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6625 USHORT usDDR3_MR3; // Used for DDR3 memory 6626 }; 6627 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6628 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6629 UCHAR ucReserved2[2]; 6630 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6631 }ATOM_VRAM_MODULE_V4; 6632 6633 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6634 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6635 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6636 #define VRAM_MODULE_V4_MISC_BL8 0x4 6637 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6638 6639 typedef struct _ATOM_VRAM_MODULE_V5 6640 { 6641 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6642 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6643 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6644 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6645 USHORT usReserved; 6646 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6647 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6648 UCHAR ucChannelNum; // Number of channels present in this module config 6649 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6650 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6651 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6652 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6653 UCHAR ucVREFI; // board dependent parameter 6654 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6655 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6656 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6657 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6658 UCHAR ucReserved[3]; 6659 6660 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6661 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6662 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6663 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6664 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6665 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6666 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6667 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6668 }ATOM_VRAM_MODULE_V5; 6669 6670 typedef struct _ATOM_VRAM_MODULE_V6 6671 { 6672 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6673 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6674 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6675 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6676 USHORT usReserved; 6677 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6678 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6679 UCHAR ucChannelNum; // Number of channels present in this module config 6680 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6681 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6682 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6683 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6684 UCHAR ucVREFI; // board dependent parameter 6685 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6686 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6687 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6688 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6689 UCHAR ucReserved[3]; 6690 6691 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6692 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6693 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6694 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6695 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6696 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6697 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6698 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6699 }ATOM_VRAM_MODULE_V6; 6700 6701 typedef struct _ATOM_VRAM_MODULE_V7 6702 { 6703 // Design Specific Values 6704 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6705 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6706 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6707 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6708 UCHAR ucExtMemoryID; // Current memory module ID 6709 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6710 UCHAR ucChannelNum; // Number of mem. channels supported in this module 6711 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6712 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6713 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6714 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6715 UCHAR ucVREFI; // Not used. 6716 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6717 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6718 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6719 USHORT usSEQSettingOffset; 6720 UCHAR ucReserved; 6721 // Memory Module specific values 6722 USHORT usEMRS2Value; // EMRS2/MR2 Value. 6723 USHORT usEMRS3Value; // EMRS3/MR3 Value. 6724 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6725 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6726 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6727 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6728 char strMemPNString[20]; // part number end with '0'. 6729 }ATOM_VRAM_MODULE_V7; 6730 6731 typedef struct _ATOM_VRAM_INFO_V2 6732 { 6733 ATOM_COMMON_TABLE_HEADER sHeader; 6734 UCHAR ucNumOfVRAMModule; 6735 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6736 }ATOM_VRAM_INFO_V2; 6737 6738 typedef struct _ATOM_VRAM_INFO_V3 6739 { 6740 ATOM_COMMON_TABLE_HEADER sHeader; 6741 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6742 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6743 USHORT usRerseved; 6744 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6745 UCHAR ucNumOfVRAMModule; 6746 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6747 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6748 // ATOM_INIT_REG_BLOCK aMemAdjust; 6749 }ATOM_VRAM_INFO_V3; 6750 6751 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6752 6753 typedef struct _ATOM_VRAM_INFO_V4 6754 { 6755 ATOM_COMMON_TABLE_HEADER sHeader; 6756 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6757 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6758 USHORT usRerseved; 6759 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6760 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6761 UCHAR ucReservde[4]; 6762 UCHAR ucNumOfVRAMModule; 6763 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6764 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6765 // ATOM_INIT_REG_BLOCK aMemAdjust; 6766 }ATOM_VRAM_INFO_V4; 6767 6768 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6769 { 6770 ATOM_COMMON_TABLE_HEADER sHeader; 6771 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6772 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6773 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6774 USHORT usReserved[3]; 6775 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6776 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6777 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6778 UCHAR ucReserved; 6779 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6780 }ATOM_VRAM_INFO_HEADER_V2_1; 6781 6782 6783 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6784 { 6785 ATOM_COMMON_TABLE_HEADER sHeader; 6786 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6787 }ATOM_VRAM_GPIO_DETECTION_INFO; 6788 6789 6790 typedef struct _ATOM_MEMORY_TRAINING_INFO 6791 { 6792 ATOM_COMMON_TABLE_HEADER sHeader; 6793 UCHAR ucTrainingLoop; 6794 UCHAR ucReserved[3]; 6795 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6796 }ATOM_MEMORY_TRAINING_INFO; 6797 6798 6799 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 6800 { 6801 UCHAR ucControl; 6802 UCHAR ucData; 6803 UCHAR ucSatus; 6804 UCHAR ucTemp; 6805 } SW_I2C_CNTL_DATA_PARAMETERS; 6806 6807 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6808 6809 typedef struct _SW_I2C_IO_DATA_PARAMETERS 6810 { 6811 USHORT GPIO_Info; 6812 UCHAR ucAct; 6813 UCHAR ucData; 6814 } SW_I2C_IO_DATA_PARAMETERS; 6815 6816 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6817 6818 /****************************SW I2C CNTL DEFINITIONS**********************/ 6819 #define SW_I2C_IO_RESET 0 6820 #define SW_I2C_IO_GET 1 6821 #define SW_I2C_IO_DRIVE 2 6822 #define SW_I2C_IO_SET 3 6823 #define SW_I2C_IO_START 4 6824 6825 #define SW_I2C_IO_CLOCK 0 6826 #define SW_I2C_IO_DATA 0x80 6827 6828 #define SW_I2C_IO_ZERO 0 6829 #define SW_I2C_IO_ONE 0x100 6830 6831 #define SW_I2C_CNTL_READ 0 6832 #define SW_I2C_CNTL_WRITE 1 6833 #define SW_I2C_CNTL_START 2 6834 #define SW_I2C_CNTL_STOP 3 6835 #define SW_I2C_CNTL_OPEN 4 6836 #define SW_I2C_CNTL_CLOSE 5 6837 #define SW_I2C_CNTL_WRITE1BIT 6 6838 6839 //==============================VESA definition Portion=============================== 6840 #define VESA_OEM_PRODUCT_REV "01.00" 6841 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6842 #define VESA_MODE_WIN_ATTRIBUTE 7 6843 #define VESA_WIN_SIZE 64 6844 6845 typedef struct _PTR_32_BIT_STRUCTURE 6846 { 6847 USHORT Offset16; 6848 USHORT Segment16; 6849 } PTR_32_BIT_STRUCTURE; 6850 6851 typedef union _PTR_32_BIT_UNION 6852 { 6853 PTR_32_BIT_STRUCTURE SegmentOffset; 6854 ULONG Ptr32_Bit; 6855 } PTR_32_BIT_UNION; 6856 6857 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6858 { 6859 UCHAR VbeSignature[4]; 6860 USHORT VbeVersion; 6861 PTR_32_BIT_UNION OemStringPtr; 6862 UCHAR Capabilities[4]; 6863 PTR_32_BIT_UNION VideoModePtr; 6864 USHORT TotalMemory; 6865 } VBE_1_2_INFO_BLOCK_UPDATABLE; 6866 6867 6868 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6869 { 6870 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6871 USHORT OemSoftRev; 6872 PTR_32_BIT_UNION OemVendorNamePtr; 6873 PTR_32_BIT_UNION OemProductNamePtr; 6874 PTR_32_BIT_UNION OemProductRevPtr; 6875 } VBE_2_0_INFO_BLOCK_UPDATABLE; 6876 6877 typedef union _VBE_VERSION_UNION 6878 { 6879 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6880 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6881 } VBE_VERSION_UNION; 6882 6883 typedef struct _VBE_INFO_BLOCK 6884 { 6885 VBE_VERSION_UNION UpdatableVBE_Info; 6886 UCHAR Reserved[222]; 6887 UCHAR OemData[256]; 6888 } VBE_INFO_BLOCK; 6889 6890 typedef struct _VBE_FP_INFO 6891 { 6892 USHORT HSize; 6893 USHORT VSize; 6894 USHORT FPType; 6895 UCHAR RedBPP; 6896 UCHAR GreenBPP; 6897 UCHAR BlueBPP; 6898 UCHAR ReservedBPP; 6899 ULONG RsvdOffScrnMemSize; 6900 ULONG RsvdOffScrnMEmPtr; 6901 UCHAR Reserved[14]; 6902 } VBE_FP_INFO; 6903 6904 typedef struct _VESA_MODE_INFO_BLOCK 6905 { 6906 // Mandatory information for all VBE revisions 6907 USHORT ModeAttributes; // dw ? ; mode attributes 6908 UCHAR WinAAttributes; // db ? ; window A attributes 6909 UCHAR WinBAttributes; // db ? ; window B attributes 6910 USHORT WinGranularity; // dw ? ; window granularity 6911 USHORT WinSize; // dw ? ; window size 6912 USHORT WinASegment; // dw ? ; window A start segment 6913 USHORT WinBSegment; // dw ? ; window B start segment 6914 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6915 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6916 6917 //; Mandatory information for VBE 1.2 and above 6918 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6919 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6920 UCHAR XCharSize; // db ? ; character cell width in pixels 6921 UCHAR YCharSize; // db ? ; character cell height in pixels 6922 UCHAR NumberOfPlanes; // db ? ; number of memory planes 6923 UCHAR BitsPerPixel; // db ? ; bits per pixel 6924 UCHAR NumberOfBanks; // db ? ; number of banks 6925 UCHAR MemoryModel; // db ? ; memory model type 6926 UCHAR BankSize; // db ? ; bank size in KB 6927 UCHAR NumberOfImagePages;// db ? ; number of images 6928 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6929 6930 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 6931 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6932 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6933 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6934 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6935 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6936 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6937 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6938 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6939 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6940 6941 //; Mandatory information for VBE 2.0 and above 6942 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6943 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6944 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6945 6946 //; Mandatory information for VBE 3.0 and above 6947 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6948 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6949 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6950 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6951 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6952 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6953 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6954 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6955 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6956 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6957 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6958 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6959 UCHAR Reserved; // db 190 dup (0) 6960 } VESA_MODE_INFO_BLOCK; 6961 6962 // BIOS function CALLS 6963 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6964 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6965 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6966 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6967 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6968 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6969 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6970 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6971 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 6972 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6973 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6974 6975 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6976 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6977 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6978 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6979 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6980 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6981 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6982 6983 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6984 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6985 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6986 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6987 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6988 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6989 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6990 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6991 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6992 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6993 6994 6995 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6996 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6997 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6998 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6999 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 7000 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 7001 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 7002 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 7003 7004 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 7005 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 7006 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 7007 7008 // structure used for VBIOS only 7009 7010 //DispOutInfoTable 7011 typedef struct _ASIC_TRANSMITTER_INFO 7012 { 7013 USHORT usTransmitterObjId; 7014 USHORT usSupportDevice; 7015 UCHAR ucTransmitterCmdTblId; 7016 UCHAR ucConfig; 7017 UCHAR ucEncoderID; //available 1st encoder ( default ) 7018 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 7019 UCHAR uc2ndEncoderID; 7020 UCHAR ucReserved; 7021 }ASIC_TRANSMITTER_INFO; 7022 7023 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 7024 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 7025 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 7026 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 7027 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 7028 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 7029 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 7030 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 7031 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 7032 7033 typedef struct _ASIC_ENCODER_INFO 7034 { 7035 UCHAR ucEncoderID; 7036 UCHAR ucEncoderConfig; 7037 USHORT usEncoderCmdTblId; 7038 }ASIC_ENCODER_INFO; 7039 7040 typedef struct _ATOM_DISP_OUT_INFO 7041 { 7042 ATOM_COMMON_TABLE_HEADER sHeader; 7043 USHORT ptrTransmitterInfo; 7044 USHORT ptrEncoderInfo; 7045 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7046 ASIC_ENCODER_INFO asEncoderInfo[1]; 7047 }ATOM_DISP_OUT_INFO; 7048 7049 typedef struct _ATOM_DISP_OUT_INFO_V2 7050 { 7051 ATOM_COMMON_TABLE_HEADER sHeader; 7052 USHORT ptrTransmitterInfo; 7053 USHORT ptrEncoderInfo; 7054 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7055 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7056 ASIC_ENCODER_INFO asEncoderInfo[1]; 7057 }ATOM_DISP_OUT_INFO_V2; 7058 7059 7060 typedef struct _ATOM_DISP_CLOCK_ID { 7061 UCHAR ucPpllId; 7062 UCHAR ucPpllAttribute; 7063 }ATOM_DISP_CLOCK_ID; 7064 7065 // ucPpllAttribute 7066 #define CLOCK_SOURCE_SHAREABLE 0x01 7067 #define CLOCK_SOURCE_DP_MODE 0x02 7068 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 7069 7070 //DispOutInfoTable 7071 typedef struct _ASIC_TRANSMITTER_INFO_V2 7072 { 7073 USHORT usTransmitterObjId; 7074 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 7075 UCHAR ucTransmitterCmdTblId; 7076 UCHAR ucConfig; 7077 UCHAR ucEncoderID; // available 1st encoder ( default ) 7078 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 7079 UCHAR uc2ndEncoderID; 7080 UCHAR ucReserved; 7081 }ASIC_TRANSMITTER_INFO_V2; 7082 7083 typedef struct _ATOM_DISP_OUT_INFO_V3 7084 { 7085 ATOM_COMMON_TABLE_HEADER sHeader; 7086 USHORT ptrTransmitterInfo; 7087 USHORT ptrEncoderInfo; 7088 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7089 USHORT usReserved; 7090 UCHAR ucDCERevision; 7091 UCHAR ucMaxDispEngineNum; 7092 UCHAR ucMaxActiveDispEngineNum; 7093 UCHAR ucMaxPPLLNum; 7094 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7095 UCHAR ucDispCaps; 7096 UCHAR ucReserved[2]; 7097 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 7098 }ATOM_DISP_OUT_INFO_V3; 7099 7100 //ucDispCaps 7101 #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 7102 #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 7103 7104 typedef enum CORE_REF_CLK_SOURCE{ 7105 CLOCK_SRC_XTALIN=0, 7106 CLOCK_SRC_XO_IN=1, 7107 CLOCK_SRC_XO_IN2=2, 7108 }CORE_REF_CLK_SOURCE; 7109 7110 // DispDevicePriorityInfo 7111 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 7112 { 7113 ATOM_COMMON_TABLE_HEADER sHeader; 7114 USHORT asDevicePriority[16]; 7115 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 7116 7117 //ProcessAuxChannelTransactionTable 7118 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7119 { 7120 USHORT lpAuxRequest; 7121 USHORT lpDataOut; 7122 UCHAR ucChannelID; 7123 union 7124 { 7125 UCHAR ucReplyStatus; 7126 UCHAR ucDelay; 7127 }; 7128 UCHAR ucDataOutLen; 7129 UCHAR ucReserved; 7130 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 7131 7132 //ProcessAuxChannelTransactionTable 7133 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 7134 { 7135 USHORT lpAuxRequest; 7136 USHORT lpDataOut; 7137 UCHAR ucChannelID; 7138 union 7139 { 7140 UCHAR ucReplyStatus; 7141 UCHAR ucDelay; 7142 }; 7143 UCHAR ucDataOutLen; 7144 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 7145 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 7146 7147 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7148 7149 //GetSinkType 7150 7151 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 7152 { 7153 USHORT ucLinkClock; 7154 union 7155 { 7156 UCHAR ucConfig; // for DP training command 7157 UCHAR ucI2cId; // use for GET_SINK_TYPE command 7158 }; 7159 UCHAR ucAction; 7160 UCHAR ucStatus; 7161 UCHAR ucLaneNum; 7162 UCHAR ucReserved[2]; 7163 }DP_ENCODER_SERVICE_PARAMETERS; 7164 7165 // ucAction 7166 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 7167 /* obselete */ 7168 #define ATOM_DP_ACTION_TRAINING_START 0x02 7169 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 7170 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 7171 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 7172 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 7173 #define ATOM_DP_ACTION_BLANKING 0x07 7174 7175 // ucConfig 7176 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 7177 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 7178 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 7179 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 7180 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 7181 #define ATOM_DP_CONFIG_LINK_A 0x00 7182 #define ATOM_DP_CONFIG_LINK_B 0x04 7183 /* /obselete */ 7184 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 7185 7186 7187 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 7188 { 7189 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7190 UCHAR ucAuxId; 7191 UCHAR ucAction; 7192 UCHAR ucSinkType; // Iput and Output parameters. 7193 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7194 UCHAR ucReserved[2]; 7195 }DP_ENCODER_SERVICE_PARAMETERS_V2; 7196 7197 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 7198 { 7199 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 7200 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 7201 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 7202 7203 // ucAction 7204 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 7205 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 7206 7207 7208 // DP_TRAINING_TABLE 7209 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 7210 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 7211 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 7212 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 7213 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 7214 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 7215 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 7216 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 7217 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 7218 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 7219 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 7220 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 7221 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 7222 7223 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7224 { 7225 UCHAR ucI2CSpeed; 7226 union 7227 { 7228 UCHAR ucRegIndex; 7229 UCHAR ucStatus; 7230 }; 7231 USHORT lpI2CDataOut; 7232 UCHAR ucFlag; 7233 UCHAR ucTransBytes; 7234 UCHAR ucSlaveAddr; 7235 UCHAR ucLineNumber; 7236 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 7237 7238 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7239 7240 //ucFlag 7241 #define HW_I2C_WRITE 1 7242 #define HW_I2C_READ 0 7243 #define I2C_2BYTE_ADDR 0x02 7244 7245 /****************************************************************************/ 7246 // Structures used by HW_Misc_OperationTable 7247 /****************************************************************************/ 7248 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 7249 { 7250 UCHAR ucCmd; // Input: To tell which action to take 7251 UCHAR ucReserved[3]; 7252 ULONG ulReserved; 7253 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 7254 7255 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 7256 { 7257 UCHAR ucReturnCode; // Output: Return value base on action was taken 7258 UCHAR ucReserved[3]; 7259 ULONG ulReserved; 7260 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 7261 7262 // Actions code 7263 #define ATOM_GET_SDI_SUPPORT 0xF0 7264 7265 // Return code 7266 #define ATOM_UNKNOWN_CMD 0 7267 #define ATOM_FEATURE_NOT_SUPPORTED 1 7268 #define ATOM_FEATURE_SUPPORTED 2 7269 7270 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 7271 { 7272 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 7273 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 7274 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 7275 7276 /****************************************************************************/ 7277 7278 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 7279 { 7280 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 7281 UCHAR ucReserved[3]; 7282 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 7283 7284 #define HWBLKINST_INSTANCE_MASK 0x07 7285 #define HWBLKINST_HWBLK_MASK 0xF0 7286 #define HWBLKINST_HWBLK_SHIFT 0x04 7287 7288 //ucHWBlock 7289 #define SELECT_DISP_ENGINE 0 7290 #define SELECT_DISP_PLL 1 7291 #define SELECT_DCIO_UNIPHY_LINK0 2 7292 #define SELECT_DCIO_UNIPHY_LINK1 3 7293 #define SELECT_DCIO_IMPCAL 4 7294 #define SELECT_DCIO_DIG 6 7295 #define SELECT_CRTC_PIXEL_RATE 7 7296 #define SELECT_VGA_BLK 8 7297 7298 // DIGTransmitterInfoTable structure used to program UNIPHY settings 7299 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 7300 ATOM_COMMON_TABLE_HEADER sHeader; 7301 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7302 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7303 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7304 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7305 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7306 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 7307 7308 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 7309 ATOM_COMMON_TABLE_HEADER sHeader; 7310 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7311 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7312 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7313 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7314 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7315 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7316 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7317 }DIG_TRANSMITTER_INFO_HEADER_V3_2; 7318 7319 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 7320 USHORT usRegisterIndex; 7321 UCHAR ucStartBit; 7322 UCHAR ucEndBit; 7323 }CLOCK_CONDITION_REGESTER_INFO; 7324 7325 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 7326 USHORT usMaxClockFreq; 7327 UCHAR ucEncodeMode; 7328 UCHAR ucPhySel; 7329 ULONG ulAnalogSetting[1]; 7330 }CLOCK_CONDITION_SETTING_ENTRY; 7331 7332 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 7333 USHORT usEntrySize; 7334 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 7335 }CLOCK_CONDITION_SETTING_INFO; 7336 7337 typedef struct _PHY_CONDITION_REG_VAL{ 7338 ULONG ulCondition; 7339 ULONG ulRegVal; 7340 }PHY_CONDITION_REG_VAL; 7341 7342 typedef struct _PHY_CONDITION_REG_VAL_V2{ 7343 ULONG ulCondition; 7344 UCHAR ucCondition2; 7345 ULONG ulRegVal; 7346 }PHY_CONDITION_REG_VAL_V2; 7347 7348 typedef struct _PHY_CONDITION_REG_INFO{ 7349 USHORT usRegIndex; 7350 USHORT usSize; 7351 PHY_CONDITION_REG_VAL asRegVal[1]; 7352 }PHY_CONDITION_REG_INFO; 7353 7354 typedef struct _PHY_CONDITION_REG_INFO_V2{ 7355 USHORT usRegIndex; 7356 USHORT usSize; 7357 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 7358 }PHY_CONDITION_REG_INFO_V2; 7359 7360 typedef struct _PHY_ANALOG_SETTING_INFO{ 7361 UCHAR ucEncodeMode; 7362 UCHAR ucPhySel; 7363 USHORT usSize; 7364 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 7365 }PHY_ANALOG_SETTING_INFO; 7366 7367 typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 7368 UCHAR ucEncodeMode; 7369 UCHAR ucPhySel; 7370 USHORT usSize; 7371 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 7372 }PHY_ANALOG_SETTING_INFO_V2; 7373 7374 typedef struct _GFX_HAVESTING_PARAMETERS { 7375 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 7376 UCHAR ucReserved; //reserved 7377 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 7378 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 7379 } GFX_HAVESTING_PARAMETERS; 7380 7381 //ucGfxBlkId 7382 #define GFX_HARVESTING_CU_ID 0 7383 #define GFX_HARVESTING_RB_ID 1 7384 #define GFX_HARVESTING_PRIM_ID 2 7385 7386 /****************************************************************************/ 7387 //Portion VI: Definitinos for vbios MC scratch registers that driver used 7388 /****************************************************************************/ 7389 7390 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 7391 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 7392 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 7393 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 7394 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 7395 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 7396 #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 7397 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 7398 7399 #define ATOM_MEM_TYPE_DDR_STRING "DDR" 7400 #define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 7401 #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 7402 #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 7403 #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 7404 #define ATOM_MEM_TYPE_HBM_STRING "HBM" 7405 #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 7406 7407 /****************************************************************************/ 7408 //Portion VI: Definitinos being oboselete 7409 /****************************************************************************/ 7410 7411 //========================================================================================== 7412 //Remove the definitions below when driver is ready! 7413 typedef struct _ATOM_DAC_INFO 7414 { 7415 ATOM_COMMON_TABLE_HEADER sHeader; 7416 USHORT usMaxFrequency; // in 10kHz unit 7417 USHORT usReserved; 7418 }ATOM_DAC_INFO; 7419 7420 7421 typedef struct _COMPASSIONATE_DATA 7422 { 7423 ATOM_COMMON_TABLE_HEADER sHeader; 7424 7425 //============================== DAC1 portion 7426 UCHAR ucDAC1_BG_Adjustment; 7427 UCHAR ucDAC1_DAC_Adjustment; 7428 USHORT usDAC1_FORCE_Data; 7429 //============================== DAC2 portion 7430 UCHAR ucDAC2_CRT2_BG_Adjustment; 7431 UCHAR ucDAC2_CRT2_DAC_Adjustment; 7432 USHORT usDAC2_CRT2_FORCE_Data; 7433 USHORT usDAC2_CRT2_MUX_RegisterIndex; 7434 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7435 UCHAR ucDAC2_NTSC_BG_Adjustment; 7436 UCHAR ucDAC2_NTSC_DAC_Adjustment; 7437 USHORT usDAC2_TV1_FORCE_Data; 7438 USHORT usDAC2_TV1_MUX_RegisterIndex; 7439 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7440 UCHAR ucDAC2_CV_BG_Adjustment; 7441 UCHAR ucDAC2_CV_DAC_Adjustment; 7442 USHORT usDAC2_CV_FORCE_Data; 7443 USHORT usDAC2_CV_MUX_RegisterIndex; 7444 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7445 UCHAR ucDAC2_PAL_BG_Adjustment; 7446 UCHAR ucDAC2_PAL_DAC_Adjustment; 7447 USHORT usDAC2_TV2_FORCE_Data; 7448 }COMPASSIONATE_DATA; 7449 7450 /****************************Supported Device Info Table Definitions**********************/ 7451 // ucConnectInfo: 7452 // [7:4] - connector type 7453 // = 1 - VGA connector 7454 // = 2 - DVI-I 7455 // = 3 - DVI-D 7456 // = 4 - DVI-A 7457 // = 5 - SVIDEO 7458 // = 6 - COMPOSITE 7459 // = 7 - LVDS 7460 // = 8 - DIGITAL LINK 7461 // = 9 - SCART 7462 // = 0xA - HDMI_type A 7463 // = 0xB - HDMI_type B 7464 // = 0xE - Special case1 (DVI+DIN) 7465 // Others=TBD 7466 // [3:0] - DAC Associated 7467 // = 0 - no DAC 7468 // = 1 - DACA 7469 // = 2 - DACB 7470 // = 3 - External DAC 7471 // Others=TBD 7472 // 7473 7474 typedef struct _ATOM_CONNECTOR_INFO 7475 { 7476 #if ATOM_BIG_ENDIAN 7477 UCHAR bfConnectorType:4; 7478 UCHAR bfAssociatedDAC:4; 7479 #else 7480 UCHAR bfAssociatedDAC:4; 7481 UCHAR bfConnectorType:4; 7482 #endif 7483 }ATOM_CONNECTOR_INFO; 7484 7485 typedef union _ATOM_CONNECTOR_INFO_ACCESS 7486 { 7487 ATOM_CONNECTOR_INFO sbfAccess; 7488 UCHAR ucAccess; 7489 }ATOM_CONNECTOR_INFO_ACCESS; 7490 7491 typedef struct _ATOM_CONNECTOR_INFO_I2C 7492 { 7493 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 7494 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7495 }ATOM_CONNECTOR_INFO_I2C; 7496 7497 7498 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 7499 { 7500 ATOM_COMMON_TABLE_HEADER sHeader; 7501 USHORT usDeviceSupport; 7502 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 7503 }ATOM_SUPPORTED_DEVICES_INFO; 7504 7505 #define NO_INT_SRC_MAPPED 0xFF 7506 7507 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 7508 { 7509 UCHAR ucIntSrcBitmap; 7510 }ATOM_CONNECTOR_INC_SRC_BITMAP; 7511 7512 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 7513 { 7514 ATOM_COMMON_TABLE_HEADER sHeader; 7515 USHORT usDeviceSupport; 7516 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7517 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7518 }ATOM_SUPPORTED_DEVICES_INFO_2; 7519 7520 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 7521 { 7522 ATOM_COMMON_TABLE_HEADER sHeader; 7523 USHORT usDeviceSupport; 7524 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7525 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7526 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 7527 7528 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7529 7530 7531 7532 typedef struct _ATOM_MISC_CONTROL_INFO 7533 { 7534 USHORT usFrequency; 7535 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7536 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7537 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7538 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7539 }ATOM_MISC_CONTROL_INFO; 7540 7541 7542 #define ATOM_MAX_MISC_INFO 4 7543 7544 typedef struct _ATOM_TMDS_INFO 7545 { 7546 ATOM_COMMON_TABLE_HEADER sHeader; 7547 USHORT usMaxFrequency; // in 10Khz 7548 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7549 }ATOM_TMDS_INFO; 7550 7551 7552 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7553 { 7554 UCHAR ucTVStandard; //Same as TV standards defined above, 7555 UCHAR ucPadding[1]; 7556 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 7557 7558 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7559 { 7560 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7561 UCHAR ucPadding[1]; 7562 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7563 7564 typedef union _ATOM_ENCODER_ATTRIBUTE 7565 { 7566 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7567 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7568 }ATOM_ENCODER_ATTRIBUTE; 7569 7570 7571 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7572 { 7573 USHORT usPixelClock; 7574 USHORT usEncoderID; 7575 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7576 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7577 ATOM_ENCODER_ATTRIBUTE usDevAttr; 7578 }DVO_ENCODER_CONTROL_PARAMETERS; 7579 7580 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7581 { 7582 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7583 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7584 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 7585 7586 7587 #define ATOM_XTMDS_ASIC_SI164_ID 1 7588 #define ATOM_XTMDS_ASIC_SI178_ID 2 7589 #define ATOM_XTMDS_ASIC_TFP513_ID 3 7590 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7591 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7592 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 7593 7594 7595 typedef struct _ATOM_XTMDS_INFO 7596 { 7597 ATOM_COMMON_TABLE_HEADER sHeader; 7598 USHORT usSingleLinkMaxFrequency; 7599 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7600 UCHAR ucXtransimitterID; 7601 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7602 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7603 // due to design. This ID is used to alert driver that the sequence is not "standard"! 7604 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7605 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7606 }ATOM_XTMDS_INFO; 7607 7608 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7609 { 7610 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7611 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7612 UCHAR ucPadding[2]; 7613 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7614 7615 /****************************Legacy Power Play Table Definitions **********************/ 7616 7617 //Definitions for ulPowerPlayMiscInfo 7618 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7619 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7620 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7621 7622 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7623 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7624 7625 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7626 7627 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7628 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7629 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7630 7631 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7632 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7633 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7634 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7635 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7636 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7637 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7638 7639 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7640 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7641 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7642 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7643 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7644 7645 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7646 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7647 7648 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7649 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7650 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7651 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7652 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7653 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7654 7655 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7656 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7657 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7658 7659 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7660 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7661 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7662 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7663 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7664 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7665 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7666 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7667 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7668 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7669 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7670 7671 //ucTableFormatRevision=1 7672 //ucTableContentRevision=1 7673 typedef struct _ATOM_POWERMODE_INFO 7674 { 7675 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7676 ULONG ulReserved1; // must set to 0 7677 ULONG ulReserved2; // must set to 0 7678 USHORT usEngineClock; 7679 USHORT usMemoryClock; 7680 UCHAR ucVoltageDropIndex; // index to GPIO table 7681 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7682 UCHAR ucMinTemperature; 7683 UCHAR ucMaxTemperature; 7684 UCHAR ucNumPciELanes; // number of PCIE lanes 7685 }ATOM_POWERMODE_INFO; 7686 7687 //ucTableFormatRevision=2 7688 //ucTableContentRevision=1 7689 typedef struct _ATOM_POWERMODE_INFO_V2 7690 { 7691 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7692 ULONG ulMiscInfo2; 7693 ULONG ulEngineClock; 7694 ULONG ulMemoryClock; 7695 UCHAR ucVoltageDropIndex; // index to GPIO table 7696 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7697 UCHAR ucMinTemperature; 7698 UCHAR ucMaxTemperature; 7699 UCHAR ucNumPciELanes; // number of PCIE lanes 7700 }ATOM_POWERMODE_INFO_V2; 7701 7702 //ucTableFormatRevision=2 7703 //ucTableContentRevision=2 7704 typedef struct _ATOM_POWERMODE_INFO_V3 7705 { 7706 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7707 ULONG ulMiscInfo2; 7708 ULONG ulEngineClock; 7709 ULONG ulMemoryClock; 7710 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7711 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7712 UCHAR ucMinTemperature; 7713 UCHAR ucMaxTemperature; 7714 UCHAR ucNumPciELanes; // number of PCIE lanes 7715 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7716 }ATOM_POWERMODE_INFO_V3; 7717 7718 7719 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7720 7721 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7722 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7723 7724 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7725 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7726 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7727 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7728 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7729 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7730 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7731 7732 7733 typedef struct _ATOM_POWERPLAY_INFO 7734 { 7735 ATOM_COMMON_TABLE_HEADER sHeader; 7736 UCHAR ucOverdriveThermalController; 7737 UCHAR ucOverdriveI2cLine; 7738 UCHAR ucOverdriveIntBitmap; 7739 UCHAR ucOverdriveControllerAddress; 7740 UCHAR ucSizeOfPowerModeEntry; 7741 UCHAR ucNumOfPowerModeEntries; 7742 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7743 }ATOM_POWERPLAY_INFO; 7744 7745 typedef struct _ATOM_POWERPLAY_INFO_V2 7746 { 7747 ATOM_COMMON_TABLE_HEADER sHeader; 7748 UCHAR ucOverdriveThermalController; 7749 UCHAR ucOverdriveI2cLine; 7750 UCHAR ucOverdriveIntBitmap; 7751 UCHAR ucOverdriveControllerAddress; 7752 UCHAR ucSizeOfPowerModeEntry; 7753 UCHAR ucNumOfPowerModeEntries; 7754 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7755 }ATOM_POWERPLAY_INFO_V2; 7756 7757 typedef struct _ATOM_POWERPLAY_INFO_V3 7758 { 7759 ATOM_COMMON_TABLE_HEADER sHeader; 7760 UCHAR ucOverdriveThermalController; 7761 UCHAR ucOverdriveI2cLine; 7762 UCHAR ucOverdriveIntBitmap; 7763 UCHAR ucOverdriveControllerAddress; 7764 UCHAR ucSizeOfPowerModeEntry; 7765 UCHAR ucNumOfPowerModeEntries; 7766 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7767 }ATOM_POWERPLAY_INFO_V3; 7768 7769 7770 // Following definitions are for compatibility issue in different SW components. 7771 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7772 #define Object_Info Object_Header 7773 #define AdjustARB_SEQ MC_InitParameter 7774 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7775 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 7776 #define ASIC_MVDDQ_Info MemoryTrainingInfo 7777 #define SS_Info PPLL_SS_Info 7778 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 7779 #define DispDevicePriorityInfo SaveRestoreInfo 7780 #define DispOutInfo TV_VideoMode 7781 7782 7783 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7784 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7785 7786 //New device naming, remove them when both DAL/VBIOS is ready 7787 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7788 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7789 7790 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7791 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7792 7793 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7794 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7795 7796 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7797 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7798 7799 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7800 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7801 7802 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7803 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7804 7805 #define ATOM_S0_DFP1I ATOM_S0_DFP1 7806 #define ATOM_S0_DFP1X ATOM_S0_DFP2 7807 7808 #define ATOM_S0_DFP2I 0x00200000L 7809 #define ATOM_S0_DFP2Ib2 0x20 7810 7811 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7812 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7813 7814 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7815 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7816 7817 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 7818 7819 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7820 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7821 7822 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7823 7824 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7825 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7826 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7827 7828 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7829 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7830 7831 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 7832 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7833 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7834 7835 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7836 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7837 7838 #define TMDS1XEncoderControl DVOEncoderControl 7839 #define DFP1XOutputControl DVOOutputControl 7840 7841 #define ExternalDFPOutputControl DFP1XOutputControl 7842 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7843 7844 #define DFP1IOutputControl TMDSAOutputControl 7845 #define DFP2IOutputControl LVTMAOutputControl 7846 7847 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7848 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7849 7850 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7851 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7852 7853 #define ucDac1Standard ucDacStandard 7854 #define ucDac2Standard ucDacStandard 7855 7856 #define TMDS1EncoderControl TMDSAEncoderControl 7857 #define TMDS2EncoderControl LVTMAEncoderControl 7858 7859 #define DFP1OutputControl TMDSAOutputControl 7860 #define DFP2OutputControl LVTMAOutputControl 7861 #define CRT1OutputControl DAC1OutputControl 7862 #define CRT2OutputControl DAC2OutputControl 7863 7864 //These two lines will be removed for sure in a few days, will follow up with Michael V. 7865 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7866 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7867 7868 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7869 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7870 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7871 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7872 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7873 7874 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 7875 #define ATOM_DEVICE_TV2_INDEX 0x00000006 7876 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7877 #define ATOM_S0_TV2 0x00100000L 7878 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7879 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7880 7881 // 7882 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7883 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7884 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7885 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7886 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7887 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7888 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7889 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7890 #define ATOM_S2_CV_DPMS_STATE 0x01000000L 7891 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7892 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7893 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7894 7895 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7896 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7897 #define ATOM_S2_TV1_DPMS_STATEb2 0x04 7898 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7899 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7900 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7901 #define ATOM_S2_TV2_DPMS_STATEb2 0x40 7902 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7903 #define ATOM_S2_CV_DPMS_STATEb3 0x01 7904 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7905 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7906 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7907 7908 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7909 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7910 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7911 7912 /*********************************************************************************/ 7913 7914 #pragma pack() // BIOS data must use byte alignment 7915 7916 // 7917 // AMD ACPI Table 7918 // 7919 #pragma pack(1) 7920 7921 typedef struct { 7922 ULONG Signature; 7923 ULONG TableLength; //Length 7924 UCHAR Revision; 7925 UCHAR Checksum; 7926 UCHAR OemId[6]; 7927 UCHAR OemTableId[8]; //UINT64 OemTableId; 7928 ULONG OemRevision; 7929 ULONG CreatorId; 7930 ULONG CreatorRevision; 7931 } AMD_ACPI_DESCRIPTION_HEADER; 7932 /* 7933 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7934 typedef struct { 7935 UINT32 Signature; //0x0 7936 UINT32 Length; //0x4 7937 UINT8 Revision; //0x8 7938 UINT8 Checksum; //0x9 7939 UINT8 OemId[6]; //0xA 7940 UINT64 OemTableId; //0x10 7941 UINT32 OemRevision; //0x18 7942 UINT32 CreatorId; //0x1C 7943 UINT32 CreatorRevision; //0x20 7944 }EFI_ACPI_DESCRIPTION_HEADER; 7945 */ 7946 typedef struct { 7947 AMD_ACPI_DESCRIPTION_HEADER SHeader; 7948 UCHAR TableUUID[16]; //0x24 7949 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure. 7950 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure. 7951 ULONG Reserved[4]; //0x3C 7952 }UEFI_ACPI_VFCT; 7953 7954 typedef struct { 7955 ULONG PCIBus; //0x4C 7956 ULONG PCIDevice; //0x50 7957 ULONG PCIFunction; //0x54 7958 USHORT VendorID; //0x58 7959 USHORT DeviceID; //0x5A 7960 USHORT SSVID; //0x5C 7961 USHORT SSID; //0x5E 7962 ULONG Revision; //0x60 7963 ULONG ImageLength; //0x64 7964 }VFCT_IMAGE_HEADER; 7965 7966 7967 typedef struct { 7968 VFCT_IMAGE_HEADER VbiosHeader; 7969 UCHAR VbiosContent[1]; 7970 }GOP_VBIOS_CONTENT; 7971 7972 typedef struct { 7973 VFCT_IMAGE_HEADER Lib1Header; 7974 UCHAR Lib1Content[1]; 7975 }GOP_LIB1_CONTENT; 7976 7977 #pragma pack() 7978 7979 7980 #endif /* _ATOMBIOS_H */ 7981 7982 #include "pptable.h" 7983 7984