1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "TargetInfo/ARMTargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
27 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegisterBankInfo.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/MC/TargetRegistry.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/ARMTargetParser.h"
45 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/TargetParser.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include <cassert>
55 #include <memory>
56 #include <optional>
57 #include <string>
58
59 using namespace llvm;
60
61 static cl::opt<bool>
62 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
63 cl::desc("Inhibit optimization of S->D register accesses on A15"),
64 cl::init(false));
65
66 static cl::opt<bool>
67 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
68 cl::desc("Run SimplifyCFG after expanding atomic operations"
69 " to make use of cmpxchg flow-based information"),
70 cl::init(true));
71
72 static cl::opt<bool>
73 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
74 cl::desc("Enable ARM load/store optimization pass"),
75 cl::init(true));
76
77 // FIXME: Unify control over GlobalMerge.
78 static cl::opt<cl::boolOrDefault>
79 EnableGlobalMerge("arm-global-merge", cl::Hidden,
80 cl::desc("Enable the global merge pass"));
81
82 namespace llvm {
83 void initializeARMExecutionDomainFixPass(PassRegistry&);
84 }
85
LLVMInitializeARMTarget()86 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
87 // Register the target.
88 RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
89 RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
90 RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
91 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
92
93 PassRegistry &Registry = *PassRegistry::getPassRegistry();
94 initializeGlobalISel(Registry);
95 initializeARMLoadStoreOptPass(Registry);
96 initializeARMPreAllocLoadStoreOptPass(Registry);
97 initializeARMParallelDSPPass(Registry);
98 initializeARMBranchTargetsPass(Registry);
99 initializeARMConstantIslandsPass(Registry);
100 initializeARMExecutionDomainFixPass(Registry);
101 initializeARMExpandPseudoPass(Registry);
102 initializeThumb2SizeReducePass(Registry);
103 initializeMVEVPTBlockPass(Registry);
104 initializeMVETPAndVPTOptimisationsPass(Registry);
105 initializeMVETailPredicationPass(Registry);
106 initializeARMLowOverheadLoopsPass(Registry);
107 initializeARMBlockPlacementPass(Registry);
108 initializeMVEGatherScatterLoweringPass(Registry);
109 initializeARMSLSHardeningPass(Registry);
110 initializeMVELaneInterleavingPass(Registry);
111 initializeARMFixCortexA57AES1742098Pass(Registry);
112 initializeARMDAGToDAGISelPass(Registry);
113 }
114
createTLOF(const Triple & TT)115 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
116 if (TT.isOSBinFormatMachO())
117 return std::make_unique<TargetLoweringObjectFileMachO>();
118 if (TT.isOSWindows())
119 return std::make_unique<TargetLoweringObjectFileCOFF>();
120 return std::make_unique<ARMElfTargetObjectFile>();
121 }
122
123 static ARMBaseTargetMachine::ARMABI
computeTargetABI(const Triple & TT,StringRef CPU,const TargetOptions & Options)124 computeTargetABI(const Triple &TT, StringRef CPU,
125 const TargetOptions &Options) {
126 StringRef ABIName = Options.MCOptions.getABIName();
127
128 if (ABIName.empty())
129 ABIName = ARM::computeDefaultTargetABI(TT, CPU);
130
131 if (ABIName == "aapcs16")
132 return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
133 else if (ABIName.startswith("aapcs"))
134 return ARMBaseTargetMachine::ARM_ABI_AAPCS;
135 else if (ABIName.startswith("apcs"))
136 return ARMBaseTargetMachine::ARM_ABI_APCS;
137
138 llvm_unreachable("Unhandled/unknown ABI Name!");
139 return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
140 }
141
computeDataLayout(const Triple & TT,StringRef CPU,const TargetOptions & Options,bool isLittle)142 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
143 const TargetOptions &Options,
144 bool isLittle) {
145 auto ABI = computeTargetABI(TT, CPU, Options);
146 std::string Ret;
147
148 if (isLittle)
149 // Little endian.
150 Ret += "e";
151 else
152 // Big endian.
153 Ret += "E";
154
155 Ret += DataLayout::getManglingComponent(TT);
156
157 // Pointers are 32 bits and aligned to 32 bits.
158 Ret += "-p:32:32";
159
160 // Function pointers are aligned to 8 bits (because the LSB stores the
161 // ARM/Thumb state).
162 Ret += "-Fi8";
163
164 // ABIs other than APCS have 64 bit integers with natural alignment.
165 if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
166 Ret += "-i64:64";
167
168 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
169 // bits, others to 64 bits. We always try to align to 64 bits.
170 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
171 Ret += "-f64:32:64";
172
173 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
174 // to 64. We always ty to give them natural alignment.
175 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
176 Ret += "-v64:32:64-v128:32:128";
177 else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
178 Ret += "-v128:64:128";
179
180 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
181 // particular hardware support on 32-bit ARM).
182 Ret += "-a:0:32";
183
184 // Integer registers are 32 bits.
185 Ret += "-n32";
186
187 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
188 // aligned everywhere else.
189 if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
190 Ret += "-S128";
191 else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
192 Ret += "-S64";
193 else
194 Ret += "-S32";
195
196 return Ret;
197 }
198
getEffectiveRelocModel(const Triple & TT,std::optional<Reloc::Model> RM)199 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
200 std::optional<Reloc::Model> RM) {
201 if (!RM)
202 // Default relocation model on Darwin is PIC.
203 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
204
205 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
206 assert(TT.isOSBinFormatELF() &&
207 "ROPI/RWPI currently only supported for ELF");
208
209 // DynamicNoPIC is only used on darwin.
210 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
211 return Reloc::Static;
212
213 return *RM;
214 }
215
216 /// Create an ARM architecture model.
217 ///
ARMBaseTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool isLittle)218 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
219 StringRef CPU, StringRef FS,
220 const TargetOptions &Options,
221 std::optional<Reloc::Model> RM,
222 std::optional<CodeModel::Model> CM,
223 CodeGenOpt::Level OL, bool isLittle)
224 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
225 CPU, FS, Options, getEffectiveRelocModel(TT, RM),
226 getEffectiveCodeModel(CM, CodeModel::Small), OL),
227 TargetABI(computeTargetABI(TT, CPU, Options)),
228 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
229
230 // Default to triple-appropriate float ABI
231 if (Options.FloatABIType == FloatABI::Default) {
232 if (isTargetHardFloat())
233 this->Options.FloatABIType = FloatABI::Hard;
234 else
235 this->Options.FloatABIType = FloatABI::Soft;
236 }
237
238 // Default to triple-appropriate EABI
239 if (Options.EABIVersion == EABI::Default ||
240 Options.EABIVersion == EABI::Unknown) {
241 // musl is compatible with glibc with regard to EABI version
242 if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
243 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
244 TargetTriple.getEnvironment() == Triple::MuslEABI ||
245 TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
246 !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
247 this->Options.EABIVersion = EABI::GNU;
248 else
249 this->Options.EABIVersion = EABI::EABI5;
250 }
251
252 if (TT.isOSBinFormatMachO()) {
253 this->Options.TrapUnreachable = true;
254 this->Options.NoTrapAfterNoreturn = true;
255 }
256
257 // ARM supports the debug entry values.
258 setSupportsDebugEntryValues(true);
259
260 initAsmInfo();
261
262 // ARM supports the MachineOutliner.
263 setMachineOutliner(true);
264 setSupportsDefaultOutlining(true);
265 }
266
267 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
268
createMachineFunctionInfo(BumpPtrAllocator & Allocator,const Function & F,const TargetSubtargetInfo * STI) const269 MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
270 BumpPtrAllocator &Allocator, const Function &F,
271 const TargetSubtargetInfo *STI) const {
272 return ARMFunctionInfo::create<ARMFunctionInfo>(
273 Allocator, F, static_cast<const ARMSubtarget *>(STI));
274 }
275
276 const ARMSubtarget *
getSubtargetImpl(const Function & F) const277 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
278 Attribute CPUAttr = F.getFnAttribute("target-cpu");
279 Attribute FSAttr = F.getFnAttribute("target-features");
280
281 std::string CPU =
282 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
283 std::string FS =
284 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
285
286 // FIXME: This is related to the code below to reset the target options,
287 // we need to know whether or not the soft float flag is set on the
288 // function before we can generate a subtarget. We also need to use
289 // it as a key for the subtarget since that can be the only difference
290 // between two functions.
291 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
292 // If the soft float attribute is set on the function turn on the soft float
293 // subtarget feature.
294 if (SoftFloat)
295 FS += FS.empty() ? "+soft-float" : ",+soft-float";
296
297 // Use the optminsize to identify the subtarget, but don't use it in the
298 // feature string.
299 std::string Key = CPU + FS;
300 if (F.hasMinSize())
301 Key += "+minsize";
302
303 auto &I = SubtargetMap[Key];
304 if (!I) {
305 // This needs to be done before we create a new subtarget since any
306 // creation will depend on the TM and the code generation flags on the
307 // function that reside in TargetOptions.
308 resetTargetOptions(F);
309 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
310 F.hasMinSize());
311
312 if (!I->isThumb() && !I->hasARMOps())
313 F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
314 "instructions, but the target does not support ARM mode execution.");
315 }
316
317 return I.get();
318 }
319
320 TargetTransformInfo
getTargetTransformInfo(const Function & F) const321 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
322 return TargetTransformInfo(ARMTTIImpl(this, F));
323 }
324
ARMLETargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)325 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
326 StringRef CPU, StringRef FS,
327 const TargetOptions &Options,
328 std::optional<Reloc::Model> RM,
329 std::optional<CodeModel::Model> CM,
330 CodeGenOpt::Level OL, bool JIT)
331 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
332
ARMBETargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)333 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
334 StringRef CPU, StringRef FS,
335 const TargetOptions &Options,
336 std::optional<Reloc::Model> RM,
337 std::optional<CodeModel::Model> CM,
338 CodeGenOpt::Level OL, bool JIT)
339 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
340
341 namespace {
342
343 /// ARM Code Generator Pass Configuration Options.
344 class ARMPassConfig : public TargetPassConfig {
345 public:
ARMPassConfig(ARMBaseTargetMachine & TM,PassManagerBase & PM)346 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
347 : TargetPassConfig(TM, PM) {}
348
getARMTargetMachine() const349 ARMBaseTargetMachine &getARMTargetMachine() const {
350 return getTM<ARMBaseTargetMachine>();
351 }
352
353 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const354 createMachineScheduler(MachineSchedContext *C) const override {
355 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
356 // add DAG Mutations here.
357 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
358 if (ST.hasFusion())
359 DAG->addMutation(createARMMacroFusionDAGMutation());
360 return DAG;
361 }
362
363 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const364 createPostMachineScheduler(MachineSchedContext *C) const override {
365 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
366 // add DAG Mutations here.
367 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
368 if (ST.hasFusion())
369 DAG->addMutation(createARMMacroFusionDAGMutation());
370 return DAG;
371 }
372
373 void addIRPasses() override;
374 void addCodeGenPrepare() override;
375 bool addPreISel() override;
376 bool addInstSelector() override;
377 bool addIRTranslator() override;
378 bool addLegalizeMachineIR() override;
379 bool addRegBankSelect() override;
380 bool addGlobalInstructionSelect() override;
381 void addPreRegAlloc() override;
382 void addPreSched2() override;
383 void addPreEmitPass() override;
384 void addPreEmitPass2() override;
385
386 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
387 };
388
389 class ARMExecutionDomainFix : public ExecutionDomainFix {
390 public:
391 static char ID;
ARMExecutionDomainFix()392 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
getPassName() const393 StringRef getPassName() const override {
394 return "ARM Execution Domain Fix";
395 }
396 };
397 char ARMExecutionDomainFix::ID;
398
399 } // end anonymous namespace
400
401 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
402 "ARM Execution Domain Fix", false, false)
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)403 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
404 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
405 "ARM Execution Domain Fix", false, false)
406
407 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
408 return new ARMPassConfig(*this, PM);
409 }
410
getCSEConfig() const411 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
412 return getStandardCSEConfigForOpt(TM->getOptLevel());
413 }
414
addIRPasses()415 void ARMPassConfig::addIRPasses() {
416 if (TM->Options.ThreadModel == ThreadModel::Single)
417 addPass(createLowerAtomicPass());
418 else
419 addPass(createAtomicExpandPass());
420
421 // Cmpxchg instructions are often used with a subsequent comparison to
422 // determine whether it succeeded. We can exploit existing control-flow in
423 // ldrex/strex loops to simplify this, but it needs tidying up.
424 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
425 addPass(createCFGSimplificationPass(
426 SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
427 [this](const Function &F) {
428 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
429 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
430 }));
431
432 addPass(createMVEGatherScatterLoweringPass());
433 addPass(createMVELaneInterleavingPass());
434
435 TargetPassConfig::addIRPasses();
436
437 // Run the parallel DSP pass.
438 if (getOptLevel() == CodeGenOpt::Aggressive)
439 addPass(createARMParallelDSPPass());
440
441 // Match complex arithmetic patterns
442 if (TM->getOptLevel() >= CodeGenOpt::Default)
443 addPass(createComplexDeinterleavingPass(TM));
444
445 // Match interleaved memory accesses to ldN/stN intrinsics.
446 if (TM->getOptLevel() != CodeGenOpt::None)
447 addPass(createInterleavedAccessPass());
448
449 // Add Control Flow Guard checks.
450 if (TM->getTargetTriple().isOSWindows())
451 addPass(createCFGuardCheckPass());
452
453 if (TM->Options.JMCInstrument)
454 addPass(createJMCInstrumenterPass());
455 }
456
addCodeGenPrepare()457 void ARMPassConfig::addCodeGenPrepare() {
458 if (getOptLevel() != CodeGenOpt::None)
459 addPass(createTypePromotionLegacyPass());
460 TargetPassConfig::addCodeGenPrepare();
461 }
462
addPreISel()463 bool ARMPassConfig::addPreISel() {
464 if ((TM->getOptLevel() != CodeGenOpt::None &&
465 EnableGlobalMerge == cl::BOU_UNSET) ||
466 EnableGlobalMerge == cl::BOU_TRUE) {
467 // FIXME: This is using the thumb1 only constant value for
468 // maximal global offset for merging globals. We may want
469 // to look into using the old value for non-thumb1 code of
470 // 4095 based on the TargetMachine, but this starts to become
471 // tricky when doing code gen per function.
472 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
473 (EnableGlobalMerge == cl::BOU_UNSET);
474 // Merging of extern globals is enabled by default on non-Mach-O as we
475 // expect it to be generally either beneficial or harmless. On Mach-O it
476 // is disabled as we emit the .subsections_via_symbols directive which
477 // means that merging extern globals is not safe.
478 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
479 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
480 MergeExternalByDefault));
481 }
482
483 if (TM->getOptLevel() != CodeGenOpt::None) {
484 addPass(createHardwareLoopsPass());
485 addPass(createMVETailPredicationPass());
486 // FIXME: IR passes can delete address-taken basic blocks, deleting
487 // corresponding blockaddresses. ARMConstantPoolConstant holds references to
488 // address-taken basic blocks which can be invalidated if the function
489 // containing the blockaddress has already been codegen'd and the basic
490 // block is removed. Work around this by forcing all IR passes to run before
491 // any ISel takes place. We should have a more principled way of handling
492 // this. See D99707 for more details.
493 addPass(createBarrierNoopPass());
494 }
495
496 return false;
497 }
498
addInstSelector()499 bool ARMPassConfig::addInstSelector() {
500 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
501 return false;
502 }
503
addIRTranslator()504 bool ARMPassConfig::addIRTranslator() {
505 addPass(new IRTranslator(getOptLevel()));
506 return false;
507 }
508
addLegalizeMachineIR()509 bool ARMPassConfig::addLegalizeMachineIR() {
510 addPass(new Legalizer());
511 return false;
512 }
513
addRegBankSelect()514 bool ARMPassConfig::addRegBankSelect() {
515 addPass(new RegBankSelect());
516 return false;
517 }
518
addGlobalInstructionSelect()519 bool ARMPassConfig::addGlobalInstructionSelect() {
520 addPass(new InstructionSelect(getOptLevel()));
521 return false;
522 }
523
addPreRegAlloc()524 void ARMPassConfig::addPreRegAlloc() {
525 if (getOptLevel() != CodeGenOpt::None) {
526 if (getOptLevel() == CodeGenOpt::Aggressive)
527 addPass(&MachinePipelinerID);
528
529 addPass(createMVETPAndVPTOptimisationsPass());
530
531 addPass(createMLxExpansionPass());
532
533 if (EnableARMLoadStoreOpt)
534 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
535
536 if (!DisableA15SDOptimization)
537 addPass(createA15SDOptimizerPass());
538 }
539 }
540
addPreSched2()541 void ARMPassConfig::addPreSched2() {
542 if (getOptLevel() != CodeGenOpt::None) {
543 if (EnableARMLoadStoreOpt)
544 addPass(createARMLoadStoreOptimizationPass());
545
546 addPass(new ARMExecutionDomainFix());
547 addPass(createBreakFalseDeps());
548 }
549
550 // Expand some pseudo instructions into multiple instructions to allow
551 // proper scheduling.
552 addPass(createARMExpandPseudoPass());
553
554 if (getOptLevel() != CodeGenOpt::None) {
555 // When optimising for size, always run the Thumb2SizeReduction pass before
556 // IfConversion. Otherwise, check whether IT blocks are restricted
557 // (e.g. in v8, IfConversion depends on Thumb instruction widths)
558 addPass(createThumb2SizeReductionPass([this](const Function &F) {
559 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
560 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
561 }));
562
563 addPass(createIfConverter([](const MachineFunction &MF) {
564 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
565 }));
566 }
567 addPass(createThumb2ITBlockPass());
568
569 // Add both scheduling passes to give the subtarget an opportunity to pick
570 // between them.
571 if (getOptLevel() != CodeGenOpt::None) {
572 addPass(&PostMachineSchedulerID);
573 addPass(&PostRASchedulerID);
574 }
575
576 addPass(createMVEVPTBlockPass());
577 addPass(createARMIndirectThunks());
578 addPass(createARMSLSHardeningPass());
579 }
580
addPreEmitPass()581 void ARMPassConfig::addPreEmitPass() {
582 addPass(createThumb2SizeReductionPass());
583
584 // Constant island pass work on unbundled instructions.
585 addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
586 return MF.getSubtarget<ARMSubtarget>().isThumb2();
587 }));
588
589 // Don't optimize barriers or block placement at -O0.
590 if (getOptLevel() != CodeGenOpt::None) {
591 addPass(createARMBlockPlacementPass());
592 addPass(createARMOptimizeBarriersPass());
593 }
594 }
595
addPreEmitPass2()596 void ARMPassConfig::addPreEmitPass2() {
597 // Inserts fixup instructions before unsafe AES operations. Instructions may
598 // be inserted at the start of blocks and at within blocks so this pass has to
599 // come before those below.
600 addPass(createARMFixCortexA57AES1742098Pass());
601 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
602 // so passes cannot add to the start of basic blocks once this has run.
603 addPass(createARMBranchTargetsPass());
604 // Inserts Constant Islands. Block sizes cannot be increased after this point,
605 // as this may push the branch ranges and load offsets of accessing constant
606 // pools out of range..
607 addPass(createARMConstantIslandPass());
608 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
609 // instructions, but the pseudos all have conservative sizes so that block
610 // sizes will only be decreased by this pass.
611 addPass(createARMLowOverheadLoopsPass());
612
613 if (TM->getTargetTriple().isOSWindows()) {
614 // Identify valid longjmp targets for Windows Control Flow Guard.
615 addPass(createCFGuardLongjmpPass());
616 // Identify valid eh continuation targets for Windows EHCont Guard.
617 addPass(createEHContGuardCatchretPass());
618 }
619 }
620