1 /* $NetBSD: tegra_apbdmareg.h,v 1.2 2017/04/29 11:47:32 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_APBDMAREG_H 30 #define _ARM_TEGRA_APBDMAREG_H 31 32 /* 33 * APB DMA registers 34 */ 35 #define APBDMA_COMMAND_REG 0x00 36 #define APBDMA_COMMAND_GEN __BIT(31) 37 #define APBDMA_STATUS_REG 0x04 38 #define APBDMA_CNTRL_REG 0x10 39 #define APBDMA_IRQ_STA_CPU_REG 0x14 40 #define APBDMA_IRQ_STA_COP_REG 0x18 41 #define APBDMA_IRQ_MASK_REG 0x1c 42 #define APBDMA_IRQ_MASK_SET_REG 0x20 43 #define APBDMA_IRQ_MASK_CLR_REG 0x24 44 #define APBDMA_TRIG_REG 0x28 45 #define APBDMA_CHANNEL_TRIG_REG 0x2c 46 #define APBDMA_DMA_STATUS_REG 0x30 47 #define APBDMA_CHANNEL_EN_REG 0x34 48 #define APBDMA_SECURITY_REG 0x38 49 #define APBDMA_CHANNEL_SWID_REG 0x3c 50 #define APBDMA_CHAN_WT_0_REG 0x44 51 #define APBDMA_CHAN_WT_1_REG 0x48 52 #define APBDMA_CHAN_WT_2_REG 0x4c 53 #define APBDMA_CHAN_WT_3_REG 0x50 54 #define APBDMA_CHANNEL_SWID1_REG 0x54 55 56 /* 57 * APB DMA channel registers 58 */ 59 #define APBDMACHAN_CSR_REG(n) (0x1000 + ((n) * 0x40)) 60 #define APBDMACHAN_CSR_ENB __BIT(31) 61 #define APBDMACHAN_CSR_IE_EOC __BIT(30) 62 #define APBDMACHAN_CSR_HOLD __BIT(29) 63 #define APBDMACHAN_CSR_DIR __BIT(28) 64 #define APBDMACHAN_CSR_ONCE __BIT(27) 65 #define APBDMACHAN_CSR_FLOW __BIT(21) 66 #define APBDMACHAN_CSR_REQ_SEL __BITS(20,16) 67 #define APBDMACHAN_STA_REG(n) (0x1004 + ((n) * 0x40)) 68 #define APBDMACHAN_DMA_BYTE_STA_REG(n) (0x1008 + ((n) * 0x40)) 69 #define APBDMACHAN_CSRE_REG(n) (0x100c + ((n) * 0x40)) 70 #define APBDMACHAN_AHB_PTR_REG(n) (0x1010 + ((n) * 0x40)) 71 #define APBDMACHAN_AHB_PTR_MASK __BITS(31,2) 72 #define APBDMACHAN_AHB_SEQ_REG(n) (0x1014 + ((n) * 0x40)) 73 #define APBDMACHAN_AHB_SEQ_INTR_ENB __BIT(31) 74 #define APBDMACHAN_AHB_SEQ_BUS_WIDTH __BITS(30,28) 75 #define APBDMACHAN_AHB_SEQ_BUS_WIDTH_32 2 76 #define APBDMACHAN_AHB_SEQ_DATA_SWAP __BIT(27) 77 #define APBDMACHAN_AHB_SEQ_BURST __BITS(26,24) 78 #define APBDMACHAN_AHB_SEQ_BURST_1 4 79 #define APBDMACHAN_AHB_SEQ_BURST_4 5 80 #define APBDMACHAN_AHB_SEQ_BURST_8 6 81 #define APBDMACHAN_AHB_SEQ_DBL_BUF __BIT(19) 82 #define APBDMACHAN_AHB_SEQ_WRAP __BITS(18,16) 83 #define APBDMACHAN_AHB_SEQ_WRAP_NO_WRAP 0 84 #define APBDMACHAN_AHB_SEQ_WRAP_32 1 85 #define APBDMACHAN_AHB_SEQ_WRAP_64 2 86 #define APBDMACHAN_AHB_SEQ_WRAP_128 3 87 #define APBDMACHAN_AHB_SEQ_WRAP_256 4 88 #define APBDMACHAN_AHB_SEQ_WRAP_512 5 89 #define APBDMACHAN_AHB_SEQ_WRAP_1024 6 90 #define APBDMACHAN_AHB_SEQ_WRAP_2048 7 91 #define APBDMACHAN_APB_PTR_REG(n) (0x1018 + ((n) * 0x40)) 92 #define APBDMACHAN_APB_PTR_MASK __BITS(31,2) 93 #define APBDMACHAN_APB_SEQ_REG(n) (0x101c + ((n) * 0x40)) 94 #define APBDMACHAN_APB_SEQ_BUS_WIDTH __BITS(30,28) 95 #define APBDMACHAN_APB_SEQ_BUS_WIDTH_8 0 96 #define APBDMACHAN_APB_SEQ_BUS_WIDTH_16 1 97 #define APBDMACHAN_APB_SEQ_BUS_WIDTH_32 2 98 #define APBDMACHAN_APB_SEQ_DATA_SWAP __BIT(27) 99 #define APBDMACHAN_APB_SEQ_WRAP __BITS(18,16) 100 #define APBDMACHAN_APB_SEQ_WRAP_NO_WRAP 0 101 #define APBDMACHAN_APB_SEQ_WRAP_1 1 102 #define APBDMACHAN_APB_SEQ_WRAP_2 2 103 #define APBDMACHAN_APB_SEQ_WRAP_4 3 104 #define APBDMACHAN_APB_SEQ_WRAP_8 4 105 #define APBDMACHAN_APB_SEQ_WRAP_16 5 106 #define APBDMACHAN_APB_SEQ_WRAP_32 6 107 #define APBDMACHAN_APB_SEQ_WRAP_64 7 108 #define APBDMACHAN_WCOUNT_REG(n) (0x1020 + ((n) * 0x40)) 109 #define APBDMACHAN_WORD_REG(n) (0x1024 + ((n) * 0x40)) 110 111 #endif /* _ARM_TEGRA_APBDMAREG_H */ 112