xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/vega12_hwmgr.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: vega12_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2017 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #ifndef _VEGA12_HWMGR_H_
27 #define _VEGA12_HWMGR_H_
28 
29 #include "hwmgr.h"
30 #include "vega12/smu9_driver_if.h"
31 #include "ppatomfwctrl.h"
32 
33 #define VEGA12_MAX_HARDWARE_POWERLEVELS 2
34 
35 #define WaterMarksExist  1
36 #define WaterMarksLoaded 2
37 
38 #define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS   16
39 #define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
40 #define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
41 #define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS     4
42 
43 enum
44 {
45 	GNLD_DPM_PREFETCHER = 0,
46 	GNLD_DPM_GFXCLK,
47 	GNLD_DPM_UCLK,
48 	GNLD_DPM_SOCCLK,
49 	GNLD_DPM_UVD,
50 	GNLD_DPM_VCE,
51 	GNLD_ULV,
52 	GNLD_DPM_MP0CLK,
53 	GNLD_DPM_LINK,
54 	GNLD_DPM_DCEFCLK,
55 	GNLD_DS_GFXCLK,
56 	GNLD_DS_SOCCLK,
57 	GNLD_DS_LCLK,
58 	GNLD_PPT,
59 	GNLD_TDC,
60 	GNLD_THERMAL,
61 	GNLD_GFX_PER_CU_CG,
62 	GNLD_RM,
63 	GNLD_DS_DCEFCLK,
64 	GNLD_ACDC,
65 	GNLD_VR0HOT,
66 	GNLD_VR1HOT,
67 	GNLD_FW_CTF,
68 	GNLD_LED_DISPLAY,
69 	GNLD_FAN_CONTROL,
70 	GNLD_DIDT,
71 	GNLD_GFXOFF,
72 	GNLD_CG,
73 	GNLD_ACG,
74 
75 	GNLD_FEATURES_MAX
76 };
77 
78 
79 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
80 
81 #define SMC_DPM_FEATURES    0x30F
82 
83 struct smu_features {
84 	bool supported;
85 	bool enabled;
86 	bool allowed;
87 	uint32_t smu_feature_id;
88 	uint64_t smu_feature_bitmap;
89 };
90 
91 struct vega12_dpm_level {
92 	bool		enabled;
93 	uint32_t	value;
94 	uint32_t	param1;
95 };
96 
97 #define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
98 #define MAX_REGULAR_DPM_NUMBER 16
99 #define MAX_PCIE_CONF 2
100 #define VEGA12_MINIMUM_ENGINE_CLOCK 2500
101 
102 struct vega12_dpm_state {
103 	uint32_t  soft_min_level;
104 	uint32_t  soft_max_level;
105 	uint32_t  hard_min_level;
106 	uint32_t  hard_max_level;
107 };
108 
109 struct vega12_single_dpm_table {
110 	uint32_t		count;
111 	struct vega12_dpm_state	dpm_state;
112 	struct vega12_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
113 };
114 
115 struct vega12_odn_dpm_control {
116 	uint32_t	count;
117 	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
118 };
119 
120 struct vega12_pcie_table {
121 	uint16_t count;
122 	uint8_t  pcie_gen[MAX_PCIE_CONF];
123 	uint8_t  pcie_lane[MAX_PCIE_CONF];
124 	uint32_t lclk[MAX_PCIE_CONF];
125 };
126 
127 struct vega12_dpm_table {
128 	struct vega12_single_dpm_table  soc_table;
129 	struct vega12_single_dpm_table  gfx_table;
130 	struct vega12_single_dpm_table  mem_table;
131 	struct vega12_single_dpm_table  eclk_table;
132 	struct vega12_single_dpm_table  vclk_table;
133 	struct vega12_single_dpm_table  dclk_table;
134 	struct vega12_single_dpm_table  dcef_table;
135 	struct vega12_single_dpm_table  pixel_table;
136 	struct vega12_single_dpm_table  display_table;
137 	struct vega12_single_dpm_table  phy_table;
138 	struct vega12_pcie_table        pcie_table;
139 };
140 
141 #define VEGA12_MAX_LEAKAGE_COUNT  8
142 struct vega12_leakage_voltage {
143 	uint16_t  count;
144 	uint16_t  leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
145 	uint16_t  actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
146 };
147 
148 struct vega12_display_timing {
149 	uint32_t  min_clock_in_sr;
150 	uint32_t  num_existing_displays;
151 };
152 
153 struct vega12_dpmlevel_enable_mask {
154 	uint32_t  uvd_dpm_enable_mask;
155 	uint32_t  vce_dpm_enable_mask;
156 	uint32_t  samu_dpm_enable_mask;
157 	uint32_t  sclk_dpm_enable_mask;
158 	uint32_t  mclk_dpm_enable_mask;
159 };
160 
161 struct vega12_vbios_boot_state {
162 	bool        bsoc_vddc_lock;
163 	uint8_t     uc_cooling_id;
164 	uint16_t    vddc;
165 	uint16_t    vddci;
166 	uint16_t    mvddc;
167 	uint16_t    vdd_gfx;
168 	uint32_t    gfx_clock;
169 	uint32_t    mem_clock;
170 	uint32_t    soc_clock;
171 	uint32_t    dcef_clock;
172 	uint32_t    eclock;
173 	uint32_t    dclock;
174 	uint32_t    vclock;
175 };
176 
177 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
178 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
179 #define DPMTABLE_UPDATE_SCLK        0x00000004
180 #define DPMTABLE_UPDATE_MCLK        0x00000008
181 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
182 
183 struct vega12_smc_state_table {
184 	uint32_t        soc_boot_level;
185 	uint32_t        gfx_boot_level;
186 	uint32_t        dcef_boot_level;
187 	uint32_t        mem_boot_level;
188 	uint32_t        uvd_boot_level;
189 	uint32_t        vce_boot_level;
190 	uint32_t        gfx_max_level;
191 	uint32_t        mem_max_level;
192 	uint8_t         vr_hot_gpio;
193 	uint8_t         ac_dc_gpio;
194 	uint8_t         therm_out_gpio;
195 	uint8_t         therm_out_polarity;
196 	uint8_t         therm_out_mode;
197 	PPTable_t       pp_table;
198 	Watermarks_t    water_marks_table;
199 	AvfsDebugTable_t avfs_debug_table;
200 	AvfsFuseOverride_t avfs_fuse_override_table;
201 	SmuMetrics_t    smu_metrics;
202 	DriverSmuConfig_t driver_smu_config;
203 	DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
204 	OverDriveTable_t overdrive_table;
205 };
206 
207 struct vega12_mclk_latency_entries {
208 	uint32_t  frequency;
209 	uint32_t  latency;
210 };
211 
212 struct vega12_mclk_latency_table {
213 	uint32_t  count;
214 	struct vega12_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
215 };
216 
217 struct vega12_registry_data {
218 	uint64_t  disallowed_features;
219 	uint8_t   ac_dc_switch_gpio_support;
220 	uint8_t   acg_loop_support;
221 	uint8_t   clock_stretcher_support;
222 	uint8_t   db_ramping_support;
223 	uint8_t   didt_mode;
224 	uint8_t   didt_support;
225 	uint8_t   edc_didt_support;
226 	uint8_t   force_dpm_high;
227 	uint8_t   fuzzy_fan_control_support;
228 	uint8_t   mclk_dpm_key_disabled;
229 	uint8_t   od_state_in_dc_support;
230 	uint8_t   pcie_lane_override;
231 	uint8_t   pcie_speed_override;
232 	uint32_t  pcie_clock_override;
233 	uint8_t   pcie_dpm_key_disabled;
234 	uint8_t   dcefclk_dpm_key_disabled;
235 	uint8_t   prefetcher_dpm_key_disabled;
236 	uint8_t   quick_transition_support;
237 	uint8_t   regulator_hot_gpio_support;
238 	uint8_t   master_deep_sleep_support;
239 	uint8_t   gfx_clk_deep_sleep_support;
240 	uint8_t   sclk_deep_sleep_support;
241 	uint8_t   lclk_deep_sleep_support;
242 	uint8_t   dce_fclk_deep_sleep_support;
243 	uint8_t   sclk_dpm_key_disabled;
244 	uint8_t   sclk_throttle_low_notification;
245 	uint8_t   skip_baco_hardware;
246 	uint8_t   socclk_dpm_key_disabled;
247 	uint8_t   sq_ramping_support;
248 	uint8_t   tcp_ramping_support;
249 	uint8_t   td_ramping_support;
250 	uint8_t   dbr_ramping_support;
251 	uint8_t   gc_didt_support;
252 	uint8_t   psm_didt_support;
253 	uint8_t   thermal_support;
254 	uint8_t   fw_ctf_enabled;
255 	uint8_t   led_dpm_enabled;
256 	uint8_t   fan_control_support;
257 	uint8_t   ulv_support;
258 	uint8_t   odn_feature_enable;
259 	uint8_t   disable_water_mark;
260 	uint8_t   disable_workload_policy;
261 	uint32_t  force_workload_policy_mask;
262 	uint8_t   disable_3d_fs_detection;
263 	uint8_t   disable_pp_tuning;
264 	uint8_t   disable_xlpp_tuning;
265 	uint32_t  perf_ui_tuning_profile_turbo;
266 	uint32_t  perf_ui_tuning_profile_powerSave;
267 	uint32_t  perf_ui_tuning_profile_xl;
268 	uint16_t  zrpm_stop_temp;
269 	uint16_t  zrpm_start_temp;
270 	uint32_t  stable_pstate_sclk_dpm_percentage;
271 	uint8_t   fps_support;
272 	uint8_t   vr0hot;
273 	uint8_t   vr1hot;
274 	uint8_t   disable_auto_wattman;
275 	uint32_t  auto_wattman_debug;
276 	uint32_t  auto_wattman_sample_period;
277 	uint8_t   auto_wattman_threshold;
278 	uint8_t   log_avfs_param;
279 	uint8_t   enable_enginess;
280 	uint8_t   custom_fan_support;
281 	uint8_t   disable_pcc_limit_control;
282 };
283 
284 struct vega12_odn_clock_voltage_dependency_table {
285 	uint32_t count;
286 	struct phm_ppt_v1_clock_voltage_dependency_record
287 		entries[MAX_REGULAR_DPM_NUMBER];
288 };
289 
290 struct vega12_odn_dpm_table {
291 	struct vega12_odn_dpm_control		control_gfxclk_state;
292 	struct vega12_odn_dpm_control		control_memclk_state;
293 	struct phm_odn_clock_levels		odn_core_clock_dpm_levels;
294 	struct phm_odn_clock_levels		odn_memory_clock_dpm_levels;
295 	struct vega12_odn_clock_voltage_dependency_table		vdd_dependency_on_sclk;
296 	struct vega12_odn_clock_voltage_dependency_table		vdd_dependency_on_mclk;
297 	struct vega12_odn_clock_voltage_dependency_table		vdd_dependency_on_socclk;
298 	uint32_t				odn_mclk_min_limit;
299 };
300 
301 struct vega12_odn_fan_table {
302 	uint32_t	target_fan_speed;
303 	uint32_t	target_temperature;
304 	uint32_t	min_performance_clock;
305 	uint32_t	min_fan_limit;
306 	bool		force_fan_pwm;
307 };
308 
309 struct vega12_clock_range {
310 	uint32_t	ACMax;
311 	uint32_t	ACMin;
312 	uint32_t	DCMax;
313 };
314 
315 struct vega12_hwmgr {
316 	struct vega12_dpm_table          dpm_table;
317 	struct vega12_dpm_table          golden_dpm_table;
318 	struct vega12_registry_data      registry_data;
319 	struct vega12_vbios_boot_state   vbios_boot_state;
320 	struct vega12_mclk_latency_table mclk_latency_table;
321 
322 	struct vega12_leakage_voltage    vddc_leakage;
323 
324 	uint32_t                           vddc_control;
325 	struct pp_atomfwctrl_voltage_table vddc_voltage_table;
326 	uint32_t                           mvdd_control;
327 	struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
328 	uint32_t                           vddci_control;
329 	struct pp_atomfwctrl_voltage_table vddci_voltage_table;
330 
331 	uint32_t                           active_auto_throttle_sources;
332 	uint32_t                           water_marks_bitmap;
333 
334 	struct vega12_odn_dpm_table       odn_dpm_table;
335 	struct vega12_odn_fan_table       odn_fan_table;
336 
337 	/* ---- General data ---- */
338 	uint8_t                           need_update_dpm_table;
339 
340 	bool                           cac_enabled;
341 	bool                           battery_state;
342 	bool                           is_tlu_enabled;
343 	bool                           avfs_exist;
344 
345 	uint32_t                       low_sclk_interrupt_threshold;
346 
347 	uint32_t                       total_active_cus;
348 
349 	struct vega12_display_timing display_timing;
350 
351 	/* ---- Vega12 Dyn Register Settings ---- */
352 
353 	uint32_t                       debug_settings;
354 	uint32_t                       lowest_uclk_reserved_for_ulv;
355 	uint32_t                       gfxclk_average_alpha;
356 	uint32_t                       socclk_average_alpha;
357 	uint32_t                       uclk_average_alpha;
358 	uint32_t                       gfx_activity_average_alpha;
359 	uint32_t                       display_voltage_mode;
360 	uint32_t                       dcef_clk_quad_eqn_a;
361 	uint32_t                       dcef_clk_quad_eqn_b;
362 	uint32_t                       dcef_clk_quad_eqn_c;
363 	uint32_t                       disp_clk_quad_eqn_a;
364 	uint32_t                       disp_clk_quad_eqn_b;
365 	uint32_t                       disp_clk_quad_eqn_c;
366 	uint32_t                       pixel_clk_quad_eqn_a;
367 	uint32_t                       pixel_clk_quad_eqn_b;
368 	uint32_t                       pixel_clk_quad_eqn_c;
369 	uint32_t                       phy_clk_quad_eqn_a;
370 	uint32_t                       phy_clk_quad_eqn_b;
371 	uint32_t                       phy_clk_quad_eqn_c;
372 
373 	/* ---- Thermal Temperature Setting ---- */
374 	struct vega12_dpmlevel_enable_mask     dpm_level_enable_mask;
375 
376 	/* ---- Power Gating States ---- */
377 	bool                           uvd_power_gated;
378 	bool                           vce_power_gated;
379 	bool                           samu_power_gated;
380 	bool                           need_long_memory_training;
381 
382 	/* Internal settings to apply the application power optimization parameters */
383 	bool                           apply_optimized_settings;
384 	uint32_t                       disable_dpm_mask;
385 
386 	/* ---- Overdrive next setting ---- */
387 	uint32_t                       apply_overdrive_next_settings_mask;
388 
389 	/* ---- Workload Mask ---- */
390 	uint32_t                       workload_mask;
391 
392 	/* ---- SMU9 ---- */
393 	uint32_t                       smu_version;
394 	struct smu_features            smu_features[GNLD_FEATURES_MAX];
395 	struct vega12_smc_state_table  smc_state_table;
396 
397 	struct vega12_clock_range      clk_range[PPCLK_COUNT];
398 
399 	/* ---- Gfxoff ---- */
400 	bool                           gfxoff_controlled_by_driver;
401 
402 	unsigned long                  metrics_time;
403 	SmuMetrics_t                   metrics_table;
404 };
405 
406 #define VEGA12_DPM2_NEAR_TDP_DEC                      10
407 #define VEGA12_DPM2_ABOVE_SAFE_INC                    5
408 #define VEGA12_DPM2_BELOW_SAFE_INC                    20
409 
410 #define VEGA12_DPM2_LTA_WINDOW_SIZE                   7
411 
412 #define VEGA12_DPM2_LTS_TRUNCATE                      0
413 
414 #define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT            80
415 
416 #define VEGA12_DPM2_MAXPS_PERCENT_M                   90
417 #define VEGA12_DPM2_MAXPS_PERCENT_H                   90
418 
419 #define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN         50
420 
421 #define VEGA12_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
422 #define VEGA12_DPM2_SQ_RAMP_MIN_POWER                 0x12
423 #define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
424 #define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
425 #define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
426 
427 #define VEGA12_VOLTAGE_CONTROL_NONE                   0x0
428 #define VEGA12_VOLTAGE_CONTROL_BY_GPIO                0x1
429 #define VEGA12_VOLTAGE_CONTROL_BY_SVID2               0x2
430 #define VEGA12_VOLTAGE_CONTROL_MERGED                 0x3
431 /* To convert to Q8.8 format for firmware */
432 #define VEGA12_Q88_FORMAT_CONVERSION_UNIT             256
433 
434 #define VEGA12_UNUSED_GPIO_PIN       0x7F
435 
436 #define VEGA12_THERM_OUT_MODE_DISABLE       0x0
437 #define VEGA12_THERM_OUT_MODE_THERM_ONLY    0x1
438 #define VEGA12_THERM_OUT_MODE_THERM_VRHOT   0x2
439 
440 #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT   0xffffffff
441 #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT    0xffffffff
442 
443 #define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
444 #define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
445 #define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
446 #define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
447 #define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
448 #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT         0xffffffff
449 #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT          0xffffffff
450 
451 #define VEGA12_UMD_PSTATE_GFXCLK_LEVEL         0x3
452 #define VEGA12_UMD_PSTATE_SOCCLK_LEVEL         0x3
453 #define VEGA12_UMD_PSTATE_MCLK_LEVEL           0x2
454 #define VEGA12_UMD_PSTATE_UVDCLK_LEVEL         0x3
455 #define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL        0x3
456 
457 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
458 
459 #endif /* _VEGA12_HWMGR_H_ */
460