1 #define NSNAME 8 2 #define NSYM 50 3 #define NREG 32 4 #define NOPROF (1<<0) 5 #define DUPOK (1<<1) 6 7 /* 8 * Register roles are influenced by the compressed extension: 9 * CIW, CL, CS and CB format use only R8-R15 10 * CL and CS floating load/store use only F8-F15 11 * CI and CSS load/store assume stack pointer is R2 12 * C.JAL assumes link register is R1 13 */ 14 enum 15 { 16 REGZERO = 0, /* always zero */ 17 REGLINK = 1, /* call return address */ 18 REGSP = 2, /* stack pointer */ 19 REGSB = 3, /* static base */ 20 REGTMP = 4, /* assembler temporary */ 21 REGEXT = 7, /* extern reg from here down */ 22 REGRET = 8, /* fn return value */ 23 REGARG = 8, /* fn arg value */ 24 REGALLOC = 15, /* highest reg to allocate (allow for RV32E) */ 25 26 FREGRET = 0, /* fn return value */ 27 FREGEXT = 27, /* extern reg from here down */ 28 FREGZERO = 28, 29 FREGHALF = 29, 30 FREGONE = 30, 31 FREGTWO = 31, 32 }; 33 34 enum as 35 { 36 AXXX = 0, 37 38 /* processor instructions */ 39 AADD, 40 AADDW, 41 AAMO_D, 42 AAMO_W, 43 AAND, 44 ABEQ, 45 ABGE, 46 ABGEU, 47 ABLT, 48 ABLTU, 49 ABNE, 50 ACSRRC, 51 ACSRRCI, 52 ACSRRS, 53 ACSRRSI, 54 ACSRRW, 55 ACSRRWI, 56 ADIV, 57 ADIVU, 58 ADIVUW, 59 ADIVW, 60 AFENCE, 61 AFENCE_I, 62 AJAL, 63 AJALR, 64 ALR_D, 65 ALR_W, 66 ALUI, 67 AMOVB, 68 AMOVBU, 69 AMOVH, 70 AMOVHU, 71 AMOV, 72 AMOVW, 73 AMOVWU, 74 AMUL, 75 AMULH, 76 AMULHSU, 77 AMULHU, 78 AMULW, 79 AOR, 80 AREM, 81 AREMU, 82 AREMUW, 83 AREMW, 84 ASC_D, 85 ASC_W, 86 ASLL, 87 ASLLW, 88 ASLT, 89 ASLTU, 90 ASRA, 91 ASRAW, 92 ASRL, 93 ASRLW, 94 ASUB, 95 ASUBW, 96 ASWAP_D, 97 ASWAP_W, 98 ASYS, 99 AXOR, 100 101 /* floating point */ 102 AMOVF, /* FLW, FSW, FSGNJ.S */ 103 AMOVD, /* FLD, FSD, FSGNJ.D */ 104 AMOVFD, /* FCVT.D.S */ 105 AMOVDF, /* FCVT.S.D */ 106 AMOVWF, /* FCVT.S.W */ 107 AMOVUF, /* FCVT.S.WU */ 108 AMOVFW, /* FCVT.W.S */ 109 AMOVWD, /* FCVT.D.W */ 110 AMOVUD, /* FCVT.D.WU */ 111 AMOVDW, /* FCVT.W.D */ 112 AADDF, /* FADD.S */ 113 AADDD, /* FADD.D */ 114 ASUBF, /* FSUB.S */ 115 ASUBD, /* FSUB.D */ 116 AMULF, /* FMUL.S */ 117 AMULD, /* FMUL.D */ 118 ADIVF, /* FDIV.S */ 119 ADIVD, /* FDIV.D */ 120 ACMPLTF, /* FLT.S */ 121 ACMPLTD, /* FLT.D */ 122 ACMPEQF, /* FEQ.S */ 123 ACMPEQD, /* FEQ.D */ 124 ACMPLEF, /* FLE.S */ 125 ACMPLED, /* FLE.S */ 126 127 /* floating point instructions not included */ 128 /* 129 FMADD.S FMADD.D 130 FMSUB.S FMSUB.D 131 FNMSUB.S FNMSUB.D 132 FNMADD.S FNMADD.D 133 FSQRT.S FSQRT.D 134 FSGNJ.S FSGNJ.D 135 FSGNJN.S FSGNJN.D 136 FSGNNX.S FSGNNX.D 137 FMIN.S FMIN.D 138 FMAX.S FMAX.D 139 FMV.X.W 140 FCLASS.S FCLASS.D 141 FCVT.WU.S FCVT.WU.D 142 FMV.W.X 143 */ 144 145 146 /* pseudo-ops */ 147 ABGT, 148 ABGTU, 149 ABLE, 150 ABLEU, 151 ASGT, 152 ASGTU, 153 AJMP, 154 ARET, 155 ANOP, 156 157 /* C compiler pseudo-ops */ 158 ADATA, 159 AGLOBL, 160 AGOK, 161 AHISTORY, 162 ANAME, 163 ATEXT, 164 AWORD, 165 AEND, 166 ADYNT, 167 AINIT, 168 ASIGNAME, 169 170 /* RV64 extension */ 171 ADWORD, 172 AMOVFV, 173 AMOVDV, 174 AMOVVF, 175 AMOVUVF, 176 AMOVVD, 177 AMOVUVD, 178 179 ALAST, 180 }; 181 182 /* type/name */ 183 enum 184 { 185 D_GOK = 0, 186 D_NONE, 187 188 /* name */ 189 D_EXTERN, 190 D_STATIC, 191 D_AUTO, 192 D_PARAM, 193 194 /* type */ 195 D_BRANCH, 196 D_OREG, 197 D_CONST, 198 D_FCONST, 199 D_SCONST, 200 D_REG, 201 D_CTLREG, 202 D_FREG, 203 D_FCREG, 204 D_FILE, 205 D_FILE1, 206 D_VCONST, 207 }; 208 209 /* 210 * this is the ranlib header 211 */ 212 #define SYMDEF "__.SYMDEF" 213 214 /* 215 * this is the simulated IEEE floating point 216 */ 217 typedef struct ieee Ieee; 218 struct ieee 219 { 220 long l; /* contains ls-man 0xffffffff */ 221 long h; /* contains sign 0x80000000 222 exp 0x7ff00000 223 ms-man 0x000fffff */ 224 }; 225