1 /* $NetBSD: sun9i_a80_ccu.h,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _SUN9I_A80_CCU_H 30 #define _SUN9I_A80_CCU_H 31 32 #define A80_RST_BUS_FD 0 33 #define A80_RST_BUS_VE 1 34 #define A80_RST_BUS_GPU_CTRL 2 35 #define A80_RST_BUS_SS 3 36 #define A80_RST_BUS_MMC 4 37 #define A80_RST_BUS_NAND0 5 38 #define A80_RST_BUS_NAND1 6 39 #define A80_RST_BUS_SDRAM 7 40 #define A80_RST_BUS_SATA 8 41 #define A80_RST_BUS_TS 9 42 #define A80_RST_BUS_SPI0 10 43 #define A80_RST_BUS_SPI1 11 44 #define A80_RST_BUS_SPI2 12 45 #define A80_RST_BUS_SPI3 13 46 #define A80_RST_BUS_OTG 14 47 #define A80_RST_BUS_OTG_PHY 15 48 #define A80_RST_BUS_MIPI_HSI 16 49 #define A80_RST_BUS_GMAC 17 50 #define A80_RST_BUS_MSGBOX 18 51 #define A80_RST_BUS_SPINLOCK 19 52 #define A80_RST_BUS_HSTIMER 20 53 #define A80_RST_BUS_DMA 21 54 #define A80_RST_BUS_LCD0 22 55 #define A80_RST_BUS_LCD1 23 56 #define A80_RST_BUS_EDP 24 57 #define A80_RST_BUS_LVDS 25 58 #define A80_RST_BUS_CSI 26 59 #define A80_RST_BUS_HDMI0 27 60 #define A80_RST_BUS_HDMI1 28 61 #define A80_RST_BUS_DE 29 62 #define A80_RST_BUS_MP 30 63 #define A80_RST_BUS_GPU 31 64 #define A80_RST_BUS_MIPI_DSI 32 65 #define A80_RST_BUS_SPDIF 33 66 #define A80_RST_BUS_AC97 34 67 #define A80_RST_BUS_I2S0 35 68 #define A80_RST_BUS_I2S1 36 69 #define A80_RST_BUS_LRADC 37 70 #define A80_RST_BUS_GPADC 38 71 #define A80_RST_BUS_CIR_TX 39 72 #define A80_RST_BUS_I2C0 40 73 #define A80_RST_BUS_I2C1 41 74 #define A80_RST_BUS_I2C2 42 75 #define A80_RST_BUS_I2C3 43 76 #define A80_RST_BUS_I2C4 44 77 #define A80_RST_BUS_UART0 45 78 #define A80_RST_BUS_UART1 46 79 #define A80_RST_BUS_UART2 47 80 #define A80_RST_BUS_UART3 48 81 #define A80_RST_BUS_UART4 49 82 #define A80_RST_BUS_UART5 50 83 84 #define A80_CLK_PLL_C0CPUX 0 85 #define A80_CLK_PLL_C1CPUX 1 86 #define A80_CLK_PLL_AUDIO 2 87 #define A80_CLK_PLL_PERIPH0 3 88 #define A80_CLK_PLL_VE 4 89 #define A80_CLK_PLL_DDR 5 90 #define A80_CLK_PLL_VIDEO0 6 91 #define A80_CLK_PLL_VIDEO1 7 92 #define A80_CLK_PLL_GPU 8 93 #define A80_CLK_PLL_DE 9 94 #define A80_CLK_PLL_ISP 10 95 #define A80_CLK_PLL_PERIPH1 11 96 #define A80_CLK_C0CPUX 12 97 #define A80_CLK_C1CPUX 13 98 #define A80_CLK_ATB0 14 99 #define A80_CLK_AXI0 15 100 #define A80_CLK_ATB1 16 101 #define A80_CLK_AXI1 17 102 #define A80_CLK_GTBUS 18 103 #define A80_CLK_AHB0 19 104 #define A80_CLK_AHB1 20 105 #define A80_CLK_AHB2 21 106 #define A80_CLK_APB0 22 107 #define A80_CLK_APB1 23 108 #define A80_CLK_CCI400 24 109 #define A80_CLK_ATS 25 110 #define A80_CLK_TRACE 26 111 #define A80_CLK_OUT_A 27 112 #define A80_CLK_OUT_B 28 113 #define A80_CLK_NAND0_0 29 114 #define A80_CLK_NAND0_1 30 115 #define A80_CLK_NAND1_0 31 116 #define A80_CLK_NAND1_1 32 117 #define A80_CLK_MMC0 33 118 #define A80_CLK_MMC0_SAMPLE 34 119 #define A80_CLK_MMC0_OUTPUT 35 120 #define A80_CLK_MMC1 36 121 #define A80_CLK_MMC1_SAMPLE 37 122 #define A80_CLK_MMC1_OUTPUT 38 123 #define A80_CLK_MMC2 39 124 #define A80_CLK_MMC2_SAMPLE 40 125 #define A80_CLK_MMC2_OUTPUT 41 126 #define A80_CLK_MMC3 42 127 #define A80_CLK_MMC3_SAMPLE 43 128 #define A80_CLK_MMC3_OUTPUT 44 129 #define A80_CLK_TS 45 130 #define A80_CLK_SS 46 131 #define A80_CLK_SPI0 47 132 #define A80_CLK_SPI1 48 133 #define A80_CLK_SPI2 49 134 #define A80_CLK_SPI3 50 135 #define A80_CLK_I2S0 51 136 #define A80_CLK_I2S1 52 137 #define A80_CLK_SPDIF 53 138 #define A80_CLK_SDRAM 54 139 #define A80_CLK_DE 55 140 #define A80_CLK_EDP 56 141 #define A80_CLK_MP 57 142 #define A80_CLK_LCD0 58 143 #define A80_CLK_LCD1 59 144 #define A80_CLK_MIPI_DSI0 60 145 #define A80_CLK_MIPI_DSI1 61 146 #define A80_CLK_HDMI 62 147 #define A80_CLK_HDMI_SLOW 63 148 #define A80_CLK_MIPI_CSI 64 149 #define A80_CLK_CSI_ISP 65 150 #define A80_CLK_CSI_MISC 66 151 #define A80_CLK_CSI0_MCLK 67 152 #define A80_CLK_CSI1_MCLK 68 153 #define A80_CLK_FD 69 154 #define A80_CLK_VE 70 155 #define A80_CLK_AVS 71 156 #define A80_CLK_GPU_CORE 72 157 #define A80_CLK_GPU_MEMORY 73 158 #define A80_CLK_GPU_AXI 74 159 #define A80_CLK_SATA 75 160 #define A80_CLK_AC97 76 161 #define A80_CLK_MIPI_HSI 77 162 #define A80_CLK_GPADC 78 163 #define A80_CLK_CIR_TX 79 164 #define A80_CLK_BUS_FD 80 165 #define A80_CLK_BUS_VE 81 166 #define A80_CLK_BUS_GPU_CTRL 82 167 #define A80_CLK_BUS_SS 83 168 #define A80_CLK_BUS_MMC 84 169 #define A80_CLK_BUS_NAND0 85 170 #define A80_CLK_BUS_NAND1 86 171 #define A80_CLK_BUS_SDRAM 87 172 #define A80_CLK_BUS_MIPI_HSI 88 173 #define A80_CLK_BUS_SATA 89 174 #define A80_CLK_BUS_TS 90 175 #define A80_CLK_BUS_SPI0 91 176 #define A80_CLK_BUS_SPI1 92 177 #define A80_CLK_BUS_SPI2 93 178 #define A80_CLK_BUS_SPI3 94 179 #define A80_CLK_BUS_OTG 95 180 #define A80_CLK_BUS_USB 96 181 #define A80_CLK_BUS_GMAC 97 182 #define A80_CLK_BUS_MSGBOX 98 183 #define A80_CLK_BUS_SPINLOCK 99 184 #define A80_CLK_BUS_HSTIMER 100 185 #define A80_CLK_BUS_DMA 101 186 #define A80_CLK_BUS_LCD0 102 187 #define A80_CLK_BUS_LCD1 103 188 #define A80_CLK_BUS_EDP 104 189 #define A80_CLK_BUS_CSI 105 190 #define A80_CLK_BUS_HDMI 106 191 #define A80_CLK_BUS_DE 107 192 #define A80_CLK_BUS_MP 108 193 #define A80_CLK_BUS_MIPI_DSI 109 194 #define A80_CLK_BUS_SPDIF 110 195 #define A80_CLK_BUS_PIO 111 196 #define A80_CLK_BUS_AC97 112 197 #define A80_CLK_BUS_I2S0 113 198 #define A80_CLK_BUS_I2S1 114 199 #define A80_CLK_BUS_LRADC 115 200 #define A80_CLK_BUS_GPADC 116 201 #define A80_CLK_BUS_TWD 117 202 #define A80_CLK_BUS_CIR_TX 118 203 #define A80_CLK_BUS_I2C0 119 204 #define A80_CLK_BUS_I2C1 120 205 #define A80_CLK_BUS_I2C2 121 206 #define A80_CLK_BUS_I2C3 122 207 #define A80_CLK_BUS_I2C4 123 208 #define A80_CLK_BUS_UART0 124 209 #define A80_CLK_BUS_UART1 125 210 #define A80_CLK_BUS_UART2 126 211 #define A80_CLK_BUS_UART3 127 212 #define A80_CLK_BUS_UART4 128 213 #define A80_CLK_BUS_UART5 129 214 215 #endif /* !_SUN9I_A80_CCU_H */ 216