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Searched defs:RC (Results 1 – 25 of 141) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/minix3/external/bsd/llvm/dist/llvm/include/llvm/IR/
H A DIRBuilder.h690 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
704 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
712 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
726 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
734 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
748 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
756 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
768 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
780 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
787 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp83 const TargetRegisterClass *RC = in getGlobalBaseReg() local
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg() local
105 const TargetRegisterClass *RC = ST.isABI_N64() ? in createEhDataRegsFI() local
136 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
H A DMipsSEFrameLowering.cpp154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
174 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
197 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
227 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
321 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
382 const TargetRegisterClass *RC = in expandExtractElementF64() local
510 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue() local
576 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitEpilogue() local
624 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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H A DMipsInstrInfo.h93 const TargetRegisterClass *RC, in storeRegToStackSlot()
101 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
H A DTargetRegisterInfo.cpp119 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
132 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
236 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
H A DAggressiveAntiDepBreaker.h43 const TargetRegisterClass *RC; member
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h122 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
128 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
135 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
467 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
493 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
617 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
626 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
638 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
693 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { in avoidWriteAfterWrite()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp140 const TargetRegisterClass *RC in inferRegClassFromUses() local
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef() local
230 const TargetRegisterClass *RC in runOnMachineFunction() local
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction() local
H A DSILowerI1Copies.cpp90 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in runOnMachineFunction() local
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp430 const TargetRegisterClass *RC, in PPCEmitLoad()
573 const TargetRegisterClass *RC = in SelectLoad() local
589 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
939 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1000 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1044 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1132 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1296 const TargetRegisterClass *RC = in processCallArgs() local
1308 const TargetRegisterClass *RC = in processCallArgs() local
1620 const TargetRegisterClass *RC = in SelectRet() local
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/minix3/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses) in runEnums() local
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
964 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1004 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1111 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1148 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1157 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1211 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1238 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1253 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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H A DCodeGenRegisters.cpp859 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
881 for (auto &RC : RegClasses) { in computeSubClasses() local
897 for (auto &RC : RegClasses) in computeSubClasses() local
999 for (auto *RC : RCs) { in CodeGenRegBank() local
1010 for (auto &RC : RegClasses) in CodeGenRegBank() local
1040 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1052 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1068 if (CodeGenRegisterClass *RC = Def2RC[Def]) in getRegClass() local
1602 for (auto &RC : RegClasses) { in computeRegUnitSets() local
1707 for (auto &RC : RegClasses) { in computeRegUnitSets() local
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H A DCodeGenTarget.cpp234 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs() local
249 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes() local
422 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, in LoadIntrinsics()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp74 const TargetRegisterClass *RC, in storeRegToStackSlot()
102 const TargetRegisterClass *RC, in loadRegFromStackSlot()
H A DARMFastISel.cpp289 const TargetRegisterClass *RC, in fastEmitInst_r()
311 const TargetRegisterClass *RC, in fastEmitInst_rr()
339 const TargetRegisterClass *RC, in fastEmitInst_rrr()
371 const TargetRegisterClass *RC, in fastEmitInst_ri()
397 const TargetRegisterClass *RC, in fastEmitInst_rri()
427 const TargetRegisterClass *RC, in fastEmitInst_i()
523 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
539 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
589 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV() local
722 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca() local
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/minix3/external/bsd/llvm/dist/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp187 struct RC final : public RA { struct
188 virtual C *f() { in f()
194 virtual C *operator-() { in operator -()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp40 const TargetRegisterClass *RC, in storeRegToStackSlot()
68 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp369 const TargetRegisterClass *RC = *I; in regPressureDelta() local
376 const TargetRegisterClass *RC = *I; in regPressureDelta() local
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
H A DFastISel.cpp1678 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) { in createResultReg()
1700 const TargetRegisterClass *RC) { in fastEmitInst_()
1709 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_r()
1730 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rr()
1754 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rrr()
1782 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_ri()
1804 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rii()
1829 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rf()
1851 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rri()
1877 const TargetRegisterClass *RC, in fastEmitInst_rrii()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp328 const TargetRegisterClass *RC = nullptr; in X86FastEmitLoad() local
554 const TargetRegisterClass *RC = nullptr; in handleConstantAddresses() local
1460 const TargetRegisterClass *RC = nullptr; in X86SelectShift() local
1544 const TargetRegisterClass *RC; in X86SelectDivRem() member
1703 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect() local
1881 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect() local
1950 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect() local
1978 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect() local
2138 const TargetRegisterClass *RC = nullptr; in fastLowerIntrinsicCall() local
2279 const TargetRegisterClass *RC; in fastLowerIntrinsicCall() local
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp342 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt() local
375 const TargetRegisterClass *RC = Is64Bit ? in materializeFP() local
1247 const TargetRegisterClass *RC = in emitAddSub_rr() local
1289 const TargetRegisterClass *RC; in emitAddSub_ri() local
1328 const TargetRegisterClass *RC = in emitAddSub_rs() local
1365 const TargetRegisterClass *RC = nullptr; in emitAddSub_rx() local
1596 const TargetRegisterClass *RC; in emitLogicalOp_ri() local
1643 const TargetRegisterClass *RC; in emitLogicalOp_rs() local
1740 const TargetRegisterClass *RC; in emitLoad() local
2587 const TargetRegisterClass *RC; in selectSelect() local
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